Anadi Srivastava

Osburn, C. M., De, I., Yee, K. F., & Srivastava, A. (2000). Design and integration considerations for end-of-the roadmap ultrashallow junctions. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, Vol. 18, pp. 338–345. https://doi.org/10.1116/1.591195

De, I., Johri, D., Srivastava, A., & Osburn, C. M. (2000). Impact of gate workfunction on device performance at the 50 nm technology node. SOLID-STATE ELECTRONICS, 44(6), 1077–1080. https://doi.org/10.1016/S0038-1101(99)00323-8

Srivastava, A. (1999). Influence of BJT transit frequency limit relation to MOSFET parameters on the switching speed of BiCMOS digital circuits. VLSI Design (Yverdon, Switzerland), 9(2), 203–211.

Srivastava, A., Heinisch, H. H., Vogel, E., Parker, C., Osburn, C. M., Masnari, N. A., … Hauser, JR. (1998). Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs. RAPID THERMAL AND INTEGRATED PROCESSING VII, Vol. 525, pp. 163–170. https://doi.org/10.1557/proc-525-163

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1998). Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 145(6), 2131–2137. https://doi.org/10.1149/1.1838607

Daubert, C. R., Steffe, J. F., & Srivastava, A. K. (1998). Predicting the electrorheological behavior of milk chocolate. Journal of Food Process Engineering, 21(3), 249–261. https://doi.org/10.1111/j.1745-4530.1998.tb00450.x

Srivastava, A., Sun, J., Bellur, K., Bartholomew, R. F., O'Neil, P., Celik, S. M., … Fowler, B. (1997). A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 144(10), 3659–3664. https://doi.org/10.1149/1.1838066

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

Sun, J. J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., & Masnari, N. A. (1997). The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's. IEEE TRANSACTIONS ON ELECTRON DEVICES, 44(9), 1491–1498. https://doi.org/10.1109/16.622606

Sun, J., Bartholomew, R. F., Bellur, K., ONeil, P. A., Srivastava, A., Violette, K. E., … Masnari, N. A. (1996). Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition. RAPID THERMAL AND INTEGRATED PROCESSING V, Vol. 429, pp. 343–347. https://doi.org/10.1557/proc-429-343