@article{yang_wortman_2001, title={A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs}, volume={41}, ISSN={["0026-2714"]}, DOI={10.1016/S0026-2714(00)00099-8}, abstractNote={This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.}, number={1}, journal={MICROELECTRONICS RELIABILITY}, author={Yang, N and Wortman, JJ}, year={2001}, month={Jan}, pages={37–46} }
 @article{weintraub_vogel_hauser_yang_misra_wortman_ganem_masson_2001, title={Study of low-frequency charge pumping on thin stacked dielectrics}, volume={48}, ISSN={["1557-9646"]}, DOI={10.1109/16.974700}, abstractNote={The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO/sub 2/ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO/sub 2/ dielectrics to thin stacked gate dielectrics are discussed.}, number={12}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Weintraub, CE and Vogel, E and Hauser, JR and Yang, N and Misra, V and Wortman, JJ and Ganem, J and Masson, P}, year={2001}, month={Dec}, pages={2754–2762} }
 @article{yang_henson_wortman_2000, title={A comparative study of gate direct tunneling and drain leakage currents in N-MOSFET's with sub-2-nm gate oxides}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.853042}, abstractNote={This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Wortman, JJ}, year={2000}, month={Aug}, pages={1636–1644} }
 @article{ahmed_wortman_hauser_2000, title={A two-dimensional numerical simulation of pulsed drain current transients in weak inversion and application to interface trap characterization on small geometry MOSFETs with ultrathin oxides}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.877189}, abstractNote={Based on two-dimensional (2-D) numerical simulation, a pulsed-drain current (PDC) measurement technique in weak inversion is investigated as an alternative to the standard charge-pumping technique for the extraction of interface trap density using small geometry MOSFETs. The PDC technique was found particularly useful for small MOSFETs with sub-20 /spl Aring/ oxides to avoid high gate tunneling current effects. The numerical simulation results are in excellent agreement with the simple analytical expressions used in the PDC technique.}, number={11}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Wortman, JJ and Hauser, JR}, year={2000}, month={Nov}, pages={2236–2237} }
 @article{henson_yang_kubicek_vogel_wortman_de meyer_naem_2000, title={Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.848282}, abstractNote={Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Henson, WK and Yang, N and Kubicek, S and Vogel, EM and Wortman, JJ and De Meyer, K and Naem, A}, year={2000}, month={Jul}, pages={1393–1400} }
 @article{ahmed_ibok_bains_chi_ogle_wortman_hauser_2000, title={Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.848276}, abstractNote={In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Bains, G and Chi, D and Ogle, B and Wortman, JJ and Hauser, JR}, year={2000}, month={Jul}, pages={1349–1354} }
 @article{yang_henson_hauser_wortman_2000, title={Estimation of the effects of remote charge scattering on electron mobility of n-MOSFET's with ultrathin gate oxides}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.822292}, abstractNote={The effects of remote charge scattering on the electron mobility of n-MOSFETs with ultrathin gate oxides from 1.5 nm to 3.2 nm have been estimated. By calculating the scattering rate of the two-dimensional (2-D) electron gas at the Si/silicon dioxide interface due to the ionized doping impurities at the poly-Si/silicon dioxide interface, the remote charge scattering mobility has been calculated. Electron mobility measured from the n-MOSFETs with ultrathin gate oxides has been used to extract several known mobility components. These mobility components have been compared to the calculated remote charge scattering mobility. From these comparisons, it is clear that the overall electron mobility is not severely degraded by remote charge scattering for the oxide thickness studied.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={2000}, month={Feb}, pages={440–447} }
 @article{ahmed_de_osburn_wortman_hauser_2000, title={Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.831010}, abstractNote={The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L/sub eff/- and R/sub sd/-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V/sub g/ dependence of L/sub eff/ and R/sub sd/ even for devices with degenerately doped drain junction.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and De, I and Osburn, C and Wortman, J and Hauser, J}, year={2000}, month={Apr}, pages={891–895} }
 @article{ban_ozturk_misra_wortman_venables_maher_1999, title={A low-thermal-budget in situ doped multilayer silicon epitaxy process for MOSFET channel engineering}, volume={146}, ISSN={["0013-4651"]}, DOI={10.1149/1.1391744}, abstractNote={This paper describes an in situ boron‐doped, multilayer epitaxial silicon process that can be used to obtain doping profiles for channels in the deep‐submicron regime. We have extensively studied lightly doped channel structures in which an intrinsic silicon layer is grown on an in situ doped epitaxial silicon film. Low‐thermal‐budget processing is achieved by the ultrahigh‐vacuum rapid thermal chemical vapor deposition technique which combines low‐temperature surface preparation and deposition (≤800°C) while providing high growth rates using disilane . Boron doping is achieved using diborane diluted in hydrogen (500 ppm) as the precursor. Temperature and gas switching are compared in terms of doping transition, interface contamination (carbon and oxygen incorporation), and impurity diffusion upon annealing. Our results reveal that for a contamination‐free epitaxial silicon interface, interfacial carbon contamination must be eliminated or reduced to a minimum level. Using this process, short‐channel n‐channel metal‐oxide semiconductor devices μm) have been fabricated for the first time demonstrating the potential use of the technique. It was found that lightly doped channel metal‐oxide semiconductor field effect transistors are more easily scalable into the 0.1 μm regime with superior short‐channel characteristics. © 1999 The Electrochemical Society. All rights reserved.}, number={3}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Ban, I and Ozturk, MC and Misra, V and Wortman, JJ and Venables, D and Maher, DM}, year={1999}, month={Mar}, pages={1189–1196} }
 @article{masson_morfouli_autran_wortman_1999, title={Electrical characterization of n-channel MOSFETs with oxynitride gate dielectric formed by low-pressure Rapid Thermal Chemical Vapor Deposition}, volume={48}, number={1-4}, journal={Microelectronic Engineering}, author={Masson, P. and Morfouli, P. and Autran, J. L. and Wortman, J. J.}, year={1999}, pages={211–214} }
 @article{masson_morfouli_autran_brini_balland_vogel_wortman_1999, title={Electrical properties of oxynitride thin films using noise and charge pumping measurements}, volume={245}, ISSN={["1873-4812"]}, DOI={10.1016/S0022-3093(98)00870-9}, abstractNote={Slow traps and interface traps density has been measured using low frequency (10 Hz) noise and charge pumping measurements. The study has been carried out on n-channel metal-oxide-semiconductor transistors with ultra thin gate dielectrics prepared by rapid thermal oxidation (RTO) and low pressure rapid thermal chemical vapor deposition. For both deposition methods, the interface trap characteristics have been studied as a function of nitrogen concentration as well as thermal annealing parameters (ambient and temperature). Experimental results have shown that a stacked dielectric combined RTO gate oxide (grown under N2O) and chemical vapor deposition oxynitride (capping layer with 8% atomic nitrogen concentration), offers a solution for gate dielectrics with thickness ⩾2 nm.}, journal={JOURNAL OF NON-CRYSTALLINE SOLIDS}, author={Masson, P and Morfouli, P and Autran, JL and Brini, J and Balland, B and Vogel, EM and Wortman, JJ}, year={1999}, month={Apr}, pages={54–58} }
 @article{henson_ahmed_vogel_hauser_wortman_venables_xu_venables_1999, title={Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.753759}, abstractNote={High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Ahmed, KZ and Vogel, EM and Hauser, JR and Wortman, JJ and Venables, RD and Xu, M and Venables, D}, year={1999}, month={Apr}, pages={179–181} }
 @article{ahmed_ibok_yeap_xiang_ogle_wortman_hauser_1999, title={Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's}, volume={46}, ISSN={["0018-9383"]}, DOI={10.1109/16.777153}, abstractNote={This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Yeap, GCF and Xiang, Q and Ogle, B and Wortman, JJ and Hauser, JR}, year={1999}, month={Aug}, pages={1650–1655} }
 @article{misra_lazar_wang_wu_niimi_lucovsky_wortman_hauser_1999, title={Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition}, volume={17}, number={4}, journal={Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures}, author={Misra, V. and Lazar, H. and Wang, Z. and Wu, Y. and Niimi, H. and Lucovsky, G. and Wortman, J. J. and Hauser, J. R.}, year={1999}, pages={1836–1839} }
 @article{yang_henson_hauser_wortman_1999, title={Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices}, volume={46}, ISSN={["1557-9646"]}, DOI={10.1109/16.772492}, abstractNote={Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={1999}, month={Jul}, pages={1464–1471} }
 @article{shanware_massoud_vogel_henson_hauser_wortman_1999, title={Modeling the trends in valence-band electron tunneling in NMOSFETs with ultrathin SiO2 and SiO2/Ta2O5 dielectrics with oxide scaling}, volume={48}, ISSN={["1873-5568"]}, DOI={10.1016/s0167-9317(99)00392-5}, abstractNote={Gate oxide scaling in NMOSFETs causes electrons to tunnel from the conduction and valence bands of the silicon substrate in the direct-tunneling regime. In NMOSFETs, the tunneling of electrons from the substrate's valence band is a source of the substrate current IB and contributes to the gate current IG. Oxide thickness scaling leads to an increase in the substrate current IB and in the ratio IBIG of substrate to gate current. In this paper, we report the trends in the IBIG ratio due to oxide thickness scaling in ultrathin SiO2 and SiO2Ta2O5 composite gate dielectrics.}, number={1-4}, journal={MICROELECTRONIC ENGINEERING}, author={Shanware, A and Massoud, HZ and Vogel, E and Henson, K and Hauser, JR and Wortman, JJ}, year={1999}, month={Sep}, pages={295–298} }
 @article{henson_yang_wortman_1999, title={Observation of oxide breakdown and its effects on the characteristics of ultra-thin-oxide nMOSFET's}, volume={20}, ISSN={["1558-0563"]}, DOI={10.1109/55.806099}, abstractNote={Ultra-thin gate oxide breakdown in nMOSFET's has been studied for an oxide thickness of 1.5 nm using constant voltage stressing. The pre- and post-oxide breakdown characteristics of the device have been compared, and the results have shown a strong dependence on the breakdown locations. The oxide breakdown near the source/drain-to-gate overlap regions was found to be more severe on the post-breakdown characteristics of the device than breakdown in the channel. This observation may be related to the dependence of breakdown on the distribution of electric field and areas of different regions within the nMOSFET under stress.}, number={12}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Yang, N and Wortman, JJ}, year={1999}, month={Dec}, pages={605–607} }
 @article{shanware_massoud_acker_li_mirabedini_henson_hauser_wortman_1999, title={The effects of Ge content in poly-Si1-xGex gate material on the tunneling barrier in PMOS devices}, volume={48}, ISSN={["0167-9317"]}, DOI={10.1016/s0167-9317(99)00333-0}, abstractNote={The use of SiGe gates in MOSFET technology has promise as a single-gate material for both n- and p-channel MOSFETs. The Ge content in the gate, however, affects the gate energy band diagram. While Ge in the SiGe gate does not affect the conduction-band energy level, it is found to raise the valence-band energy level and reduce the gate bandgap. This change results in an increase in the gate current resulting mainly from the tunneling of electrons from the valence band of the gate in PMOSFETs. This paper reports on the effects of Ge content in SiGe gates on the tunneling characteristics of PMOSFETs.}, number={1-4}, journal={MICROELECTRONIC ENGINEERING}, author={Shanware, A and Massoud, HZ and Acker, A and Li, VZQ and Mirabedini, MR and Henson, K and Hauser, JR and Wortman, JJ}, year={1999}, month={Sep}, pages={39–42} }
 @article{li_mirabedini_vogel_henson_batchelor_wortman_kuehn_1998, title={Effects of Si source gases (SiH4 and Si2H6) on polycrystalline- Si1-xGex deposited on oxide by RTCVD}, volume={1}, number={3}, journal={Electrochemical and Solid State Letters}, author={Li, V. Z. Q. and Mirabedini, M. R. and Vogel, E. and Henson, K. and Batchelor, A. D. and Wortman, J. J. and Kuehn, R. T.}, year={1998}, pages={153–155} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{heinisch_hornung_linkous_craig_mirabedini_wortman_1998, title={Impact of floating gate dopant concentration and interpoly dielectric processing on tunnel dielectric reliability}, volume={145}, ISSN={["0013-4651"]}, DOI={10.1149/1.1838464}, abstractNote={The influence of gate dopant concentration and thermal budget on the reliability of tunnel dielectric films was studied. Metal oxide semiconductor (MOS) capacitors were furnace annealed after gate formation, floating gate devices were fabricated with interpoly dielectric films either grown by furnace oxidation or deposited by rapid thermal chemical vapor deposition (RTCVD); the latter process is associated with a much lower thermal budget. Ion implanted amorphous silicon was employed for the gate electrodes of the MOS capacitors and for the floating gate layers of the memory devices. The reliability of the dielectrics was evaluated under a constant current stress, and the cycling endurance of the floating gate devices was examined. It was found that tap generation and charge trapping increase with increasing annealing time and increasing dopant concentration, while charge to breakdown (Q bd ) decreases with increasing annealing time. The cycling endurance plot for the floating gate devices revealed little distortion of the threshold voltage window for devices with the low thermal budget RTCVD interpoly dielectric film. Based on this study, a low thermal budget process is preferable for the formation of the interpoly dielectric.}, number={4}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Heinisch, HH and Hornung, BE and Linkous, RB and Craig, SA and Mirabedini, MR and Wortman, JJ}, year={1998}, month={Apr}, pages={1351–1355} }
 @article{vogel_ahmed_hornung_henson_mclarty_lucovsky_hauser_wortman_1998, title={Modeled tunnel currents for high dielectric constant dielectrics}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.678572}, abstractNote={The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Vogel, EM and Ahmed, KZ and Hornung, B and Henson, WK and McLarty, PK and Lucovsky, G and Hauser, JR and Wortman, JJ}, year={1998}, month={Jun}, pages={1350–1355} }
 @article{li_mirabedini_hornung_heinisch_xu_batchelor_maher_wortman_kuehn_1998, title={Structure and properties of rapid thermal chemical vapor deposited polycrystalline silicon-germanium films on SiO2 using Si2H6, GeH4, and B2H6 gases}, volume={83}, ISSN={["0021-8979"]}, DOI={10.1063/1.367404}, abstractNote={Deposition of undoped and in situ boron-doped polycrystalline silicon-germanium (poly-Si1−xGex) films on oxide has been investigated at temperatures below 625 °C and a pressure of 4 Torr in a rapid thermal chemical vapor deposition system. The influences of reactant gases such as Si2H6, SiH4, GeH4, and B2H6 on the nucleation behavior, and structural properties of poly-Si1−xGex films formed on oxide were studied. The experimental results showed that in situ boron-doped or undoped poly-Si1−xGex films can be directly deposited on oxide without an initial Si predeposition layer to provide the necessary nucleation sites on the surface when using Si2H6 as the Si source gas. However, when SiH4 was used as the Si source gas, only in situ boron-doped films can be deposited nonselectively on the oxide without the initial Si predeposition layer, and to deposit undoped poly-Si1−xGex films, Si predeposition is needed, otherwise Si1−xGex islands are formed on the oxide. X-ray diffraction analysis showed that poly-Si1−xGex films deposited using Si2H6, GeH4, and B2H6 gas mixture have three singular peaks corresponding to {311}, {220}, and {111} planes, thus indicating the Si1−xGex alloy is formed. In addition, we found that B2H6 gas has a minor effect on the Ge incorporation into the films but reduces the overall deposition rate.}, number={10}, journal={JOURNAL OF APPLIED PHYSICS}, author={Li, VZQ and Mirabedini, MR and Hornung, BE and Heinisch, HH and Xu, M and Batchelor, D and Maher, DM and Wortman, JJ and Kuehn, RT}, year={1998}, month={May}, pages={5469–5476} }
 @article{morfouli_ghibaudo_vogel_hill_misra_mclarty_wortman_1997, title={Electrical and reliability properties of thin silicon oxinitride dielectrics formed by low pressure rapid thermal chemical vapor deposition}, volume={41}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(97)00019-1}, abstractNote={The electrical properties and reliability issues of MOSFETs with an ultra thin silicon oxinitride gate film (5 nm up to 8.5 nm), prepared by low pressure rapid thermal chemical vapor deposition are studied with the goal to evaluate the impact of the nitridation on the electrical properties of MOSFETs. More specifically, the wear-out and breakdown features of oxinitride dielectrics are investigated as a function of the nitrogen concentration in the film. The charge building up in the insulator bulk was evaluated while the interface reliability parameters were extracted from charge pumping and transfer characteristics measurements after constant current gate stress (1 mA cm−2). The optimum nitridation rate for minimizing the charge building up is shown to be 2–3%. However the charge-to-breakdown was found to decrease continuously after nitridation.}, number={7}, journal={SOLID-STATE ELECTRONICS}, author={Morfouli, P and Ghibaudo, G and Vogel, EM and Hill, WL and Misra, V and McLarty, PK and Wortman, JJ}, year={1997}, month={Jul}, pages={1051–1055} }
 @article{li_mirabedini_kuehn_wortman_ozturk_batchelor_christensen_maher_1997, title={Rapid thermal chemical vapor deposition of in situ boron doped polycrystalline silicon germanium films on silicon dioxide for complimentary metal oxide semiconductor applications}, volume={71}, DOI={10.1063/1.120344}, abstractNote={In situ boron-doped polycrystalline Si1−xGex (x>0.4) films have been formed on the thermally grown oxides in a rapid thermal chemical vapor deposition processor using SiH4-GeH4-B2H6-H2 gas system. Our results showed that in situ boron-doped Si1−xGex films can be directly deposited on the oxide surface, in contrast to the rapid thermal deposition of undoped silicon-germanium (Si1−xGex) films on oxides which is a partially selective process and requires a thin silicon film pre-deposition to form a continuous film. For the in situ boron-doped Si1−xGex films, we observed that with the increase of the germane percentage in the gas source, the Ge content and the deposition rate of the film are increased, while its resistivity is decreased down to 0.66 mΩ cm for a Ge content of 73%. Capacitance-voltage characteristics of p-type metal-oxide-semiconductor capacitors with p+-Si1−xGex gates showed negligible polydepletion effect for a 75 Å gate oxide, indicating that a high doping level of boron at the poly-Si1−xGex/oxide interface was achieved.}, number={23}, journal={Applied Physics Letters}, author={Li, V. Z. Q. and Mirabedini, M. R. and Kuehn, R. T. and Wortman, J. J. and Ozturk, M. C. and Batchelor, D. and Christensen, K. and Maher, D. M.}, year={1997}, pages={3388–3390} }
 @misc{hauser_sorrell_wortman_1995, title={Three-zone rapid thermal processing system utilizing wafer edge heating means}, volume={5,418,885}, number={1995 May 23}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Hauser, J. and Sorrell, F. and Wortman, J.}, year={1995} }
 @misc{ozturk_grider_sanganeria_ashburn_wortman_1994, title={Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures}, volume={5,336,903}, number={1994 Aug. 9}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Ozturk, M. and Grider, D. and Sanganeria, M. and Ashburn, S. and Wortman, J.}, year={1994} }
 @article{masnari_hauser_lucovsky_maher_markunas_ozturk_wortman_1993, title={CENTER FOR ADVANCED ELECTRONIC MATERIALS PROCESSING}, volume={81}, ISSN={["0018-9219"]}, DOI={10.1109/JPROC.1993.752025}, abstractNote={Microelectronics manufacturing technology is rapidly moving toward integrated circuits with submicron minimum feature sizes. This is being driven by the development of devices and circuits with reduced device lateral dimensions, increased density per chip, thinner material layers, increased use of the vertical dimension (three-dimensional circuits), low volume/fast tumaround design (ASIC's), increased use of heterojunctions, mixed material technologies, and quantum-based device structures. These trends require precise control of thin layers processed on wafers and a need for lower temperature processing or a lower overall thermal budget}, number={1}, journal={PROCEEDINGS OF THE IEEE}, author={MASNARI, NA and HAUSER, JR and LUCOVSKY, G and MAHER, DM and MARKUNAS, RJ and OZTURK, MC and WORTMAN, JJ}, year={1993}, month={Jan}, pages={42–59} }
 @misc{wortman_sorrell_hauser_fordham_1993, title={Conical rapid thermal processing apparatus}, volume={5,253,324}, number={1993 Oct. 12}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Wortman, J. and Sorrell, F. and Hauser, J. and Fordham, M.}, year={1993} }
 @misc{ozturk_wortman_1993, title={Deposition of germanium thin films on silicon dioxide employing interposed polysilicon laye}, volume={5,250,452}, number={1993 Oct. 5}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Ozturk, M. and Wortman, J.}, year={1993} }
 @misc{ozturk_wortman_1992, title={Germanium silicon dioxide gate MOSFET}, volume={5,101,247}, number={1992 Mar. 31}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Ozturk, M. and Wortman, J.}, year={1992} }
 @misc{ozturk_wortman_grider_1992, title={Selective germanium deposition on silicon and resulting structures}, volume={5,089,872}, number={1992 Feb. 18}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Ozturk, M. and Wortman, J. and Grider, D.}, year={1992} }