Works (4)
Updated: July 5th, 2023 15:50
2012 journal article
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 68(2), 171–182.
author keywords: MIMO; K-best; Sphere decoder; VLSI
TL;DR:
A reconfigurable in-place architecture that is scalable to an arbitrary number of antennas at run-time, while reducing area significantly compared with other sphere decoders, and to improve the throughput of the in-place architecture without any degradation in BER performance is proposed.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2011 journal article
Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor
IET COMPUTERS AND DIGITAL TECHNIQUES, 5(3), 198–204.
TL;DR:
A floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path is presented.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
9. Industry, Innovation and Infrastructure
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2009 conference paper
A low power 3D integrated FFT engine using hypercube memory division
ISLPED 09, 231–236.
TL;DR:
A floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point F FT down to 4.227 μJ is demonstrated.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2009 journal article
Parallel merge algorithm for high-throughput signal processing applications
ELECTRONICS LETTERS, 45(3), 188–189.
TL;DR:
A parallel merge algorithm is proposed that results in a smaller critical-path delay than all of the other merge algorithms explored, which effectively increases the throughput of VLSI signal processing systems.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
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