@article{moezzi-madani_thorolfsson_chiang_davis_2012, title={Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding}, volume={68}, ISSN={["1939-8115"]}, DOI={10.1007/s11265-011-0595-9}, number={2}, journal={JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY}, author={Moezzi-Madani, Nariman and Thorolfsson, Thorlindur and Chiang, Patrick and Davis, William Rhett}, year={2012}, month={Aug}, pages={171–182} }
@article{thorolfsson_moezzi-madani_franzon_2011, title={Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor}, volume={5}, ISSN={["1751-861X"]}, DOI={10.1049/iet-cdt.2009.0106}, abstractNote={In this study, the authors present a floating-point synthetic aperture radar processor that achieves a power efficiency of 18.0 mW/GFlop in simulation through the use of three-dimensional (3D) integration and reconfiguration of the data path. The reconfiguration reduces the number of arithmetic units required in every processing element (PE) from 24 down to 10. The processor uses a 3D integrated memory that reduces the memory power consumption by 70% when compared to a 2D memory. The system processes a SAR image using a two-tier 3D integrated PE, which when compared to an equivalent 2D PE decreases the power consumed in the interconnect of each PE by 15.5% and the footprint by 49.2%, and allows the PE to operate 7.1% faster in simulation. Additionally, by using 3D integration in the memory one can reduce the power consumption of the memory by 70%. Furthermore, the authors show how the 3D aspects of the processor can be realised by using 2D tools, when used in conjunction with the proposed through-silicon via assignment algorithm.}, number={3}, journal={IET COMPUTERS AND DIGITAL TECHNIQUES}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, P. D.}, year={2011}, month={May}, pages={198–204} }
@inproceedings{thorolfsson_moezzi-madani_franzon_2009, title={A low power 3D integrated FFT engine using hypercube memory division}, DOI={10.1145/1594233.1594289}, abstractNote={In this paper we demonstrate a floating point FFT processor that leverages both 3D integration and a hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down to 4.227 μJ. The hypercube memory division scheme lowers the energy per memory access by 59.2% while only increasing the total area required by 16.8%, while using 3D integration reduces the logic power by 5.2%. For comparison, we analyze the amount of power and wire length reduction that can be expected from 3D integration for normal digital logic circuits.}, booktitle={ISLPED 09}, author={Thorolfsson, T. and Moezzi-Madani, N. and Franzon, Paul}, year={2009}, pages={231–236} }
@article{moezzi-madani_davis_2009, title={Parallel merge algorithm for high-throughput signal processing applications}, volume={45}, ISSN={["1350-911X"]}, DOI={10.1049/el:20092616}, abstractNote={A parallel merge algorithm is proposed that results in a smaller critical-path delay than all of the other merge algorithms explored. The parallel merge circuit effectively increases the throughput of VLSI signal processing systems. The critical path of this circuit is independent of the number of input values.}, number={3}, journal={ELECTRONICS LETTERS}, author={Moezzi-Madani, N. and Davis, W. R.}, year={2009}, month={Jan}, pages={188–189} }