@article{yang_ade_nemanich_2004, title={Stability and dynamics of Pt-Si liquid microdroplets on Si(001)}, volume={69}, ISSN={["2469-9969"]}, DOI={10.1103/physrevb.69.045421}, abstractNote={The formation and dynamics of Pt-Si liquid droplets on Si (001) surfaces are explored with real-time ultraviolet photoelectron emission microscopy. PtSi islands of micrometer lateral diameter begin to melt and are transformed into molten Pt-Si alloy islands below the melting point of bulk PtSi. In particular, at ∼1100 °C surface migration of the liquid microdroplets is observed, where the droplets move directionally from the cold to the hot regions of the surface following the temperature gradient across the substrate. It is proposed that the droplet surface migration is due to dissolution-diffusion-deposition flow of Si through the droplet driven by the Si concentration difference in the droplet. In addition, the migration rate of the droplet is measured as a function of temperature and droplet diameter. Above a minimum diameter, the migration velocity is independent of the droplet size, which indicates that Si diffusivity through the droplet is the primary factor determining the rate of migration. The activation energy for the Si diffusion in the droplet is found to be ∼0.57 eV. We conclude that the thermal and chemical stability of the droplet-substrate interface significantly affects the evolution and dynamics of the liquid island on the surface.}, number={4}, journal={PHYSICAL REVIEW B}, author={Yang, WC and Ade, H and Nemanich, RJ}, year={2004}, month={Jan} }
 @article{yang_smith_arthur_parsons_2000, title={Stability of low-temperature amorphous silicon thin film transistors formed on glass and transparent plastic substrates}, volume={18}, ISSN={["1071-1023"]}, url={http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000086587000015&KeyUID=WOS:000086587000015}, DOI={10.1116/1.591259}, abstractNote={This article describes the formation of amorphous silicon thin film transistors (TFTs) on glass and flexible transparent plastic substrates using rf plasma enhanced chemical vapor deposition and a maximum processing temperature of 110 °C. Silane diluted with hydrogen was used for the preparation of the amorphous silicon, and SiH4/NH3/N2 or SiH4/NH3/N2/H2 mixtures were used for the deposition of the silicon nitride gate dielectric. The amorphous silicon nitride layers were characterized by transmission infrared spectroscopy and current-voltage measurements; the plastic substrates were 10 mil thick (0.25 mm) polyethylene terephthalate sheets. Transistors formed using the same process on glass and plastic showed linear mobilities ranging from 0.1 to 0.5 cm2/V s with ION/IOFF ratios⩾107. To characterize the stability of the transistors on glass, n- and p-channel transconductances were measured before and after bias stressing. Devices formed at 110 °C show evidence of charge trapping near the a-Si/SiNx interface and the creation of dangling-bond defects. The defect dynamics are consistent with the defect pool model. Under +10 and +25 V bias stress, the rates of creation of low energy defects are only moderately larger than those for high temperature devices; the devices show markedly higher rates of defect creation under higher positive bias. Current-voltage analysis of low temperature dielectrics shows very low leakage, but positive bias stress shows a significantly higher electron trapping rate near the a-Si:H/SiNx interface, indicating problems with low temperature dielectric formation. The magnitude of the rates of defect creation and trapping in these nonoptimized devices suggests that amorphous silicon TFTs with stability approaching that of typical large area active matrix electronic devices could be formed at low temperatures compatible with transparent flexible polymeric substrates.}, number={2}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={Yang, CS and Smith, LL and Arthur, CB and Parsons, GN}, year={2000}, pages={683–689} }
 @article{yang_read_arthur_srinivasan_parsons_1998, title={Self-aligned gate and source drain contacts in inverted-staggered a-Si : H thin-film transistors fabricated using selective area silicon PECVD}, volume={19}, ISSN={["0741-3106"]}, url={http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=ORCID&SrcApp=OrcidOrg&DestLinkType=FullRecord&DestApp=WOS_CPL&KeyUT=WOS:000073727100002&KeyUID=WOS:000073727100002}, DOI={10.1109/55.678536}, abstractNote={This article demonstrates full self-aligned inverted-staggered amorphous silicon thin-film transistors (TFT's) fabricated using selective plasma deposition of doped microcrystalline silicon source/drain contacts. Back-side exposure, using the bottom metal gate as the mask, produced the self-aligned contact openings. Selective deposition of the n+ silicon contact layer assures self-aligned ion resistance contacts and eliminates the need for reactive ion etching of the n+ silicon. Complete TFT fabrication requires no critical alignment steps. Transistors have linear mobility between 0.6 and 1.1 cm/sup 2//Vs, threshold voltage of 3.0 V, and sub-threshold slope of 0.35 V/decade. The OFF current is <10/sup -11/ A with -10 V gate voltage and 10 V between the source and drain, and ON/OFF ratios exceed 10.}, number={6}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Yang, CS and Read, WW and Arthur, C and Srinivasan, E and Parsons, GN}, year={1998}, month={Jun}, pages={180–182} }