@article{yang_wortman_2001, title={A study of the effects of tunneling currents and reliability of sub-2 nm gate oxides on scaled n-MOSFETs}, volume={41}, ISSN={["0026-2714"]}, DOI={10.1016/S0026-2714(00)00099-8}, abstractNote={This work examined various components of direct gate tunneling currents and analyzed reliability of ultrathin gate oxides (1.4–2 nm) in scaled n-metal-oxide-semiconductor field effective transistor (MOSFETs). Direct gate tunneling current components were studied both experimentally and theoretically. In addition to gate tunneling currents, oxide reliability was investigated as well. Constant voltage stressing was applied to the gate oxides. The oxide breakdown behaviors were observed and their effects on device performance were studied. The ultrathin oxides in scaled n-MOSFETs used in this study showed distinct breakdown behavior and strong location dependence. No “soft” breakdown was seen for 1.5 nm oxide with small area, implying the importance of using small and more realistic MOS devices for ultrathin oxide reliability study instead of using large area devices. Higher frequency of oxide breakdowns in the source/drain extension to the gate overlap region was then observed in the channel region. Possible explanations to the observed breakdown behaviors were proposed based on the quantum mechanical effects and point-contact model for electron conduction in the oxide during the breakdown. It was concluded that the source/drain extension to the gate overlap regions have strong effects on the device performance in terms of both gate tunneling currents and oxide reliability.}, number={1}, journal={MICROELECTRONICS RELIABILITY}, author={Yang, N and Wortman, JJ}, year={2001}, month={Jan}, pages={37–46} }
 @article{yang_henson_wortman_2000, title={A comparative study of gate direct tunneling and drain leakage currents in N-MOSFET's with sub-2-nm gate oxides}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.853042}, abstractNote={This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Wortman, JJ}, year={2000}, month={Aug}, pages={1636–1644} }
 @article{henson_yang_kubicek_vogel_wortman_de meyer_naem_2000, title={Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.848282}, abstractNote={Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Henson, WK and Yang, N and Kubicek, S and Vogel, EM and Wortman, JJ and De Meyer, K and Naem, A}, year={2000}, month={Jul}, pages={1393–1400} }
 @article{wang_parker_hodge_croswell_yang_misra_hauser_2000, title={Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks}, volume={21}, ISSN={["0741-3106"]}, DOI={10.1109/55.830971}, abstractNote={In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wang, ZG and Parker, CG and Hodge, DW and Croswell, RT and Yang, N and Misra, V and Hauser, JR}, year={2000}, month={Apr}, pages={170–172} }
 @article{yang_henson_hauser_wortman_2000, title={Estimation of the effects of remote charge scattering on electron mobility of n-MOSFET's with ultrathin gate oxides}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.822292}, abstractNote={The effects of remote charge scattering on the electron mobility of n-MOSFETs with ultrathin gate oxides from 1.5 nm to 3.2 nm have been estimated. By calculating the scattering rate of the two-dimensional (2-D) electron gas at the Si/silicon dioxide interface due to the ionized doping impurities at the poly-Si/silicon dioxide interface, the remote charge scattering mobility has been calculated. Electron mobility measured from the n-MOSFETs with ultrathin gate oxides has been used to extract several known mobility components. These mobility components have been compared to the calculated remote charge scattering mobility. From these comparisons, it is clear that the overall electron mobility is not severely degraded by remote charge scattering for the oxide thickness studied.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={2000}, month={Feb}, pages={440–447} }
 @article{yang_henson_hauser_wortman_1999, title={Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices}, volume={46}, ISSN={["1557-9646"]}, DOI={10.1109/16.772492}, abstractNote={Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={1999}, month={Jul}, pages={1464–1471} }
 @article{henson_yang_wortman_1999, title={Observation of oxide breakdown and its effects on the characteristics of ultra-thin-oxide nMOSFET's}, volume={20}, ISSN={["1558-0563"]}, DOI={10.1109/55.806099}, abstractNote={Ultra-thin gate oxide breakdown in nMOSFET's has been studied for an oxide thickness of 1.5 nm using constant voltage stressing. The pre- and post-oxide breakdown characteristics of the device have been compared, and the results have shown a strong dependence on the breakdown locations. The oxide breakdown near the source/drain-to-gate overlap regions was found to be more severe on the post-breakdown characteristics of the device than breakdown in the channel. This observation may be related to the dependence of breakdown on the distribution of electric field and areas of different regions within the nMOSFET under stress.}, number={12}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Yang, N and Wortman, JJ}, year={1999}, month={Dec}, pages={605–607} }