@article{yang_chen_wen_chen_wang_chen_wang_zhang_zhang_hu_et al._2019, title={A Therapeutic Microneedle Patch Made from Hair-Derived Keratin for Promoting Hair Regrowth}, volume={13}, ISSN={["1936-086X"]}, DOI={10.1021/acsnano.8b09573}, abstractNote={Activating hair follicle stem cells (HFSCs) to promote hair follicle regrowth holds promise for hair loss therapy, while challenges still remain to develop a scenario that enables enhanced therapeutic efficiency and easy administration. Here we describe a detachable microneedle patch-mediated drug delivery system, mainly made from hair-derived keratin, for sustained delivery of HFSC activators. It was demonstrated that this microneedle device integrated with mesenchymal stem cell (MSC)-derived exosomes and a small molecular drug, UK5099, could enhance the treatment efficiency at a reduced dosage, leading to promoted pigmentation and hair regrowth within 6 days through two rounds of administration in a mouse model. This microneedle-based transdermal drug delivery approach shows augmented efficacy compared to the subcutaneous injection of exosomes and topical administration of UK5099.}, number={4}, journal={ACS NANO}, author={Yang, Guang and Chen, Qian and Wen, Di and Chen, Zhaowei and Wang, Jinqiang and Chen, Guojun and Wang, Zejun and Zhang, Xudong and Zhang, Yuqi and Hu, Quanyin and et al.}, year={2019}, month={Apr}, pages={4354–4360} }
 @article{zhang_wilson_bashirullah_luo_xu_franzon_2009, title={A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling}, volume={17}, ISSN={1063-8210 1557-9999}, url={http://dx.doi.org/10.1109/tvlsi.2008.2002682}, DOI={10.1109/TVLSI.2008.2002682}, abstractNote={This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.}, number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Zhang, Liang and Wilson, John M. and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul D.}, year={2009}, month={Sep}, pages={1267–1274} }