@article{choudhary_wadhavkar_shah_mayukh_gandhi_dwiel_navada_najaf-abadi_rotenberg_2012, title={FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN}, volume={32}, ISSN={["1937-4143"]}, DOI={10.1109/mm.2012.23}, abstractNote={Providing multiple superscalar core types on a chip, each tailored to different classes of instruction-level behavior, is an exciting direction for increasing processor performance and energy efficiency. Unfortunately, processor design and verification effort increases with each additional core type, limiting the microarchitectural diversity that can be practically implemented. FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities.}, number={3}, journal={IEEE MICRO}, author={Choudhary, Niket K. and Wadhavkar, Salil V. and Shah, Tanmay A. and Mayukh, Hiran and Gandhi, Jayneel and Dwiel, Brandon H. and Navada, Sandeep and Najaf-Abadi, Hashem H. and Rotenberg, Eric}, year={2012}, pages={48–59} }
 @article{choudhary_wadhavkar_shah_mayukh_gandhi_dwiel_navada_najaf-abadi_rotenberg_2011, title={FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template}, DOI={10.1145/2000064.2000067}, abstractNote={A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-designed superscalar core types that can streamline the execution of diverse programs and program phases. No prior research has addressed the “Achilles' heel” of this paradigm: design and verification effort is multiplied by the number of different core types. This work frames superscalar processors in a canonical form, so that it becomes feasible to quickly design many cores that differ in the three major superscalar dimensions: superscalar width, pipeline depth, and sizes of structures for extracting instruction-level parallelism (ILP). From this idea, we develop a toolset, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template. The template defines canonical pipeline stages and interfaces among them. A Canonical Pipeline Stage Library (CPSL) provides many implementations of each canonical pipeline stage, that differ in their superscalar width and depth of sub-pipelining. An RTL generation tool uses the template and CPSL to automatically generate an overall core of desired configuration. Validation experiments are performed along three fronts to evaluate the quality of RTL designs generated by FabScalar: functional and performance (instructions-per-cycle (IPC)) validation, timing validation (cycle time), and confirmation of suitability for standard ASIC flows. With FabScalar, a chip with many different superscalar core types is conceivable.}, journal={ISCA 2011: Proceedings of the 38th annual international symposium on computer architecture}, author={Choudhary, N. K. and Wadhavkar, S. V. and Shah, T. A. and Mayukh, H. and Gandhi, J. and Dwiel, B. H. and Navada, S. and Najaf-abadi, H. H. and Rotenberg, E.}, year={2011}, pages={11–22} }
 @article{navada_choudhary_rotenberg_2010, title={Criticality-driven Superscalar Design Space Exploration}, ISBN={["978-1-4503-0178-7"]}, DOI={10.1145/1854273.1854308}, abstractNote={It has become increasingly difficult to perform design space exploration (DSE) of computer systems with a short turnaround time because of exploding design spaces, increasing design complexity and long-running workloads. Researchers have used classical search/optimization techniques like simulated annealing, genetic algorithms, etc., to accelerate the DSE. While these techniques are better than an exhaustive search, a substantial amount of time must still be dedicated to DSE. This is a serious bottleneck in reducing research/development time. These techniques do not perform the DSE quickly enough, primarily because they do not leverage any insight as to how the different design parameters of a computer system interact to increase or degrade performance at a design point and treat the computer system as a “black-box”.}, journal={PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES}, author={Navada, Sandeep and Choudhary, Niket K. and Rotenberg, Eric}, year={2010}, pages={261–272} }