Sanjeev Banerjia

Works (2)

Updated: July 5th, 2023 16:03

1998 journal article

MPS: Miss-path scheduling for multiple-issue processors

IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397.

By: S. Banerjia*, S. Sathaye*, K. Menezes* & T. Conte n

author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
TL;DR: This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS, which is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1998 conference paper

Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures

Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308–315. Los Alamitos, Calif.: IEEE Computer Society Press.

By: E. Ozer, S. Banerjia & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

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