Brandon Harley Dwiel

Works (3)

Updated: July 5th, 2023 15:45

2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi n, N. Choudhary n, B. Dwiel n, A. Upreti n, E. Rotenberg n, R. Davis  n, P. Franzon n 

Event: International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 4-6, 2013

TL;DR: This work proposes exploiting two complementary forms of heterogeneity to profitably exploit an immature technology for Chip Multiprocessors (CMP): 3D integration facilitates a technology alloy and application and microarchitectural heterogeneity is exploited to compensate for lower efficiency of old-technology cores. (via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2012 journal article

FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN

IEEE MICRO, 32(3), 48–59.

By: N. Choudhary n, S. Wadhavkar n, T. Shah n, H. Mayukh n, J. Gandhi  n, B. Dwiel n, S. Navada n, H. Najaf-Abadi n, E. Rotenberg n

TL;DR: FabScalar aims to automate superscalar core design, opening up processor design to microarchitectural diversity and its many opportunities. (via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

2011 journal article

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

By: N. Choudhary n, S. Wadhavkar n, T. Shah*, H. Mayukh*, J. Gandhi *, B. Dwiel n, S. Navada n, H. Najaf-abadi*, E. Rotenberg n

TL;DR: From this idea, a toolset is developed, called FabScalar, for automatically composing the synthesizable register-transfer-level (RTL) designs of arbitrary cores within a canonical superscalar template, which defines canonical pipeline stages and interfaces among them. (via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018

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