2013 conference paper

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

By: S. Priyadarshi, N. Choudhary, B. Dwiel, A. Upreti n, E. Rotenberg, R. Davis, P. Franzon

Event: International Symposium on Quality Electronic Design (ISQED) at Santa Clara, CA on March 4-6, 2013

Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2012 journal article


IEEE MICRO, 32(3), 48–59.

By: N. Choudhary, S. Wadhavkar, T. Shah n, H. Mayukh n, J. Gandhi n, B. Dwiel, S. Navada, H. Najaf-Abadi n, E. Rotenberg

Source: Web Of Science
Added: August 6, 2018

2011 journal article

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

By: N. Choudhary, S. Wadhavkar, T. Shah*, H. Mayukh*, J. Gandhi*, B. Dwiel, S. Navada, H. Najaf-abadi*, E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018