@article{davis_wilson_mick_xu_hua_mineo_sule_steer_franzon_2005, title={Demystifying 3D ICs: The procs and cons of going vertical}, volume={22}, ISSN={["1558-1918"]}, DOI={10.1109/MDT.2005.136}, abstractNote={This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.}, number={6}, journal={IEEE DESIGN & TEST OF COMPUTERS}, author={Davis, WR and Wilson, J and Mick, S and Xu, M and Hua, H and Mineo, C and Sule, AM and Steer, M and Franzon, PD}, year={2005}, pages={498–510} }
 @article{pa o'neil_ozturk_batchelor_xu_maher_1999, title={Quality of selective silicon epitaxial films deposited using disilane and chlorine}, volume={146}, ISSN={["0013-4651"]}, DOI={10.1149/1.1391937}, abstractNote={We have previously reported on the selectivity and growth of a silicon epitaxy process using Si 2 H 6 and Cl 2 in an ultrahigh-vacuum rapid thermal chemical vapor deposition reactor. In this report, we have extended the previous work and provide information regarding the structural and electrical quality of thick (3000 A) selective silicon epitaxial layers deposited under a variety of growth conditions. Electrical test structures, including enclosed n-channel metal oxide semiconductor field effect transistors (MOSFETs) and large-area gated diodes, were fabricated within the epitaxial layers. We demonstrate that variations in the chlorine to silicon ratio (Cl/Si) and the process temperature can lead to structural defects and low generation lifetimes. The defects, however, had a benign effect over the MOSFET drive current and channel transconductance. Overall, the results in this study indicate that high levels of chlorine, as well as low growth temperatures, can potentially inhibit the structural and/or electrical quality of selectively deposited silicon films. However, for growth at or above 800°C with Cl/Si ratio of 0.23, excellent selectivity as well as extremely high bulk generation lifetimes can be obtained for films with structural defect densities well below the detection limits used within this study.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={PA O'Neil and Ozturk, MC and Batchelor, AD and Xu, MM and Maher, DM}, year={1999}, month={Jun}, pages={2337–2343} }