@article{osburn_de_yee_srivastava_2000, title={Design and integration considerations for end-of-the roadmap ultrashallow junctions}, volume={18}, ISSN={["1071-1023"]}, DOI={10.1116/1.591195}, abstractNote={Device simulations and response surface analysis have been used to quantify the trade-offs and issues encountered in designing ultrashallow junctions for the 250–50 nm generations of complimentary metal-oxide-semiconductor ultralarge scale integration technology. The design of contacting and extension junctions is performed to optimize short channel effects, performance, and reliability, while meeting the National Technology Roadmap for Semiconductors off-state leakage specifications. A maxima in saturated drive current is observed for an intermediate extension junction depth (∼20 nm for 100 nm technology): shallower junctions lead to higher series resistance, and deeper junctions result in more severe short channel effects. The gate-to-junction overlap required to preserve drive current was seen to depend on junction abruptness. For a perfectly abrupt junction, it is not necessary for the gate to overlap the junction. Performance depends on many parameters, including: overlap of gate to extension junction, junction capacitance, and parasitic series resistance, which depends on the doping gradient at the junction (spreading resistance), the extension series resistance, and the contact resistance. Extraction of these parameters using I–V or C–V measurements can potentially lead to erroneous conclusions about lateral junction excursion and abruptness.}, number={1}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={Osburn, CM and De, I and Yee, KF and Srivastava, A}, year={2000}, pages={338–345} }
 @article{de_johri_srivastava_osburn_2000, title={Impact of gate workfunction on device performance at the 50 nm technology node}, volume={44}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(99)00323-8}, abstractNote={The optimal gate electrode workfunction was determined for the 50 nm technology node using a simulation strategy that takes into account the impact of short-channel effects on device performance in uniformly doped and super-steep-retrograde doped channels in conventional and dynamic threshold operation. Classical device simulations suggest that the optimal workfunction is such that the gate Fermi level is 0.2 eV below (above) the conduction (valence) band edge of silicon for NMOS (PMOS) devices. However, when quantum mechanical effects are taken into account, the optimal workfunction is such that the gate Fermi level coincides with the conduction (valence) band edge. Midgap gates are not viable because the resulting short-channel effects are too severe. In a surrounding-gate transistor the optimal workfunction is attained when the gate Fermi level is 0.35 eV below (above) the conduction (valence) band edge in NMOS (PMOS) device. Midgap gates are not viable because the resulting threshold voltage is too high and cannot be reduced by lowering the substrate doping.}, number={6}, journal={SOLID-STATE ELECTRONICS}, author={De, I and Johri, D and Srivastava, A and Osburn, CM}, year={2000}, month={Jun}, pages={1077–1080} }
 @article{ahmed_de_osburn_wortman_hauser_2000, title={Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.831010}, abstractNote={The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L/sub eff/- and R/sub sd/-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V/sub g/ dependence of L/sub eff/ and R/sub sd/ even for devices with degenerately doped drain junction.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and De, I and Osburn, C and Wortman, J and Hauser, J}, year={2000}, month={Apr}, pages={891–895} }
 @article{de_osburn_1999, title={Impact of super-steep-retrograde channel doping profiles on the performance of scaled devices}, volume={46}, ISSN={["0018-9383"]}, DOI={10.1109/16.777161}, abstractNote={Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L/sub gate/ and the same off-state leakage current I/sub off/, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved short-channel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gate-dielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrodinger-Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET's will be similar.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={De, I and Osburn, CM}, year={1999}, month={Aug}, pages={1711–1717} }