@article{williams_kim_holton_2000, title={Ensemble Monte Carlo study of channel quantization in a 25-nm n-MOSFET}, volume={47}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.870564}, DOI={10.1109/16.870564}, abstractNote={We develop a self-consistent, ensemble Monte Carlo device simulator that is capable of modeling channel carrier quantization and polysilicon gate depletion in nanometer-scale n-MOSFETs. A key feature is a unique bandstructure expression for quantized electrons. Carrier quantization and polysilicon depletion are examined against experimental capacitance-voltage (C-V) data. Calculated drain current values are also compared with measured current-voltage data for an n-MOSFET with an effective channel length (L/sub eff/) of 90 nm. Finally, the full capabilities of the Monte Carlo simulator are used to investigate the effects of carrier confinement in a L/sub eff/=25 nm n-MOSFET. In particular, the mechanisms affecting the subband populations of quantized electrons in the highly nonuniform channel region are investigated. Simulation results indicate that the occupation levels in the subbands are a strong function of the internal electric field configurations and two-dimensional (2-D) carrier scattering.}, number={10}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Williams, S.C. and Kim, K.W. and Holton, W.C.}, year={2000}, pages={1864–1872} }
 @article{williams_kim_littlejohn_holton_1999, title={Analysis of hot-electron reliability and device performance in 80-nm double-gate SOI n-MOSFET's}, volume={46}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.777167}, DOI={10.1109/16.777167}, abstractNote={In this paper, we employ a comprehensive Monte Carlo-based simulation method to model hot-electron injection, to predict induced device degradation, and to simulate and compare the performance of two double-gate fully depleted silicon-on-insulator n-MOSFET's (one with a lightly-doped channel and one with a heavily-doped channel) and a similar lightly-doped single-gate design. All three designs have an effective channel length of 80 nm and a silicon layer thickness of 25 mm. Monte Carlo simulations predict a spatial retardation between the locations of peak hot-electron injection into the front and back oxides. Since the observed shift is a significant portion of the channel length, the retardation effect greatly influences induced degradation in otherwise well-designed SOI devices. This effect may signal an important consideration for sub-100-nm design strategy. Simulations were also conducted to compare transistor performance against a key figure of merit. Evaluation of reliability and performance results indicate that the double-gate design with a lightly doped channel offers the best tradeoff in immunity to hot-electron-induced degradation and performance.}, number={8}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Williams, S.C. and Kim, K.W. and Littlejohn, M.A. and Holton, W.C.}, year={1999}, pages={1760–1767} }