@article{wang_parker_hodge_croswell_yang_misra_hauser_2000, title={Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks}, volume={21}, ISSN={["0741-3106"]}, DOI={10.1109/55.830971}, abstractNote={In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wang, ZG and Parker, CG and Hodge, DW and Croswell, RT and Yang, N and Misra, V and Hauser, JR}, year={2000}, month={Apr}, pages={170–172} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{parker_lucovsky_hauser_1998, title={Ultrathin oxide-nitride gate dielectric MOSFET's}, volume={19}, ISSN={["0741-3106"]}, DOI={10.1109/55.663529}, abstractNote={The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Parker, CG and Lucovsky, G and Hauser, JR}, year={1998}, month={Apr}, pages={106–108} }