@article{ozer_conte_2005, title={High-performance and low-cost dual-thread VLIW processor using weld architecture paradigm}, volume={16}, ISSN={["1045-9219"]}, DOI={10.1109/TPDS.2005.150}, abstractNote={This paper presents a cost-effective and high-performance dual-thread VLIW processor model. The dual-thread VLIW processor model is a low-cost subset of the Weld architecture paradigm. It supports one main thread and one speculative thread running simultaneously in a VLIW processor with a register file and a fetch unit per thread along with memory disambiguation hardware for speculative load and store operations. This paper analyzes the performance impact of the dual-thread VLIW processor, which includes analysis of migrating disambiguation hardware for speculative load operations to the compiler and of the sensitivity of the model to the variation of branch misprediction, second-level cache miss penalties, and register file copy time. Up to 34 percent improvement in performance can be attained using the dual-thread VLIW processor when compared to a single-threaded VLIW processor model.}, number={12}, journal={IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS}, author={Ozer, E and Conte, TM}, year={2005}, month={Dec}, pages={1132–1142} }
 @inproceedings{ozer_banerjia_conte_1998, title={Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures}, booktitle={Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture.}, publisher={Los Alamitos, Calif.: IEEE Computer Society Press}, author={Ozer, E. and Banerjia, S. and Conte, T. M.}, year={1998}, pages={308–315} }