@inproceedings{purser_sundaramoorthy_rotenberg_2000, title={A study of slipstream processors}, ISBN={076950924X}, DOI={10.1145/360128.360155}, abstractNote={Article Free Access Share on A study of slipstream processors Authors: Zach Purser North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NCView Profile , Karthik Sundaramoorthy North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NCView Profile , Eric Rotenberg North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NC North Carolina State University, Department of Electrical and Computer Engineering, Engineering Graduate Research Center, Campus Box 7914, Raleigh, NCView Profile Authors Info & Claims MICRO 33: Proceedings of the 33rd annual ACM/IEEE international symposium on MicroarchitectureDecember 2000 Pages 269–280https://doi.org/10.1145/360128.360155Published:01 December 2000Publication History 53citation486DownloadsMetricsTotal Citations53Total Downloads486Last 12 Months42Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF}, booktitle={Proceedings: 33rd Annual IEEE/ACM International Symposium on Microarchitecture: Monterey, California, USA, 10-13 December 2000}, publisher={Los Alamitos, CA: IEEE Computer Society}, author={Purser, Z. and Sundaramoorthy, K. and Rotenberg, E.}, year={2000}, pages={269–280} }
 @article{sundaramoorthy_purser_rotenberg_2000, title={Slipstream processors: Improving both performance and fault tolerance}, volume={35}, ISSN={["0362-1340"]}, DOI={10.1145/356989.357013}, abstractNote={
            Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor or simultaneous multithreaded processor, with two key advantages:1)
            Improved single-program performance
            . The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2)
            Fault tolerance
            . The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.
          }, number={11}, journal={ACM SIGPLAN NOTICES}, author={Sundaramoorthy, K and Purser, Z and Rotenberg, E}, year={2000}, month={Nov}, pages={257–268} }
 @inproceedings{sundaramoorthy_purser_rotenberg_2000, title={Slipstream processors: Improving both performance and fault tolerance}, ISBN={1581133170}, DOI={10.1145/378993.379247}, abstractNote={Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effect. We propose creating a shorter but otherwise equivalent version of the original program by removing ineffectual computation and computation related to highly-predictable control flow. The shortened program is run concurrently with the full program on a chip multiprocessor simultaneous multithreaded processor, with two key advantages:1) Improved single-program performance. The shorter program speculatively runs ahead of the full program and supplies the full program with control and data flow outcomes. The full program executes efficiently due to the communicated outcomes, at the same time validating the speculative, shorter program. The two programs combined run faster than the original program alone. Detailed simulations of an example implementation show an average improvement of 7% for the SPEC95 integer benchmarks.2) Fault tolerance. The shorter program is a subset of the full program and this partial-redundancy is transparently leveraged for detecting and recovering from transient hardware faults.}, booktitle={ASPLOS-IX proceedings: Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, November 12-15, 2000}, publisher={New York: ACM Press}, author={Sundaramoorthy, K. and Purser, Z. and Rotenberg, E.}, year={2000}, pages={257–268} }