@article{venkatesan_herr_rotenberg_2006, title={Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM}, ISBN={["0-7803-9368-6"]}, ISSN={["1530-0897"]}, DOI={10.1109/hpca.2006.1598122}, abstractNote={Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention time of a page is defined as the shortest retention time among its constituent cells). Currently, a single worst-case refresh period is selected based on the page with the shortest retention time. Even with refresh optimized for room temperature, the worst page limits the safe refresh period to no longer than 500 ms. Yet, 99% and 85% of pages have retention times above 3 seconds and 10 seconds, respectively. We propose retention-aware placement in DRAM (RAPID), novel software approaches that can exploit off-the-shelf DRAMs to reduce refresh power to vanishingly small levels approaching non-volatile memory. The key idea is to favor longer-retention pages over shorter-retention pages when allocating DRAM pages. This allows selecting a single refresh period that depends on the shortest-retention page among populated pages, instead of the shortest-retention page overall. We explore three versions of RAPID and observe refresh energy savings of 83%, 93%, and 95%, relative to the best temperature-compensated refresh. RAPID with off-the-shelf DRAM also approaches the energy levels of idealized techniques that require custom DRAM support.}, journal={TWELFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS}, author={Venkatesan, Ravi K. and Herr, Stephen and Rotenberg, Eric}, year={2006}, pages={157-+} }
 @misc{rotenberg_venkatesan_al-zawawi_2006, title={Systems, methods and devices for providing variable-latency write operations in memory devices}, volume={7,099,215}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Rotenberg, E. and Venkatesan, R. K. and Al-Zawawi, A. S.}, year={2006} }
 @article{venkatesan_al-zawawi_rotenberg_2005, title={Tapping ZettaRAM (TM) for low-power memory systems}, ISBN={["0-7695-2275-0"]}, ISSN={["1530-0897"]}, DOI={10.1109/hpca.2005.35}, abstractNote={ZettaRAM/spl trade/ is a new memory technology under development by ZettaCore/spl trade/ as a potential replacement for conventional DRAM. The key innovation is replacing the conventional capacitor in each DRAM cell with "charge-storage" molecules - a molecular capacitor. We look beyond ZettaRAM's manufacturing benefits, and approach it from an architectural viewpoint to discover benefits within the domain of architectural metrics. The molecular capacitor is unusual because the amount of charge deposited (critical for reliable sensing) is independent of write voltage, i.e., there is a discrete threshold voltage above/below which the device is fully charged/discharged. Decoupling charge from voltage enables manipulation via arbitrarily small bitline swings, saving energy. However, while charge is voltage-independent, speed is voltage-dependent. Operating too close to the threshold causes molecules to overtake peripheral circuitry as the overall performance limiter. Nonetheless, ZettaRAM offers a speed/energy trade-off whereas DRAM is inflexible, introducing new dimensions for architectural management of memory. We apply architectural insights to tap the full extent of ZettaRAM's power savings without compromising performance. Several factors converge nicely to direct focus on L2 writebacks: (i) they account for 80% of row buffer misses in the main memory, thus most of the energy savings potential, and (ii) they do not directly stall the processor and thereby offer scheduling flexibility for tolerating extended molecule latency. Accordingly, slow writes (low energy) are applied to non-critical writebacks and fast writes (high energy) to critical fetches. The hybrid write policy is combined with two options for tolerating delayed writebacks: large buffers with access reordering or L2-cache eager writebacks. Eager writebacks are remarkably synergistic with ZettaRAM: initiating writebacks early in the L2 cache compensates for delaying them at the memory controller. Dual-speed writes coupled with eager writebacks yields energy savings of 34% (out of 41% with uniformly slow writes), with less than 1% performance degradation.}, journal={11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS}, author={Venkatesan, RK and Al-Zawawi, AS and Rotenberg, E}, year={2005}, pages={83–94} }
 @article{narayan_venkatesan_kvit_2002, title={Structure and properties of nanocrystalline zinc films}, volume={4}, ISSN={["1572-896X"]}, DOI={10.1023/A:1019925315398}, number={3}, journal={JOURNAL OF NANOPARTICLE RESEARCH}, author={Narayan, J and Venkatesan, RK and Kvit, A}, year={2002}, month={Jun}, pages={265–269} }