@article{zhang_wilson_bashirullah_luo_xu_franzon_2009, title={A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling}, volume={17}, ISSN={1063-8210 1557-9999}, url={http://dx.doi.org/10.1109/tvlsi.2008.2002682}, DOI={10.1109/TVLSI.2008.2002682}, abstractNote={This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.}, number={9}, journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Zhang, Liang and Wilson, John M. and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul D.}, year={2009}, month={Sep}, pages={1267–1274} }
 @article{wilson_mick_xu_luo_bonafede_huffman_labennett_franzon_2007, title={Fully integrated AC coupled interconnect using buried bumps}, volume={30}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2007.896920}, abstractNote={Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.}, number={2}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Wilson, John and Mick, Stephen and Xu, Jian and Luo, Lei and Bonafede, Salvatore and Huffman, Alan and LaBennett, Richard and Franzon, Paul D.}, year={2007}, month={May}, pages={191–199} }
 @article{zhang_wilson_bashirullah_luo_xu_franzon_2007, title={Voltage-mode driver preemphasis technique for on-chip global buses}, volume={15}, ISSN={["1557-9999"]}, DOI={10.1109/TVLSI.2007.893588}, abstractNote={This paper demonstrates that driver preemphasis technique can be used for on-chip global buses to increase signal channel bandwidth. Compared to conventional repeater insertion techniques, driver preemphasis saves repeater layout complexity and reduces power consumption by 12%-39% for data activity factors above 0.1. A driver circuit architecture using voltage-mode preemphasis technique was tested in 0.18-mum CMOS technology for 10-mm long interconnects at 2 Gb/s}, number={2}, journal={IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}, author={Zhang, Liang and Wilson, John M. and Bashirullah, Rizwan and Luo, Lei and Xu, Jian and Franzon, Paul D.}, year={2007}, month={Feb}, pages={231–236} }
 @article{luo_wilson_mick_xu_zhang_franzon_2006, title={3 Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver}, volume={41}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2005.859881}, DOI={10.1109/JSSC.2005.859881}, abstractNote={A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.}, number={1}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Luo, L. and Wilson, J.M. and Mick, S.E. and Xu, J. and Zhang, L. and Franzon, P.D.}, year={2006}, month={Jan}, pages={287–296} }
 @article{xu_mick_wilson_luo_chandrasekar_erickson_franzon_2004, title={AC coupled interconnect for dense 3-D ICs}, volume={51}, ISSN={["1558-1578"]}, DOI={10.1109/TNS.2004.834712}, abstractNote={This paper presents the potential application of AC coupled interconnect (ACCI) for dense three-dimensional (3-D) integrated circuits (ICs). The concept of inductive ACCI for 3-D ICs has been proposed. Combined with the "through vias" technology, inductive ACCI can provide small pitch vertical interconnects, as well as an excellent thermal solution for dense 3-D ICs. Transformer modeling and transceiver circuit design have also been investigated. Simulations predict that, for 20 /spl mu/m thinned die stacks coupled by a 100 /spl mu/m diameter transformer, the transceiver circuit fed with a 5 Gbps data stream consumes 14.5 mW power.}, number={5}, journal={IEEE TRANSACTIONS ON NUCLEAR SCIENCE}, author={Xu, J and Mick, S and Wilson, J and Luo, L and Chandrasekar, K and Erickson, E and Franzon, PD}, year={2004}, month={Oct}, pages={2156–2160} }
 @article{mick_luo_wilson_franzon_2004, title={Buried bump and AC coupled interconnection technology}, volume={27}, ISSN={["1521-3323"]}, DOI={10.1109/TADVP.2004.825482}, abstractNote={A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 /spl mu/m and data rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-/spl mu/m technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 /spl mu/m are also presented.}, number={1}, journal={IEEE TRANSACTIONS ON ADVANCED PACKAGING}, author={Mick, S and Luo, L and Wilson, J and Franzon, P}, year={2004}, month={Feb}, pages={121–125} }