2008 article

Improving Behavioral IO Buffer Modeling Based on IBIS

Varma, A. K., Steer, M., & Franzon, P. D. (2008, November 1). IEEE Transactions on Advanced Packaging, Vol. 31, pp. 711–721.

By: A. Varma*, M. Steer n & P. Franzon n

author keywords: Behavioral modeling; gate modulation effect; input output buffer information specification (IBIS); input/output (IO) buffer modeling; simultaneous switching noise (SSN)
topics (OpenAlex): VLSI and Analog Circuit Testing; Electrostatic Discharge in Electronics; Real-time simulation and control systems
TL;DR: A method is presented for compensating for the missing information in IBIS by complimenting the IBIS model with a black box that is simulator independent, without compromising with the speed that IBIS enjoys over the transistor models. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018

2005 article

CAD flows for chip-package coverification

Varma, A. K., Glaser, A., & Franzon, P. D. (2005, February 1). IEEE Transactions on Advanced Packaging, Vol. 28, pp. 194–202.

By: A. Varma n, A. Glaser* & P. Franzon n

topics (OpenAlex): 3D IC and TSV technologies; Manufacturing Process and Optimization; Advancements in Photolithography Techniques
TL;DR: A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification. (via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

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