@article{neuburger_aleksov_schlesser_kohn_sitar_2007, title={Electronic high temperature characteristics of AlN}, volume={43}, DOI={10.1049/el:20070275}, abstractNote={The high temperature electronic properties of bulk single crystal AIN were investigated by temperature dependent I-V measurements in the range of R.T. to 1100degC in vacuum. The samples have been highly insulating at R.T. Such isolation properties are mostly obtained by a high defect density and a high oxygen content. Temperature cycling was used to identify carrier activation and heterogeneous conduction paths possibly originating from a dislocation network. Indeed an increase in conductivity with temperature is observed, which can be fitted with an activation energy of 1.3 eV at medium temperatures. The crystals remained stable up to 1100degC. No change of the room temperature conductivity was observed after several cycles. Impedance spectroscopy at medium temperature, where the material behaves like a lossy dielectric, shows only one dominating conduction path. No grain boundary-like heterogeneous transport through a dislocation network could be detected. Thus, the materials' quality as indicated by its Raman spectrum is also mirrored in the electrical high temperature performance}, number={10}, journal={Electronics Letters}, author={Neuburger, M. and Aleksov, A. and Schlesser, R. and Kohn, E. and Sitar, Z.}, year={2007}, pages={592–594} }
 @article{govindaraju_aleksov_li_okuzumi_wolter_collazo_prater_sitar_2006, title={Comparative study of textured diamond films by thermal conductivity measurements}, volume={85}, ISSN={["1432-0630"]}, DOI={10.1007/s00339-006-3697-7}, number={3}, journal={APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING}, author={Govindaraju, N. and Aleksov, A. and Li, X. and Okuzumi, F. and Wolter, S. D. and Collazo, R. and Prater, J. T. and Sitar, Z.}, year={2006}, month={Nov}, pages={331–335} }
 @article{aleksov_collazo_mita_schlesser_sitar_2006, title={Current-voltage characteristics of n/n lateral polarity junctions in GaN}, volume={89}, ISSN={["1077-3118"]}, DOI={10.1063/1.2244046}, abstractNote={Lateral Si:N-polar/Si:Ga-polar GaN homojunctions were fabricated using metal organic chemical vapor deposition with nitrogen as the carrier and dilution gas. Nominally undoped N-polar areas are n-type conductive, while nominally undoped Ga-polar areas are insulating with carrier densities below 1×1015cm−3. This allows for the fabrication of selectively doped areas within one growth step that can be used to fabricate novel lateral device structures or enhance existing III-N-device structures. In this letter we investigated the electrical properties of the simplest case of these junctions, namely, when both sides are n-type conductive. The results of the IV measurements show a linear characteristic both for the measurement of a N-polar/Si:Ga-polar junction and a N-polar/Si:Ga-polar/N-polar double junction. This result indicates that, as expected, there are no energy barriers between the N-polar and the Ga-polar material and that these structures can be used to achieve laterally selective doped areas in Ga–N for electronic device applications.}, number={5}, journal={APPLIED PHYSICS LETTERS}, author={Aleksov, Aleksandar and Collazo, Ramon and Mita, Seiji and Schlesser, Raoul and Sitar, Zlatko}, year={2006}, month={Jul} }
 @article{collazo_mita_aleksov_schlesser_sitar_2006, title={Growth of Ga- and N- polar gallium nitride layers by metalorganic vapor phase epitaxy on sapphire wafers}, volume={287}, ISSN={["0022-0248"]}, DOI={10.1016/j.jcrysgro.2005.10.080}, abstractNote={Following an already established polarity control scheme for GaN thin films, we developed a process to simultaneously grow Ga- and N-polarity layers side by side on c-plane sapphire. The simultaneous growth is achieved by properly treating the AlN nucleation/buffer layer and subsequent substrate annealing. During this process, the growth is mass-transfer-limited, permitting the same growth rate for both types of polarity domains. Smooth domains of both polarity types (RMS roughness ∼1–2 nm) were obtained.}, number={2}, journal={JOURNAL OF CRYSTAL GROWTH}, author={Collazo, R and Mita, S and Aleksov, A and Schlesser, R and Sitar, Z}, year={2006}, month={Jan}, pages={586–590} }
 @article{aleksov_gobien_li_prater_sitar_2006, title={Silicon-on-diamond - An engineered substrate for electronic applications}, volume={15}, ISSN={["0925-9635"]}, DOI={10.1016/j.diamond.2005.09.012}, abstractNote={Silicon on Diamond (SOD) is a substrate engineered to address the major challenges of silicon-based ULSI technology, in particular, to provide for enhanced thermal management and charge confinement. The SOD concept is achieved by joining a thin, single crystalline Si device layer to a highly oriented diamond (HOD) layer that serves as an electrical insulator, heat spreader and supporting substrate. Therefore, SOD represents an alternative SOI concept, where the thermally insulating SiO2 has been replaced by highly thermally conductive diamond. Initial experiments and theoretical assessments have been aimed at demonstrating the improved thermal management properties of fabricated SOD wafers and comparing them to Si and SOI [A. Aleksov, X. Li, N. Govindaraju, J.M. Gobien, S.D. Wolter, J.T. Prater, Z. Sitar, Silicon on Diamond: an advanced Silicon on Insulator technology, Diamond and Related Materials, 14, 308–313 (2005).], [A. Aleksov, S.D. Wolter, J.T. Prater, Z. Sitar, Fabrication and Thermal Evaluation of Silicon on Diamond Wafers, Journal of Electronic Materials, 34 (2005) 1089.]. The experimental results are in good agreement with the values obtained by finite element modeling (FEM). The results show that for a 1.5 μm thick Si device layer, SOD can sustain more than 10 times higher power than SOI. This in turn will permit a more than 3-fold greater integration density of circuits fabricated on SOD as compared to SOI. Having validated the superior thermal management properties of SOD, the second task has been to compare device operation on SOD and SOI to identify whether the Si layer degrades during the SOD fabrication process. In addition, the analysis of the interface properties between the Si device layer and diamond is important in order to better understand the operation of devices on SOD and identify their limitations. For this reason, Schottky and pn-junction diodes were fabricated on the Si device layer of SOD and SOI wafers. The first results of the electrical analyses indicated that there are no additional leakage currents in SOD devices compared to devices on SOI. In addition, CV measurements indicated no differences in the device behavior i.e. no additional charge trapping with respect to SOI in the frequency range of 1 kHz–10 MHz.}, number={2-3}, journal={DIAMOND AND RELATED MATERIALS}, author={Aleksov, A and Gobien, JM and Li, X and Prater, JT and Sitar, Z}, year={2006}, pages={248–253} }
 @article{aleksov_wolter_prater_sitar_2005, title={Fabrication and thermal evaluation of silicon on diamond wafers}, volume={34}, ISSN={["0361-5235"]}, DOI={10.1007/s11664-005-0100-y}, number={7}, journal={JOURNAL OF ELECTRONIC MATERIALS}, author={Aleksov, A and Wolter, SD and Prater, JT and Sitar, Z}, year={2005}, month={Jul}, pages={1089–1094} }
 @article{aleksov_li_govindaraju_gobien_wolter_prater_sitar_2005, title={Silicon-on-diamond: An advanced silicon-on-insulator technology}, volume={14}, ISSN={["1879-0062"]}, DOI={10.1016/j.diamond.2005.01.019}, abstractNote={Silicon-on-diamond (SOD) technology is proposed as an advanced alternative to conventional silicon-on-insulator (SOI) technology. In SOD, the electrical insulator is diamond, the best thermal conductor in nature. In our SOD concept, the diamond film is highly oriented (HOD), 75–100 μm thick and serves as an electrical insulator, heat spreader and substrate. In this paper, we focus on the thermal evaluation of SOD with a Si device layer on the nucleation side of the diamond film. The obtained results indicated that SOD can sustain up to 10-times higher power loads than SOI. The results were experimentally obtained by R(T) measurements of micro-heaters deposited on the Si device layer and by thermal imaging. 3D finite element thermal simulations using ANSYS confirmed that these numbers are in good agreement with expectations.}, number={3-7}, journal={DIAMOND AND RELATED MATERIALS}, author={Aleksov, A and Li, X and Govindaraju, N and Gobien, JM and Wolter, SD and Prater, JT and Sitar, Z}, year={2005}, pages={308–313} }