@article{blum_soto_wilson_amsinck_franzon_ratna_2007, title={Electronic properties of molecular memory circuits on a nanoscale scaffold}, volume={6}, ISSN={["1558-2639"]}, DOI={10.1109/TNB.2007.908978}, abstractNote={Significant challenges exist in assembling and interconnecting the building blocks of a nanoscale device and being able to electronically address or measure responses at the molecular level. Here we demonstrate the usefulness of engineered proteins as scaffolds for bottom-up self-assembly for building nanoscale devices out of multiple components. Using genetically engineered cowpea mosaic virus, modified to express cysteine residues on the capsid exterior, gold nanoparticles were attached to the viral scaffold in a specific predetermined pattern to produce specific interparticle distances. The nanoparticles were then interconnected using thiol-terminated conjugated organic molecules, resulting in a three-dimensional network. Network properties were engineered by using molecular components with different I-V characteristics. Networks consisting of molecular wires alone were compared with networks containing voltage controlled molecular switches with two stable conductance states. Using such bistable molecules enabled the formation of switchable molecular networks that could be used in nanoscale memory circuits.}, number={4}, journal={IEEE TRANSACTIONS ON NANOBIOSCIENCE}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Amsinck, Christian and Franzon, Paul and Ratna, Banahalli R.}, year={2007}, month={Dec}, pages={270–274} }
 @article{di spigna_nackashi_amsinck_sonkusale_franzon_2006, title={Deterministic nanowire fanout and interconnect without any critical translational alignment}, volume={5}, ISSN={["1941-0085"]}, DOI={10.1109/TNANO.2006.876926}, abstractNote={Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design}, number={4}, journal={IEEE TRANSACTIONS ON NANOTECHNOLOGY}, author={Di Spigna, Neil H. and Nackashi, David P. and Amsinck, Christian J. and Sonkusale, Sachin R. and Franzon, Paul D.}, year={2006}, month={Jul}, pages={356–361} }
 @article{kriplani_nackashi_amsinck_di spigna_steer_franzon_rick_solomon_reimers_2006, title={Physically based molecular device model in a transient circuit simulator}, volume={326}, ISSN={["1873-4421"]}, DOI={10.1016/j.chemphys.2006.03.003}, abstractNote={Abstract Two efficient, physically based models for the real-time simulation of molecular device characteristics of single molecules are developed. These models assume that through-molecule tunnelling creates a steady-state Lorentzian distribution of excess electron density on the molecule and provides for smooth transitions for the electronic degrees of freedom between the tunnelling, molecular-excitation, and charge-hopping transport regimes. They are implemented in the f REEDA™ transient circuit simulator to allow for the full integration of nanoscopic molecular devices in standard packages that simulate entire devices including CMOS circuitry. Methods are presented to estimate the parameters used in the models via either direct experimental measurement or density-functional calculations. The models require 6–8 orders of magnitude less computer time than do full a priori simulations of the properties of molecular components. Consequently, molecular components can be efficiently implemented in circuit simulators. The molecular-component models are tested by comparison with experimental results reported for 1,4-benzenedithiol.}, number={1}, journal={CHEMICAL PHYSICS}, author={Kriplani, Nikhil M. and Nackashi, David P. and Amsinck, Christian J. and Di Spigna, Neil H. and Steer, Michael B. and Franzon, Paul D. and Rick, Ramon L. and Solomon, Gemma C. and Reimers, Jeffrey R.}, year={2006}, month={Jul}, pages={188–196} }
 @article{blum_soto_wilson_brower_pollack_schull_chatterji_lin_johnson_amsinck_et al._2005, title={An Engineered Virus as a Scaffold for Three-Dimensional Self-Assembly on the Nanoscale}, volume={1}, ISSN={1613-6810 1613-6829}, url={http://dx.doi.org/10.1002/smll.200500021}, DOI={10.1002/smll.200500021}, abstractNote={Exquisite control over positioning nanoscale components on a protein scaffold allows bottom-up self-assembly of nanodevices. Using cowpea mosaic virus, modified to express cysteine residues on the capsid exterior, gold nanoparticles were attached to the viral scaffold to produce specific interparticle distances (see picture). The nanoparticles were then interconnected using thiol-terminated conjugated organic molecules that act as "molecular wires", resulting in a 3D spherical conductive network, which is only 30 nm in diameter.}, number={7}, journal={Small}, publisher={Wiley}, author={Blum, Amy Szuchmacher and Soto, Carissa M. and Wilson, Charmaine D. and Brower, Tina L. and Pollack, Steven K. and Schull, Terence L. and Chatterji, Anju and Lin, Tianwei and Johnson, John E. and Amsinck, Christian and et al.}, year={2005}, month={Jul}, pages={702–706} }
 @article{sonkusale_amsinck_nackashi_di spigna_barlage_johnson_franzon_2005, title={Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process}, volume={28}, ISSN={["1873-1759"]}, DOI={10.1016/j.physe.2005.01.010}, abstractNote={We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.}, number={2}, journal={PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES}, author={Sonkusale, SR and Amsinck, CJ and Nackashi, DP and Di Spigna, NH and Barlage, D and Johnson, M and Franzon, PD}, year={2005}, month={Jul}, pages={107–114} }
 @article{amsinck_di spigna_nackashi_franzon_2005, title={Scaling constraints in nanoelectronic random-access memories}, volume={16}, ISSN={["1361-6528"]}, DOI={10.1088/0957-4484/16/10/047}, abstractNote={Nanoelectronic molecular and magnetic tunnel junction (MTJ) MRAM crossbar memory systems have the potential to present significant area advantages (4 to 6F2) compared to CMOS-based systems. The scalability of these conductivity-switched RAM arrays is examined by establishing criteria for correct functionality based on the readout margin. Using a combined circuit theoretical modelling and simulation approach, the impact of both the device and interconnect architecture on the scalability of a conductivity-state memory system is quantified. This establishes criteria showing the conditions and on/off ratios for the large-scale integration of molecular devices, guiding molecular device design. With 10% readout margin on the resistive load, a memory device needs to have an on/off ratio of at least 7 to be integrated into a 64 × 64 array, while an on/off ratio of 43 is necessary to scale the memory to 512 × 512.}, number={10}, journal={NANOTECHNOLOGY}, author={Amsinck, CJ and Di Spigna, NH and Nackashi, DP and Franzon, PD}, year={2005}, month={Oct}, pages={2251–2260} }