@article{sonkusale_di spigna_franzon_2007, title={Uniformity analysis of wafer scale sub-25 nm wide nanowire array nanoimprint mold fabricated by PEDAL process}, volume={84}, ISSN={["0167-9317"]}, DOI={10.1016/j.mee.2007.01.210}, abstractNote={In earlier publications [S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, E. Physica, Low Dimensional Systems and Nanostructures 28 (2005) 107–114; S. Sonkusale, C.J. Amsinck, D.P. Nackashi, N.H. Di Spigna, D. Barlage, M. Johnson, P.D. Franzon, in: Proceedings of Nano Science and Technology Institute (NSTI) conference 2005, vol. 3, pp. 255.], we proposed and successfully demonstrated an unconventional lithographic technique called PEDAL process (planar edge defined alternate layer) to define wafer scale sub 25 nm nanowires and nanoimprint template. In this publication, the uniformity results on array of sixteen line-width structures with obtained by PEDAL process are presented. The average pitch of array across the 4 in. wafer was measured to be 40.8 nm with the standard deviation of 2.3 nm where as the average pitch of the lines in an array was found to be 41.5 nm with the standard deviation of 4.6 nm. After Pd lift-off the average pitch in nanowire array was measured to be 41.9 nm with standard deviation of 1.8 nm, which is close to the values obtained for the template.}, number={5-8}, journal={MICROELECTRONIC ENGINEERING}, author={Sonkusale, Sachin R. and Di Spigna, Neil H. and Franzon, Paul D.}, year={2007}, pages={1523–1527} }
 @article{di spigna_nackashi_amsinck_sonkusale_franzon_2006, title={Deterministic nanowire fanout and interconnect without any critical translational alignment}, volume={5}, ISSN={["1941-0085"]}, DOI={10.1109/TNANO.2006.876926}, abstractNote={Interfacing the nanoworld with the microworld represents a critical challenge to fully integrated nanosystems. Solutions to this problem have generally required either nanoprecision alignment or stochastic assembly. A design is presented that allows complete and deterministic fanout of regular arrays of wires from the nano- to the microworld without the need for any critical translational alignment steps. For example, deterministically connecting 10-nm wires directly to 3-mum wires would require a translational alignment to within only about 6 mum. The design also allows for nanowire interconnect and is independent of the technology used to fabricate the nanowires, enabling technologies for which alignment remains very challenging. The impact of potential fabrication errors is analyzed and a structure is fabricated that demonstrates the feasibility of such a design}, number={4}, journal={IEEE TRANSACTIONS ON NANOTECHNOLOGY}, author={Di Spigna, Neil H. and Nackashi, David P. and Amsinck, Christian J. and Sonkusale, Sachin R. and Franzon, Paul D.}, year={2006}, month={Jul}, pages={356–361} }
 @article{sonkusale_amsinck_nackashi_di spigna_barlage_johnson_franzon_2005, title={Fabrication of wafer scale, aligned sub-25 nm nanowire and nanowire templates using planar edge defined alternate layer process}, volume={28}, ISSN={["1873-1759"]}, DOI={10.1016/j.physe.2005.01.010}, abstractNote={We have demonstrated a new planar edge defined alternate layer (PEDAL) process to make sub-25 nm nanowires across the whole wafer. The PEDAL process is useful in the fabrication of metal nanowires directly onto the wafer by shadow metallization and has the ability to fabricate sub-10 nm nanowires with 20 nm pitch. The process can also be used to make templates for the nano-imprinting with which the crossbar structures can be fabricated. The process involves defining the edge by etching a trench patterned by conventional i-line lithography, followed by deposition of alternating layers of silicon nitride and crystallized a-Si. The thickness of these layers determines the width and spacing of the nanowires. Later the stack is planarized to the edge of the trench by spinning polymer Shipley 1813 and then dry etching the polymer, nitride and polysilicon stack with non-selective RIE etch recipe. Selective wet etch of either nitride or polysilicon gives us the array of an aligned nanowires template. After shadow metallization of the required metal, we get metal nanowires on the wafer. The process has the flexibility of routing the nanowires around the logic and memory modules all across the wafer. The fabrication facilities required for the process are readily available and this process provides the great alternative to existing slow and/or costly nanowire patterning techniques.}, number={2}, journal={PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES}, author={Sonkusale, SR and Amsinck, CJ and Nackashi, DP and Di Spigna, NH and Barlage, D and Johnson, M and Franzon, PD}, year={2005}, month={Jul}, pages={107–114} }