@article{osburn_bellur_1998, title={Low parasitic resistance contacts for scaled ULSI devices}, volume={332}, ISSN={["0040-6090"]}, DOI={10.1016/S0040-6090(98)01046-3}, abstractNote={Analysis of the components of parasitic series resistance in ULSI devices shows that interfacial contact resistivities less than 10−7 Ω cm2 will be required for sub 100-nm ULSI devices in order to stay on the historical performance trend. With dimensional scaling, the series resistance–width product decreases because channel lengths are scaled, while it increases in contacts because the contact length is decreased. Unless the contact resistivity is also reduced, the contact resistance ultimately becomes higher than the channel resistance, and no performance advantage will be obtained by making the device smaller. The challenge in meeting the contacting requirements in the 1997 National Technology Roadmap for Semiconductors is especially difficult in light of the desire to simultaneously contact both n+ and p+ junctions with a single material and given the trend towards lower processing temperatures, in which the equilibrium dopant electrical activity is lower. Several techniques, such as dielectric capping during junction annealing, are effective in reducing contact resistivity by maximizing interfacial dopant concentrations and minimizing contact barrier heights. Higher saturated drive currents, due to lowered parasitic series resistance, are observed in deep submicron devices made using silicides as diffusion sources (SADS); this technique eliminates the interfacial dopant segregation that is associated with conventional silicidation. The use of elevated source drains (ESD) also allows the use of thicker silicides while minimizing the consumption-induced increase in contact resistivity that normally accompanies silicidation; as a result, ESD devices give higher drive currents. The recrystallization of amorphous layers has been observed to result in non-equilibrium dopant activation which can be many times the equilibrium value. Finally, the use of heterojunction contacts using Si–Ge in the context of elevated source/drain devices presents another way to achieve lower contact resistance.}, number={1-2}, journal={THIN SOLID FILMS}, author={Osburn, CM and Bellur, KR}, year={1998}, month={Nov}, pages={428–436} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1998, title={Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors}, volume={145}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838607}, abstractNote={Device drive current, parasitic resistance, and junction leakage current have been studied using silicided and non-silicided deep submicron elevated source/drain (ESD) n-channel metal oxide semiconductor field effect transistors (NMOSFETs). This study illustrated the effects of doping profile in the elevated S/D region, junction depth in the substrate, and doping level in the source/drain extension. Compared to devices having nonelevated junctions with the same substrate doping profile, MOSFETs with a profile-doped elevated S/D, used to contact an ultrashallow junction formed before selective epitaxial growth, had higher drive currents and demonstrated the ability of the elevated junction to reduce the extrinsic resistance. Measurements of drive currents in ESD devices showed that (i) the lightly doped region at the bottom of a profile-doped elevated layer introduces additional extrinsic resistance, and (ii) the locally deeper junction beneath the epi facets extends laterally toward the channel and shortens the drain extension length, thereby reducing the intrinsic resistance. Silicided devices had higher drive current and reduced parasitic resistance when the silicide/silicon interfacial dopant concentrations remained high (>1 x 10 20 /cm 3 ) after silicidation. The lowest total parasitic resistance was achieved when the elevated S/D was used to give a small contact resistance to a shallow junction and a moderately doped drain extension was used to lower the resistance of the source/drain extension tab.}, number={6}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1998}, month={Jun}, pages={2131–2137} }
 @inproceedings{srivastava_sun_bellur_bartholomew_o'neil_celik_osburn_masnari_ozturk_westhoff_et al._1997, title={A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Srivastava, A. and Sun, J. and Bellur, K. and Bartholomew, R. F. and O'Neil, P. and Celik, S. M. and Osburn, C. M. and Masnari, N. A. and Ozturk, M. C. and Westhoff, R. and et al.}, year={1997}, pages={571–585} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors}, volume={144}, ISSN={["1945-7111"]}, DOI={10.1149/1.1838066}, abstractNote={Ultrashallow elevated n'/p junctions (∼75 nm) incorporating selectively deposited epitaxial silicon layers were fabricated. The undoped epi layers (∼100 nm) were deposited on exposed diffusion areas in an Advanced Semiconductor Material Epsilon I system specifically designed for low thermal budget single-wafer processing. Shallow junctions (∼75 nm) were formed by ion implantation (As, 4 x 10 15 /cm 2 , 80 keV) into undoped epi layers and out-diffusion into the underlying substrate. Alternatively, an ion implanted (As, 4 x 10 15 /cm 2 , 60 keV) elevated layer was utilized to contact a shallow junction, which was formed (As, 1.5 x 10 15 /cm 2 , 15 keV) before the epi deposition. All junctions were annealed at 950°C for 10 s. Nonsilicided elevated junctions and conventional nonelevated (As, 1.5 x 10 15 /cm 2 , 15 keV) ones displayed very similar junction characteristics. Silicided nonelevated ultrashallow junctions, however, showed large reverse leakage current due to the substrate consumption. Both silicided elevated (post-epi and pre-epi) junctions exhibited excellent forward characteristics and low reverse leakage current. The difference in the reverse leakage characteristics of these two elevated junctions was attributed to the epi faceting formed at the sidewall edge of localized oxidation of silicon isolation. Deep submicron n = channel metal oxide semiconductor field effect transistors incorporating these junctions were also fabricated and electrically tested. Both elevated source/drain (S/D) devices show superior current driving capability compared to nonelevated ones as a result of much reduced parasitic resistance from contact source/drain junctions.}, number={10}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Sun, J and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA and Westhoff, R}, year={1997}, month={Oct}, pages={3659–3664} }
 @inproceedings{sun_bartholomew_bellur_srivastava_osburn_masnari_westhoff_1997, title={Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology}, booktitle={ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3)}, publisher={Pennington, NJ: Electrochemical Society}, author={Sun, J. and Bartholomew, R. F. and Bellur, K. and Srivastava, A. and Osburn, C. M. and Masnari, N. A. and Westhoff, R.}, year={1997}, pages={587–597} }
 @article{sun_bartholomew_bellur_srivastava_osburn_masnari_1997, title={The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.622606}, abstractNote={Deep submicron NMOSFETs with elevated source/drain (ESD) were fabricated using self-aligned selective epitaxial deposition and engineered ion implanted profiles in the elevated layers, Deeper source/drain (S/D) junctions give rise to improved drive current over shallower profiles when the same spacer thickness and LDD doping level are used, Shallower junctions, especially with the heavily-doped S/D residing in the elevated layer, give better immunity to drain-induced-barrier lowering (DLBL) and bulk punchthrough. Tradeoffs between short-channel behavior and drive current with regard to S/D junction depth and spacer thickness were further studied using process/device simulations to cover a broader range of structure parameters. Despite the existence of epi facets along the sidewall spacers, the elevated S/D could be used as a sacrificial layer for silicidation, without degradation of the low-leakage junctions. The effects of the elevated S/D doping profile on substrate current and hot-electron-induced degradation were measured and analyzed. The simulated results were used, for the first time, to define the range of spacer thickness and LDD doses that are required in order for the lightly-doped region in the elevated S/D to effectively suppress the lateral electric field.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sun, JJ and Bartholomew, RF and Bellur, K and Srivastava, A and Osburn, CM and Masnari, NA}, year={1997}, month={Sep}, pages={1491–1498} }
 @article{sun_bartholomew_bellur_oneil_srivastava_violette_ozturk_osburn_masnari_1996, title={Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition}, volume={429}, ISBN={["1-55899-332-0"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-429-343}, abstractNote={Abstract}, journal={RAPID THERMAL AND INTEGRATED PROCESSING V}, author={Sun, J and Bartholomew, RF and Bellur, K and ONeil, PA and Srivastava, A and Violette, KE and Ozturk, MC and Osburn, CM and Masnari, NA}, year={1996}, pages={343–347} }