Kashyap Bellur

Osburn, C. M., & Bellur, K. R. (1998, November 2). Low parasitic resistance contacts for scaled ULSI devices. THIN SOLID FILMS, Vol. 332, pp. 428–436. https://doi.org/10.1016/S0040-6090(98)01046-3

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1998). Parasitic resistance considerations of using elevated source/drain technology for deep submicron metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 145(6), 2131–2137. https://doi.org/10.1149/1.1838607

Srivastava, A., Sun, J., Bellur, K., Bartholomew, R. F., O'Neil, P., Celik, S. M., … Fowler, B. (1997). A 0.18 ?m CMOS technology for elevated source/drain MOSFETs using selective silicon epitaxy. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 571–585. Pennington, NJ: Electrochemical Society.

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). A comparative study of n(+)/p junction formation for deep submicron elevated source/drain metal oxide semiconductor field effect transistors. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 144(10), 3659–3664. https://doi.org/10.1149/1.1838066

Sun, J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., Masnari, N. A., & Westhoff, R. (1997). Parasitic resistance considerations of using elevated source/drain for deep submicron MOSFET technology. ULSI science and technology/1997: Proceedings of the Sixth International Symposium on UltraLarge Scale Integration Science and Technology (Proceedings (Electrochemical Society); v. 97-3), 587–597. Pennington, NJ: Electrochemical Society.

Sun, J. J., Bartholomew, R. F., Bellur, K., Srivastava, A., Osburn, C. M., & Masnari, N. A. (1997). The effect of the elevated source drain doping profile on performance and reliability of deep submicron MOSFET's. IEEE TRANSACTIONS ON ELECTRON DEVICES, 44(9), 1491–1498. https://doi.org/10.1109/16.622606

Sun, J., Bartholomew, R. F., Bellur, K., ONeil, P. A., Srivastava, A., Violette, K. E., … Masnari, N. A. (1996). Sub-half micron elevated source/drain NMOSFETs by low temperature selective epitaxial deposition. RAPID THERMAL AND INTEGRATED PROCESSING V, Vol. 429, pp. 343–347. https://doi.org/10.1557/proc-429-343