@inproceedings{narwal_rawat_kanale_cheng_agarwal_bhattacharya_baliga_hopkins_2023, title={Analysis and Characterization of Four-quadrant Switches based Commutation Cell}, volume={2023-March}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec43580.2023.10131312}, DOI={10.1109/APEC43580.2023.10131312}, abstractNote={A four-quadrant switch (FQS) blocks either polarity voltage and controls current flow in both directions. Unlike voltage-source converters, in which two-quadrant switches operate over a narrow voltage range, four-quadrant switches are required to operate over a wide range of both voltage and current in applications such as matrix converters and current-source converters. Furthermore, matrix converters require multi-step commutation schemes compared to two-step schemes for current-bidirectional switch based voltage-source converters and voltage-bidirectional switch based current-source converters. This paper provides a generalized overview of commutation schemes used for two and four quadrant switches based two-level commutation cells, identifies comparison indices for FQS commutation schemes, and discusses the need for adaptive commutation-step times for wide voltage and current variation applications. Also, the static and dynamic characteristics of 1.2 kV rated FQS implementations utilizing commercial SiC MOSFETs from four different manufacturers and novel monolithic SiC BiDirectional Field Effect Transistor (BiDFET) have been reported.}, booktitle={2023 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Narwal, Ramandeep and Rawat, Shubham and Kanale, Ajit and Cheng, Tzu-Hsuan and Agarwal, Aditi and Bhattacharya, Subhashish and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2023}, month={Mar}, pages={209–216} }
@article{bhattacharya_narwal_shah_baliga_agarwal_kanale_han_hopkins_cheng_2023, title={Power Conversion Systems Enabled by SiC BiDFET Device}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237060}, DOI={10.1109/MPEL.2023.3237060}, abstractNote={The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Bhattacharya, Subhashish and Narwal, Ramandeep and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Agarwal, Aditi and Kanale, Ajit and Han, Kijeong and Hopkins, Douglas C. and Cheng, Tzu-Hsuan}, year={2023}, month={Mar}, pages={39–43} }
@article{baliga_hopkins_bhattacharya_agarwal_cheng_narwal_kanale_shah_han_2023, title={The BiDFET Device and Its Impact on Converters}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237059}, DOI={10.1109/MPEL.2023.3237059}, abstractNote={The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable d.c. link capacitors used in the popular voltage-source inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish and Agarwal, Aditi and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Kanale, Ajit and Shah, Suyash Sushilkumar and Han, Kijeong}, year={2023}, month={Mar}, pages={20–27} }
@misc{kanale_cheng_narwal_agarwal_baliga_bhattacharya_hopkins_2022, title={Design Considerations for Developing 1.2 kV 4H-SiC BiDFET-enabled Power Conversion Systems}, ISSN={["2329-3721"]}, url={http://dx.doi.org/10.1109/ECCE50734.2022.9947715}, DOI={10.1109/ECCE50734.2022.9947715}, abstractNote={Bidirectional switches are essential for cycloconverter and matrix converter applications to facilitate single-stage AC-AC conversion without intermediate energy storage elements. The 1.2 kV 4H-SiC BiDFET was developed as the first monolithic bidirectional SiC power transistor. This paper describes the design considerations taken into account while creating the BiDFET device and developing custom packages for housing the switch in discrete form for low power applications and in module form for high-power applications. The realized switches are characterized for their on-state and switching performance. The versatility of the BiDFET device is demonstrated by operating a single BiDFET H-bridge in voltage-source-inverter and current-source-inverter topologies only by varying the gate bias on the individual BiDFETs and reversing the input-output connections.}, journal={2022 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Agarwal, Aditi and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2022}, month={Oct} }
@article{agarwal_baliga_2022, title={Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters}, volume={10}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2022.3152489}, abstractNote={Significant impact of the ion-implant straggle of the P+ shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modeling. The P+ region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of $0.7 \mu \text{m}$ . The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and $0.5 \mu \text{m}$ using both accumulation and inversion mode channels. The presence of the P+ shielding region ion-implant straggle is shown to: (a) increase specific on-resistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P+ shielding region lateral straggle on device cell optimization is an important contribution of this paper.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Baliga, B. J.}, year={2022}, pages={245–255} }
@article{kanale_agarwal_baliga_bhattacharya_2022, title={Monolithic Reverse Blocking 1.2 kV 4H-SiC Power Transistor: A Novel, Single-Chip, Three-Terminal Device for Current Source Inverter Applications}, volume={37}, ISSN={["1941-0107"]}, url={https://doi.org/10.1109/TPEL.2022.3166933}, DOI={10.1109/TPEL.2022.3166933}, abstractNote={Current sourceinverters (CSIs) require power switches with first quadrant current conduction and gate-controlled output characteristics as well as reverse blocking capability. Experimental demonstration of a SiC monolithic reverse blocking transistor (MRBT) suitable for CSI applications is described in this letter. The proposed device is based on the integration of a SiC JBS diode with a SiC power mosfet on the same chip. The cathode of the SiC JBS diode is connected to the drain of the SiC power mosfet by their common N+ substrate. The proposed device structure creates a novel SiC-based unipolar single-chip three-terminal transistor with reverse blocking capability. The measured characteristics of a 1.2 kV 4H-SiC MRBT, fabricated in a commercial six-inch wafer foundry, are reported in this letter. The devices show a diode-like on-state characteristic with a low knee voltage of 1.3 V and an on-state voltage drop of 2.8 V at 5 A. The measured reverse transfer capacitance and output capacitance for the MRBT at a drain bias of 2 and 1000 V are a factor of ∼3x and ∼1.6x smaller than the measured values for the internal mosfet device. Switching measurements show a 12% reduction in the gate-drain charge for the MRBT compared with the internal mosfet which is favorable for reducing switching losses.}, number={9}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Kanale, Ajit and Agarwal, Aditi and Baliga, B. Jayant and Bhattacharya, Subhashish}, year={2022}, month={Sep}, pages={10112–10116} }
@article{agarwal_baliga_2022, title={Temperature Dependence of 55 nm Gate Oxide, 2.3 kV SiC Power JBSFETs With Linear, Hexagonal, and Octagonal Cell Layouts}, volume={69}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2022.3148058}, abstractNote={The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below $1~\mu \text{A}$ even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ ] and FOM[ $ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ ] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode.}, number={3}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Baliga, B. Jayant}, year={2022}, month={Mar}, pages={1233–1241} }
@article{agarwal_baliga_2021, title={2.3 kV 4H-SiC Planar-Gate Accumulation Channel Power JBSFETs: Analysis of Experimental Data}, volume={9}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2021.3058662}, abstractNote={Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 $\mu \text{m}$ and gate oxide thickness of 55 nm. The Schottky contact width was chosen to achieve an on-state voltage drop of below 2.8 V in the 3rd quadrant for the integrated JBS diodes. Lower specific on-resistance of the Hexagonal and higher values for the Octagonal cell topologies compared with the conventional Linear cell design were experimentally observed. New analytical models developed for the various cell topologies reveal that these differences arise from changes in the relative contributions from the N+ source contact, channel, and accumulation region resistances. The analysis reported in this article provides new insight on the importance of the accumulation layer resistance to the Octagonal cell topology. Numerical simulation reveal that the measured leakage current behavior correlates with the electric field observed at the Schottky contact within the 2.3 kV JBSFET cell structures. The leakage current begins to rise rapidly when the electric field exceeds 1.5 MV/cm due to Schottky barrier lowering and enhanced tunneling. The reverse transfer capacitance and gate charge were found to correlate with the JFET region density within the different cell topologies. The measured on-state voltage drop in the third quadrant was found to correlate with the JBS diode density in the cell topologies. A new high-frequency figure-of-merit [ $\text{V}_{\mathrm{ f3Q}}*Q_{\mathrm{ gd,sp}}$ ] is proposed for SiC JBSFETs. The Octagonal cell designs are found to be the most suitable for high frequency applications of 2.3 kV JBSFETs based on the HF-FOMs [ $\text{R}_{\mathrm{ on}}*Q_{\mathrm{ gd}}$ ] and [ $\text{V}_{\mathrm{ f3Q}}$ *Q $_{\mathrm{ gd,sp}}$ ].}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Baliga, B. J.}, year={2021}, pages={324–333} }
@article{agarwal_baliga_francois_maxwell_berliner_papageorge_2021, title={3.3 kV 4H-SiC Planar-Gate MOSFETs Manufactured using Gen-5 PRESiCE (TM) Technology in a 4-inch Wafer Commercial Foundry}, ISSN={["1558-058X"]}, DOI={10.1109/SOUTHEASTCON45413.2021.9401931}, abstractNote={The successful fabrication of 3.3 kV 4H-SiC Planar-Gate MOSFETs in a 4" commercial foundry using the Gen-5 PRESiCE™ technology is reported in this paper. Both Accumulation-channel MOSFETs (ACCUFETs) and Inversion-channel MOSFETs (INVFETs) were successfully manufactured. The electrical characteristics of the two types of fabricated devices are compared in this paper. The wafer yield data indicates that gate-source shorts were the yield-limiting criteria. This effort establishes a second source foundry for manufacturing SiC power devices in the United States.}, journal={SOUTHEASTCON 2021}, author={Agarwal, Aditi and Baliga, Jayant and Francois, Michel M. A. and Maxwell, Ed and Berliner, Nathaniel and Papageorge, Marc}, year={2021}, pages={555–558} }
@article{agarwal_han_baliga_2021, title={650-V 4H-SiC Planar Inversion-Channel Power JBSFETs With 55-nm Gate Oxide: Relative Performance of Three Cell Types}, volume={68}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2021.3067921}, abstractNote={Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, month={May}, pages={2395–2400} }
@article{agarwal_kanale_baliga_2021, title={Advanced 650 V SiC Power MOSFETs With 10 V Gate Drive Compatible With Si Superjunction Devices}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2020.3017215}, abstractNote={Advanced SiC planar-gate power MOSFETs have been successfully manufactured in a 6-inch commercial foundry with device structures optimized for operation with gate drive voltage of 10 V, compatible with gated drive voltage for Si superjunction products. The electrical characteristics of three advanced SiC MOSFET options are described in this article and compared with those of a state-of-the art Si superjunction MOSFET. The new advanced SiC power MOSFETs are demonstrated to exhibit superior on-state and switching losses with significantly better body-diode reverse recovery performance. Their short-circuit withstand time is also found to be significantly longer than typical commercially available planar-gate SiC power MOSFETs. These improved characteristics make the advanced SiC power MOSFETs suitable replacements for Si superjunction transistors to enhance high frequency circuit performance.}, number={3}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Agarwal, Aditi and Kanale, Ajit and Baliga, B. Jayant}, year={2021}, month={Mar}, pages={3335–3345} }
@article{agarwal_han_baliga_2021, title={Assessment of Linear, Hexagonal, and Octagonal Cell Topologies for 650 V 4H-SiC Inversion-Channel Planar-Gate Power JBSFETs Fabricated With 27 nm Gate Oxide Thickness}, volume={9}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.3040353}, abstractNote={A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planar-gate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 nm gate oxide thickness allows operation of these JBSFETs at a gate bias of 15 V compared with 20 V used in previous reports for devices with 55 nm gate oxide thickness. The width for the Schottky contact was varied to optimize the performance of the JBS diode in the third quadrant for each cell topology. An on-state voltage drop of 2.5 V or less was achieved in the third quadrant for all the cell topologies by current flow through the integrated JBS diode, satisfying the objective of effectively by-passing the MOSFET body diode. The best breakdown voltage was achieved using the Octagonal cell topology with a half-cell Schottky contact width of 1.1 $\mu \text{m}$ . It had a breakdown voltage of 850 V with a low leakage current of less than 5 nA at 650 V. The Linear cell (with half-cell Schottky contact width of 1.0 $\mu \text{m}$ ) and the Octagonal cell (with half-cell Schottky contact width of 2.8 $\mu \text{m}$ ) had blocking voltages of 800 V. The hexagonal cell topology (with half-cell Schottky contact width of 1.5 $\mu \text{m}$ ) had the worst blocking voltage of 715 V. Numerical simulation results are provided to show that the leakage current in all cell topologies begins to increase when the electric field at the Schottky contact exceeds 1.5 MV/cm. The lowest specific on-resistance was obtained with the hexagonal cell topology but its gate-drain charge was $2\times $ larger than the conventional Linear cell design. The Octagonal cell topology with half-cell Schottky contact width of 1.1 $\mu \text{m}$ had the same specific on-resistance as the Linear cell case with $2\times $ smaller gate-drain charge. This work demonstrates for the first time that excellent High-Frequency Figures-of-Merit can be achieved with a reduced gate drive voltage of 15 V for 650 V SiC JBSFETs by using a smaller gate oxide thickness of 27 nm and the Octagonal cell topology.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, pages={79–88} }
@inproceedings{kanale_narasimhan_cheng_agarwal_shah_baliga_bhattacharya_hopkins_2021, title={Comparison of the Capacitances and Switching Losses of 1.2 kV Common-Source and Common- Drain Bidirectional Switch Topologies}, ISBN={9781665401821}, url={http://dx.doi.org/10.1109/WiPDA49284.2021.9645130}, DOI={10.1109/WiPDA49284.2021.9645130}, abstractNote={Bidirectional, or four-quadrant switches (FQS) can be designed as back-to-back MOSFETs connected in common-drain (CD) or common-source (CS) topologies. CDFQS and CS-FQS assembled from discrete 1.2 kV commercially available SiC power MOSFETs were characterized to obtain capacitance and switching loss values. The CD-FQS exhibited a 1. 17x larger turn-on loss compared to the CS-FQS, while the CS-FQS exhibited a 1. 52x larger turn-off loss compared to the CD-FQS. The CS-FQS exhibited a lower input capacitance, while the CD-FQS exhibited a lower output and reverse transfer capacitance.}, booktitle={2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Kanale, Ajit and Narasimhan, Sneha and Cheng, Tzu-Hsuan and Agarwal, Aditi and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2021}, pages={112–117} }
@article{shah_narwal_bhattacharya_kanale_cheng_mehrotra_agarwal_baliga_hopkins_2021, title={Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for Solar PV Applications}, ISSN={["2329-3721"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85123361428&partnerID=MN8TOARS}, DOI={10.1109/ECCE47101.2021.9595533}, abstractNote={Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, $46 \mathrm{m}\Omega$, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, $400\mathrm{V}/277\mathrm{V}_{{\mathrm {RMS}}}$ hardware prototype are finally presented to verify the design process.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Shah, Suyash Sushilkumar and Narwal, Ramandeep and Bhattacharya, Subhashish and Kanale, Ajit and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2021}, pages={568–575} }
@article{agarwal_baliga_2021, title={Performance Enhancement of 2.3 kV 4H-SiC Planar-Gate MOSFETs Using Reduced Gate Oxide Thickness}, volume={68}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2021.3102473}, abstractNote={Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( ${R}_{\mathrm {ON},\text {sp}}$ ) and high-frequency figures-of-merit (FOM[ ${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ ], FOM[ ${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ ]) were improved by a factor of $1.3\times $ by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the ${R}_{\mathrm {ON},\text {sp}}$ and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.}, number={10}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Baliga, B. Jayant}, year={2021}, month={Oct}, pages={5029–5033} }
@inproceedings{kanale_cheng_shah_han_agarwal_baliga_hopkins_bhattacharya_2021, title={Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487410}, DOI={10.1109/APEC42165.2021.9487410}, abstractNote={The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Shah, Suyash Sushilkumar and Han, Kijeong and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish}, year={2021}, month={Jun}, pages={1267–1274} }
@article{agarwal_han_baliga_2020, title={2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge}, volume={8}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.2991355}, abstractNote={2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8 $\times$ better than that of the conventional MOSFETs with no difference in specific on-resistance.}, number={1}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020}, pages={499–504} }
@article{agarwal_han_baliga_2020, title={2.3-kV, 5-A 4H-SiC Ti and Ni JBS Rectifiers manufactured in Commercial Foundry: Impact of Implant Lateral Straggle}, DOI={10.1109/WiPDAAsia49671.2020.9360272}, abstractNote={This paper reports characteristics of 2.3-kV 5-A 4H-SiC Junction Barrier controlled Schottky (JBS) rectifiers manufactured in a 6-inch commercial foundry. Two types (Ni and Ti Schottky contact metal) of JBS rectifiers were successfully fabricated. The electrical performance of the Ni and Ti JBS rectifiers is compared at temperatures up to 1500 C. The on-state voltage drop (@ 5 A) of the Ti devices increased from 1.4 to 1.8 V with increasing temperature while that for Ni devices increased from 2.0 to 2.3 V, maintaining values well below that of the SiC P-N junction as required for a JBS diode. The leakage current for the Ni JBS diodes remained below 2 nA @ 500V even up to 1500 C. In contrast, an increase in leakage current to an acceptable level of 100 nA @ 500V was observed for the Ti JBS diodes at 150°C due to its lower barrier height.Analytical modelling indicated that lateral straggle of the $P^{+}$ ion-implant plays an important role in determining the measured on-state voltage drop and reverse leakage characteristics. Simulations were performed to confirm the effect of lateral implant straggle. The simulations demonstrated that lateral implant straggle increases the on-resistance and reduces the leakage current of the JBS rectifier but has no effect on the knee voltage. The experimental results in this paper demonstrate that 4H-SiC JBS rectifiers with 2.3 kV blocking voltage can be manufactured using either Ni or Ti Schottky contacts with excellent on-state voltage drop and leakage current up to 150$^{0}C$.}, journal={2020 IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS IN ASIA (WIPDA ASIA)}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020} }
@article{agarwal_han_jayant baliga_2020, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V (vol 40, pg 1792, 2019)}, volume={41}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2956966}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Jayant Baliga, B.}, year={2020}, month={Jan}, pages={195–195} }
@article{agarwal_han_baliga_2020, title={Comparison of 2.3-kV 4H-SiC Accumulation-Channel Planar Power MOSFETs Fabricated With Linear, Square, Hexagonal, and Octagonal Cell Topologies}, volume={67}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2020.3005632}, abstractNote={The performance of four cell topologies is compared for 2.3-kV 4H-SiC power MOSFETs fabricated in a commercial 6-in foundry. The devices were simultaneously manufactured with the same channel length (0.5 $ {\mu } \text{m}$ ), JFET width (1.1 $ {\mu } \text{m}$ ), and gate oxide thickness (55 nm) for comparison. In addition, an octagonal cell design with a JFET width of 1.5 $ {\mu } \text{m}$ was included for comparison. The square and hexagonal cell designs had the lowest specific ON-resistance, but their breakdown voltage was found to be reduced below 2.3 kV due to sharp cell corners. The smallest reverse transfer capacitance and gate charge were observed for the octagonal cell design with significantly larger (~5 $\times $ ) values for the square and hexagonal designs. The high-frequency figure-of-merit HF-FOM[ ${R}_{\mathrm{\scriptscriptstyle ON}}{\ast } {C}_{\text {rss}}$ ] for the octagonal cell design was $3.5\times $ superior to the hexagonal and square cells and $1.5\times $ better than the linear cell. Its high-frequency figure-of-merit HF-FOM[ ${R}_{\mathrm{\scriptscriptstyle ON}} {\ast } {Q}_{\text {gd}}$ ] was $1.5\times $ superior to the hexagonal and square cells and $1.2\times $ better than the linear cell. This work demonstrates that the square and hexagonal cells are the best for low-frequency applications, whereas the octagonal cell design is the most suitable for achieving the best high-frequency performance of 2.3-kV 4H-SiC power MOSFETs.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2020}, pages={3673–3678} }
@article{agarwal_han_baliga_2019, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2942259}, abstractNote={The measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated in a 6 inch commercial foundry with 27 nm gate oxide thickness are compared with 55 nm gate oxide devices. The High-Frequency Figures-of-Merit (HF-FOMs) of the SiC MOSFETs with 27 nm gate oxide were found to surpass that of commercially available 600 V P7 Si CoolMOS products for the first time. Statistical parametric distribution data and wafer-maps for the 27 nm devices are provided to demonstrate that excellent yield and uniformity can be achieved with the reduced gate oxide thickness. These devices can be operated at 15 V gate bias compatible with IGBT gate drivers.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={Nov}, pages={1792–1795} }
@article{agarwal_han_baliga_2019, title={Impact of Cell Topology on Characteristics of 600V 4H-SiC Planar MOSFETs}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2908078}, abstractNote={This letter compares the measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated with four different cell topologies (Linear, Square, Hexagonal, and Octagonal) for the first time. The High-Frequency Figures-of-Merit (HF-FOMs) of these devices were compared with the commercially available SiC device and the Si CoolMOS product. It was found that the HF-FOMs of the 600-V SiC product and our fabricated conventional Linear cell device are much worse in comparison to the Si CoolMOS product. However, the 600 V SiC power MOSFET with comparable performance to the Si CoolMOS product could be achieved by using the Octagonal cell topology.}, number={5}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={May}, pages={773–776} }