@article{anurag_acharya_bhattacharya_weatherford_parker_2022, title={A Gen-3 10-kV SiC MOSFET-Based Medium-Voltage Three-Phase Dual Active Bridge Converter Enabling a Mobile Utility Support Equipment Solid State Transformer}, volume={10}, ISSN={["2168-6785"]}, url={https://doi.org/10.1109/JESTPE.2021.3069810}, DOI={10.1109/JESTPE.2021.3069810}, abstractNote={The emergence of medium-voltage silicon carbide (SiC) power semiconductor devices, in ranges of 10–15 kV, has led to the development of simple two-level converter systems for medium-voltage applications. A medium-voltage mobile utility support equipment-based three-phase solid state transformer (MUSE-SST) system, based on Gen3 10 kV SiC MOSFETs, is developed to interconnect a three-phase 4160 V/60 Hz grid to a three-phase 480 V/60 Hz grid to provide a shore-to-ship power interface for naval vessels. The MUSE-SST system consists of three power conversion stages, namely, MVac/MVdc stage (MV: active front-end converter), MVdc/LVdc stage (dual active bridge converter), and LVdc/LVac stage (LV: active front-end converter). The galvanic isolation is introduced in the MVdc/LVdc stage using MV/LV high-frequency transformers (HFTs). This article demonstrates the operation of the three-phase Y– $\Delta $ connected dual active bridge converter used in the MVdc/LVdc stage of the MUSE-SST system. Equations for phase currents, power flow, and zero-voltage switching (ZVS) boundaries are derived for all possible modes for the three-phase Y– $\Delta $ configuration. A detailed parasitic simulation model is derived by measuring and experimentally verifying the parasitic elements of the HFT. A brief discussion regarding the design considerations required for the hardware development of the medium- and low-voltage sides of the three-phase dual active bridge converter is also provided. Successful tests demonstrating the operation and feasibility of the medium-voltage dual active bridge converter, at medium-voltage levels (7.2 kV dc-link voltage), are shown. The results indicate that these devices can accelerate the growth and deployment of the medium-voltage SiC-based converter for isolated and bidirectional medium- to low-voltage dc systems.}, number={2}, journal={IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish and Weatherford, Todd R. and Parker, Andrew A.}, year={2022}, month={Apr}, pages={1519–1536} }
 @article{anurag_acharya_kolli_bhattacharya_weatherford_parker_2022, title={A Three-Phase Active-Front-End Converter System Enabled by 10-kV SiC MOSFETs Aimed at a Solid-State Transformer Application}, volume={37}, ISSN={["1941-0107"]}, url={https://doi.org/10.1109/TPEL.2021.3131262}, DOI={10.1109/TPEL.2021.3131262}, abstractNote={The use of high-voltage silicon carbide (SiC) devices can eliminate multilevel and cascaded converters and their complicated control strategies, making converter systems simple and reliable. A three-phase two-level voltage-source converter system serves as a simple converter system for interfacing any dc source to a three-phase grid. However, when the high-voltage devices are used in two-level converters, they are exposed to a high-voltage peak stress and a high $dv/dt$ (up to 100 kV/$\mu$s). Operating these semiconductor devices at these stress levels requires careful design not only of the semiconductor die and the module, but also of the gate drivers, busbars, and passive filters. This article demonstrates the operation of 10-kV SiC mosfets and discusses the design considerations, advantages, and challenges associated with the operation of the three-phase two-level medium-voltage converter system used as the active-front-end converter system. Reliable operation of the medium-voltage converter system requires the development of reliable high-voltage modules and auxiliary parts, such as gate drivers, busbars, inductors, voltage and current sensors, and proper design of the controller system. Successful tests demonstrating continuous field operation of the medium-voltage active-front-end converter at a nominal rating of 7.2-kV dc-link voltage is demonstrated for the first time in the literature. The results indicate that these devices can accelerate the growth and deployment of medium-voltage SiC devices for field operation, as demonstrated by the operation inside the mobile container.}, number={5}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Kolli, Nithin and Bhattacharya, Subhashish and Weatherford, Todd R. and Parker, Andrew A.}, year={2022}, month={May}, pages={5606–5624} }
 @article{kim_anurag_acharya_bhattacharya_2021, title={Analytical Study of SiC MOSFET Based Inverter Output dv/dt Mitigation and Loss Comparison With a Passive dv/dt Filter for High Frequency Motor Drive Applications}, volume={9}, ISSN={["2169-3536"]}, url={https://doi.org/10.1109/ACCESS.2021.3053198}, DOI={10.1109/ACCESS.2021.3053198}, abstractNote={Fast switching characteristic of wide bandgap devices enables high switching frequency of power devices and thereby, can facilitate high fundamental frequency operation of electrical machines. However, with the switching transition times in orders of tens of nanoseconds, the high dv/dt is observed across the switching device. The high dv/dt experienced by the switches, and consequently by the machine, can degrade winding insulations or bearings over a period of time. Therefore, it is imperative to maintain the dv/dt below recommended values depending on the machine insulation. The dv/dt across the devices can be adjusted by varying the gate resistance. A high value of gate resistance, however, introduces additional switching losses on the device. Using different dv/dt filtering techniques can also help to control the dv/dt on the machine terminals. These techniques do not increase the switching losses on the device. However, it introduces additional losses in the filter resistors and also increases the cost of the system. In this paper, an analysis based on the impact of gate resistance on the dv/dt across the machine, and the corresponding losses is carried out. An analytical dv/dt filter design strategy is proposed to limit the dv/dt to a particular value. With the proposed design scheme, the value of each filter component can be easily obtained, and filter losses can be estimated accurately. Lastly, a comparison is performed on the basis of efficiency between these two techniques.}, journal={IEEE ACCESS}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kim, Heonyoung and Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish}, year={2021}, pages={15228–15238} }
 @article{narasimhan_anurag_bhattacharya_2021, title={Comparative Study of a 3.3 kV SiC-based Voltage and Current Source Inverter for High-Speed Motor Drive Applications}, ISSN={["2150-6078"]}, DOI={10.1109/ECCE-Asia49820.2021.9479066}, abstractNote={Current source inverters (CSIs) is a technology typically used for high power medium voltage (MV) applications. With the emergence of wide-bandgap (WBG) technology, the CSI has been widely looked into for aerospace applications, MV solid-state transformers (SST), electric vehicles, traction applications, and renewable energy systems. This paper looks into the potential of MV-based CSI inverter for high-speed machine (HSM) applications compared to MV-based voltage source inverters (VSIs) inverter in terms of efficiency, reflected voltage, and sizing of passive components. It also compares the effects of dead-time in the VSI and effects of overlap-time in the CSI. The fault tolerance of permanent magnet motor-based HSM for VSI and CSI-based systems is discussed. The switch configuration required for a WBG based MV-based CSI is discussed.}, journal={2021 IEEE 12TH ENERGY CONVERSION CONGRESS AND EXPOSITION - ASIA (ECCE ASIA)}, author={Narasimhan, Sneha and Anurag, Anup and Bhattacharya, Subhashish}, year={2021}, pages={2211–2217} }
 @article{kolli_parashar_kokkonda_anurag_kumar_bhattacharya_veliadis_2021, title={Design Considerations of Three Phase Active Front End Converter for 13.8 kV Asynchronous Microgrid Power Conditioning System enabled by Series Connection of Gen-3 10 kV SiC MOSFETs}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE47101.2021.9594975}, abstractNote={The recent growth in power generation using renewable energy sources has led to extensive research and development of robust and resilient power converters, which can integrate them with the medium voltage (MV) grids (13.8 kV,60Hz). Conventional power converters need a line frequency transformer for their integration to the MV grid, which increases the overall footprint and installation cost of the system. Therefore, a compact and lightweight alternative are required for largescale integration of the renewable energy source to the MV grid. With the advent of high voltage SiC MOSFETs, the operating frequency of grid converter can be increased up to 10-20 kHz, thus significantly reducing the size of filter inductors. The use of these devices in multi-level configurations with series-connected devices facilitates the design of power converters that can interface directly with MV grid, eliminating the need for line frequency transformers. The converter presented in this paper is designed to interface a 13.8 kV three-phase grid to a dc link of 24 kV. A three-level neutral point clamped (3L-NPC) topology enabled by series-connected 10 kV 15 A SiC MOSFETs and 10 kV 15 A SiC JBS diodes is presented. This paper focuses on the advantages, design considerations, and challenges associated with a medium voltage 3L-NPC converter. Experimental results show the successful operation of series-connected 10 kV 15 A SiC MOSFETs and JBS Diodes at medium voltage levels and highlights the series connection that is realized with snubber circuits for voltage balancing.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Kolli, Nithin and Parashar, Sanket and Kokkonda, Raj Kumar and Anurag, Anup and Kumar, Ashish and Bhattacharya, Subhashish and Veliadis, Victor}, year={2021}, pages={1211–1218} }
 @article{agarwal_anurag_kolli_kumar_bhattacharya_2021, title={Design considerations of 6.5kV enabled three-level and 10kV enabled two-level medium voltage SST}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE47101.2021.9595367}, abstractNote={The advent of medium voltage silicon carbide (SiC) power semiconductor devices (6.5kV and 10 kV) has opened up the possibilities of looking into different converter topologies for the MV grid interfaced applications. A medium voltage mobile utility support equipment-based three-phase solid-state transformer (MUSE-SST) system is one such application aimed to interconnect a three-phase 4160 V/60 Hz grid to a three-phase 480 V/60 Hz grid to provide a shore-to-ship power interface for naval vessels. The system can be realized by both 10 kV SiC MOSFET and 6.5kV SiC MOSFET employing a two-level and three-level architecture respectively. The aim of this paper is to understand the thermal challenges and provides detailed design considerations of the two MV device-based architectures for a system scale-up to 500kVA rating. Device characteristics for both 6.5kV and 10kV SiC MOSFETs have been evaluated from experimental results. Based on these experimental data, the thermal performance of these devices enabled converter architecture is compared using elctro-thermal simulation-based loss comparison.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Agarwal, Apoorv and Anurag, Anup and Kolli, Nithin and Kumar, Ashish and Bhattacharya, Subhashish}, year={2021}, pages={282–289} }
 @article{kokkonda_kumar_anurag_kolli_parashar_bhattacharya_2021, title={Medium Voltage Shore-to-Ship Connection System Enabled by Series Connected 3.3 kV SiC MOSFETs}, ISSN={["1048-2334"]}, DOI={10.1109/APEC42165.2021.9487119}, abstractNote={Increasing concern about the environmental impact of ships has made Shore-to-Ship (STS) power an attractive solution for ship owners and port authorities worldwide in reducing emissions at ports. Existing shore-to-ship solutions for 0.1 MVA to 5 MVA applications employ silicon (Si) IGBT based static frequency converters. Recent developments in high voltage silicon carbide (SiC) devices have facilitated improvement in efficiency and power density of medium voltage (MV) converters in various applications. This paper proposes an MV STS system enabled by series connection of three 3.3 kV SiC MOSFETs, which shows the potential for improved power density and efficiency compared to existing Si IGBT based solutions. A 100 kVA 3-phase two-level voltage source converter (VSC) with series connected 3.3 kV SiC MOSFETs is designed and demonstrated. Experimental results for the series connected 3.3kV SiC MOSFET based converter is shown at 6 kV dc link voltage to validate the design and operation of such a system. Successful demonstration of a MV converter system enabled by series connection of high voltage SiC MOSFETs can open up opportunities to replace conventional Si IGBT based converters with SiC MOSFET based converters in applications interfacing with medium voltage grid.}, journal={2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021)}, author={Kokkonda, Raj Kumar and Kumar, Ashish and Anurag, Anup and Kolli, Nithin and Parashar, Sanket and Bhattacharya, Subhashish}, year={2021}, pages={1380–1387} }
 @article{anurag_acharya_bhattacharya_2021, title={Solid State Transformer for Medium Voltage Grid Applications Enabled by 10 kV SiC MOSFET based Three-Phase Converter Systems}, ISSN={["2150-6078"]}, DOI={10.1109/ECCE-Asia49820.2021.9479336}, abstractNote={The emergence of wide bandgap semiconductors in power electronics has made it possible to manufacture medium voltage (MV) devices with low on-state resistance and offer fast switching transitions. This has enabled high switching frequencies in MV applications, which reduces the size and weight of the magnetic components and has opened up many opportunities in the field of power transmission and distribution. With the increasing popularity of MVac and MVdc microgrids, it has become necessary to have suitable MVac/MVdc, MVac/MVac, or MVac/LVac converters to integrate MVac systems with AC or DC microgrids. On account of this, an MV solid-state transformer (MV-SST) enabled by 10 kV SiC MOSFETs is developed to integrate an MV grid of 4.16 kV to a low voltage (LV) grid of 480 V. The MV-SST is divided into three stages: MVac/MVdc stage, MVdc/LVdc stage, and LVdc/LVac stage. These three stages ensure an SST operation to integrate MVac and LVac grids and provide an option to integrate DC loads or DC grids at the DC ports. This paper discusses the design, development, and operation of the 10 kV SiC MOSFETs based SST. A concise description of the hardware challenges in developing the MV-SST system is also shown. A brief description of the design aspects of different parts of the system (MVac/MVdc stage, MVdc/LVdc stage, and LVdc/LVac stage) is highlighted. Stability analysis for integrating the different converter systems is also provided to ensure that the system remains stable in its rated operating conditions. The operation and feasibility of the MV-SST system are demonstrated by experimental results.}, journal={2021 IEEE 12TH ENERGY CONVERSION CONGRESS AND EXPOSITION - ASIA (ECCE ASIA)}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish}, year={2021}, pages={906–913} }
 @article{anurag_acharya_bhattacharya_2020, title={An Accurate Calorimetric Loss Measurement Method for SiC MOSFETs}, volume={8}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/jestpe.2019.2920935}, DOI={10.1109/jestpe.2019.2920935}, abstractNote={An accurate measurement of conduction and switching losses in the power semiconductor devices is necessary in order to design and evaluate the thermal management system of modern converter systems. Conventionally, electrical measurement methods, such as the double-pulse tests (DPTs), are used for measuring the switching losses. However, with the advent of wide-bandgap (WBG) devices that have fast switching transients, it is rather difficult to capture the waveforms accurately during switching transitions, and consequently, the measurement of switching loss becomes inaccurate. In addition, the measurement of switching waveforms depends on the voltage and current probes, as well as the oscilloscope used for the measurement, which makes this method prone to errors. This necessitates the use of measurement methods, which can provide much higher accuracy than the existing conventional electrical methods. Calorimetric methods are based on comparatively slow temperature measurements and do not rely on the measurements of fast switching transitions of voltages and currents, thus eliminating the demand for measuring fast switching transitions. This paper presents an accurate calorimetric method for measuring the device losses, which can be used to determine individual loss components accurately (conduction, turn-on, and turn-off losses). In addition to the turn-on and turn-off losses, this method can evaluate the charging and discharging losses of the device. The novelty of the method lies in the fact that a single setup can be used to measure all possible losses that can occur in a device during converter operation. The calorimetric test setup is described, and a novel modulation scheme is introduced, which enables the segregation of the individual losses. The experimental test setup is built and the method is verified by measuring the losses of a 900-V, 23-A Wolfspeed C3M0120090D SiC MOSFET.}, number={2}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish}, year={2020}, month={Jun}, pages={1644–1656} }
 @article{acharya_anurag_bhattacharya_pellicone_2020, title={Performance Evaluation of a Loop Thermosyphon-Based Heatsink for High-Power SiC-Based Converter Applications}, volume={10}, ISSN={2156-3950 2156-3985}, url={http://dx.doi.org/10.1109/tcpmt.2019.2923332}, DOI={10.1109/tcpmt.2019.2923332}, abstractNote={Thermal management system (TMS) of a power converter directly dictates the available power rating, power density, semiconductor module reliability, and its operating lifetime. For the latest-generation wide bandgap (WBG) semiconductor device-based converters, it is challenging to extract the generated heat from the devices due to smaller die area as compared to its silicon (Si) counterparts. In this paper, the thermal performance of a new loop thermosiphon-based TMS for silicon carbide (SiC) semiconductor device-based power conversion system is presented. The working principle and design of the TMS are shown, and the performance of the designed TMS in both transient and steady-state conditions of power dissipation is evaluated. Furthermore, an accurate thermoelectrical model of the TMS is presented, and the circuit parameters are quantified by experimental results. This analysis helps to estimate the device junction temperature in real time during converter operation. Moreover, detailed simulations are carried out with the derived TMS thermal model to evaluate its performance at low fundamental frequencies at rated currents. The experimental results and the simulation studies indicate that the TMS offers a low thermal resistance and can extract a large amount of heat without increasing the device junction temperatures beyond their rated values. Furthermore, the designed TMS is able to maintain the junction temperature ripples at low fundamental frequencies within small values, which helps to increase the lifetime of the power modules significantly, as compared to conventional heatsinks.}, number={1}, journal={IEEE Transactions on Components, Packaging and Manufacturing Technology}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Acharya, Sayan and Anurag, Anup and Bhattacharya, Subhashish and Pellicone, Devin}, year={2020}, month={Jan}, pages={99–110} }
 @article{anurag_acharya_bhattacharya_weatherford_2020, title={Thermal Performance and Reliability Analysis of a Medium-Voltage Three-Phase Inverter Considering the Influence of High $dv/dt$  on Parasitic Filter Elements}, volume={8}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/jestpe.2019.2952570}, DOI={10.1109/jestpe.2019.2952570}, abstractNote={In recent years, the use of silicon carbide (SiC) power semiconductor devices in medium-voltage (MV) applications has been made possible due to the development of high blocking voltage (10–15 kV)-based devices. While the use of these devices brings in a lot of advantages, the semiconductor devices are exposed to high peak stress (of up to 15 kV) and a very high <inline-formula> <tex-math notation="LaTeX">$dv/dt$ </tex-math></inline-formula> (of up to 100 kV/<inline-formula> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula>). The high <inline-formula> <tex-math notation="LaTeX">$dv/dt$ </tex-math></inline-formula> across the devices leads to a high <inline-formula> <tex-math notation="LaTeX">$dv/dt$ </tex-math></inline-formula> across other components connected to the system. This makes the effect of the parasitic capacitance across the components to be of paramount importance since an additional current flows through the components and, consequently, through the switching device. This additional current flows during each switching transition and leads to increased switching losses in the device. This article analyzes the effect of these additional losses on the lifetime of the device. The thermal performance of a three-phase inverter power block is provided, and a mission profile (solar irradiance and temperature)-based analysis is carried out to account for the additional junction temperature rise. The rainflow counting method is implemented to identify the mean and amplitude of each thermal cycle. An empirical device lifetime model is used to calculate the number of cycles to failure. Finally, the Palgrem Miner rule is used to quantify the total damage in the device. Comparisons have been carried out on basis of lifetime for both the cases (with and without the influence of parasitic capacitances). This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.}, number={1}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish and Weatherford, Todd R.}, year={2020}, month={Mar}, pages={486–494} }
 @inproceedings{agarwal_iyer_anurag_bhattacharya_2019, title={Adaptive Control of a Hybrid Energy Storage System for Wave Energy Conversion Application}, ISBN={9781728103952}, url={http://dx.doi.org/10.1109/ecce.2019.8912897}, DOI={10.1109/ecce.2019.8912897}, abstractNote={A hybrid energy storage system (HESS), that comprises of a battery and a supercapacitor, is utilized to absorb the power and energy oscillations for a wave energy conversion system so as to inject a smooth power to the grid. Continuous variation in the wave profile presents a formidable challenge in terms of the power and energy allocation among the battery and supercapacitor. In this paper, an adaptive control strategy is proposed, wherein the power and energy sharing between the battery and super-capacitor are dynamically decided based on an optimization algorithm. The proposed algorithm is aimed at optimizing the total losses in the hybrid energy storage system while simultaneously maximizing the battery lifetime. Circuit simulation and experimental results from a hardware prototype are provided to validate the effectiveness of the proposed control scheme.}, booktitle={2019 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Agarwal, Apoorv and Iyer, Vishnu Mahadeva and Anurag, Anup and Bhattacharya, Subhashish}, year={2019}, month={Sep}, pages={4994–5001} }
 @inproceedings{anurag_acharya_gohil_bhattacharya_2019, title={Benchmarking and Qualification of Gate Drivers for Medium Voltage (MV) Operation using 10 kV Silicon Carbide (SiC) MOSFETs}, volume={2019-March}, ISBN={9781538683309}, url={http://dx.doi.org/10.1109/apec.2019.8721799}, DOI={10.1109/apec.2019.8721799}, abstractNote={Emergence of reliable medium voltage (MV) silicon carbide (SiC) devices, has made it possible to use these for MV applications, including grid interconnections, and medium voltage drives system. In a converter structure, the isolated power supplies of the gate drivers for these MV devices experience a peak stress up to 15 kV and a very high dv/dt (up to 100 kV/μs). Exposing the gate driver to such harsh conditions leads to various challenges in providing the required insulation, and maintaining the signal fidelity (due to common mode (CM) currents across the parasitic capacitance of the transformer). The failure of gate drivers at a converter level can lead to destructive damage to the converter. This calls for a methodology to design, test and qualify the gate drivers before implementing them in the field for long-term operation. This paper provides a detailed design methodology and analysis to qualify the gate drivers for a long-term operation. The analysis and design-phase ensures reliable operation of the gate driver, and the testing and qualifying phase ensures long-term operation of the gate driver. The experimental test setup has been built and test results have been provided based on a gate driver designed for 10 kV SiC MOSFETs.}, booktitle={2019 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Anurag, Anup and Acharya, Sayan and Gohil, Ghanshyamsinh and Bhattacharya, Subhashish}, year={2019}, month={Mar}, pages={441–447} }
 @article{anurag_acharya_prabowo_gohil_bhattacharya_2019, title={Design Considerations and Development of an Innovative Gate Driver for Medium-Voltage Power Devices With High dv/dt}, volume={34}, ISSN={0885-8993 1941-0107}, url={http://dx.doi.org/10.1109/tpel.2018.2870084}, DOI={10.1109/tpel.2018.2870084}, abstractNote={Medium-voltage (MV) silicon carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon-based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5–10 kV) and a very high <inline-formula><tex-math notation="LaTeX">$dv/dt$</tex-math></inline-formula> (10–100 kV/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>s). Using these devices calls for a gate driver with a dc–dc isolation stage that has ultralow coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. An MV isolation transformer is designed with a low interwinding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short-circuit protection scheme specifically designed for 10 kV SiC <sc>mosfet</sc>s. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for MV SiC devices exhibiting very high <inline-formula><tex-math notation="LaTeX">$dv/dt$</tex-math></inline-formula>. The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices.}, number={6}, journal={IEEE Transactions on Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Prabowo, Yos and Gohil, Ghanshyamsinh and Bhattacharya, Subhashish}, year={2019}, month={Jun}, pages={5256–5267} }
 @inproceedings{acharya_anurag_kolli_bhattacharya_2019, place={New York}, title={Design and Performance Evaluation of 1.2 kV, 325 A SiC-MOSFET High Performance Module based 100 kVA Three-phase Two-level Power Block}, booktitle={10th International Conference on Power Electronics and ECCE Asia}, publisher={IEEE}, author={Acharya, Sayan and Anurag, Anup and Kolli, Nithin and Bhattacharya, Subhashish}, year={2019}, pages={821–828} }
 @inproceedings{kim_acharya_anurag_kim_bhattacharya_2019, title={Effect of Inverter Output dv/dt with Respect to Gate Resistance and Loss Comparison with dv/dt Filters for SiC MOSFET based High Speed Machine Drive Applications}, ISBN={9781728103952}, url={http://dx.doi.org/10.1109/ecce.2019.8912249}, DOI={10.1109/ecce.2019.8912249}, abstractNote={Fast switching characteristic of wide band gap (WBG) devices enables high frequency switching of power devices and thereby, facilitates high fundamental frequency operation of a machine. However, with the switching transition times being in orders of tens of nanoseconds, a high dv/dt is observed across the switching device. The high dv/dt experienced by the switches, and consequently by the machine, can degrade winding insulations or bearings over a period of time. It is therefore imperative to maintain dv/dt below recommended values depending on the machine insulation. The dv/dt across the devices can be adjusted by using higher values of gate resistance. However, this introduces additional switching losses on the device. Using different dv/dt filtering techniques can also help to control the dv/dt on the machine terminals. These techniques do not increase the switching losses on the device. However, the filter circuits introduce losses in the circuit and additional costs. In this paper, an analysis based on the impact of gate resistance on the dv/dt across the machine, and the corresponding losses is carried out. In addition, a comparision is performed on the basis of efficiency between these two techniques. A SiC MOSFET based 3-phase inverter (CREE-CCS020M12CM2) is used for the analysis.}, booktitle={2019 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Kim, Heonyoung and Acharya, Sayan and Anurag, Anup and Kim, Byeong-Heon and Bhattacharya, Subhashish}, year={2019}, month={Sep}, pages={2301–2306} }
 @inproceedings{anurag_acharya_bhattacharya_2019, title={Evaluation of Extra High Voltage (XHV) Power Module for Gen3 10 kV SiC MOSFETs in a Mobile Utility Support Equipment based Solid State Transformer (MUSE-SST)}, booktitle={10th International Conference on Power Electronics and ECCE Asia}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish}, year={2019}, pages={1–7} }
 @article{anurag_acharya_bhattacharya_2019, title={Gate Drivers for High-Frequency Application of Silicon-Carbide MOSFETs}, volume={6}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2019.2925238}, DOI={10.1109/MPEL.2019.2925238}, abstractNote={With the advent of wide-bandgap (WBG) semiconductor devices, silicon-carbide (SiC)-based MOSFETs for high voltage and current serve as a viable replacement for conventional Si-based IGBTs [1], [2]. SiC-based MOSFETs combine the advantages of both IGBTs and MOSFETs, have a low on-state resistance at a high-voltage rating (similar to IGBTs), and lower-switching losses than those of Si MOSFETs, thus making it closer to an ideal switch [3]. This makes it possible for SiC MOSFETs to process high power at high-switching frequencies without compromising the efficiency of the system [4]. Due to the inherent lower on-state specific resistance and faster switching speeds in SiC MOSFETs, it is also possible to develop and use medium-voltage (MV) power semiconductor devices greater than 6.5 kV without experiencing very high losses [5]. The SiC MOSFET design and development can be divided into two broad categories: low-voltage (LV)-blocking (<3.3-kV) and MV-blocking (>3.3-kV) SiC MOSFETs [6]. Although MV SiC MOSFETs can enable niche applications, there is widespread use of LV-blocking power devices in various applications such as renewable energy, drives for electrical machines, power converters for electric vehicles, and so on, whereas SiC MOSFETs can offer a multitude of advantages over Si IGBTs [7], [8].}, number={3}, journal={IEEE POWER ELECTRONICS MAGAZINE}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Acharya, Sayan and Bhattacharya, Subhashish}, year={2019}, month={Sep}, pages={18–31} }
 @inproceedings{anurag_acharya_pal_bhattacharya_2019, title={Mission Profile based Reliability Analysis of a Three-Phase PV Inverter Considering the Influence of High dv/dt on Parasitic Filter Elements}, volume={2019-March}, ISBN={9781538683309}, url={http://dx.doi.org/10.1109/apec.2019.8721983}, DOI={10.1109/apec.2019.8721983}, abstractNote={Silicon Carbide (SiC) power semiconductor devices in medium voltage (MV) applications have facilitated the use of power converters at distribution voltage level. In these applications, the semiconductor devices are exposed to a high peak stress (of up to 15 kV) and a very high dv/dt (of up to 100 kV/µs). The increasing use of these power devices has made the effects of the parasitic elements in the filter more prominent, due to the high dv/dt experienced by the passive filter elements during device switching transients. The parasitic elements in the filter inductors causes an increased switching loss in the devices. This paper analyses the effect of these additional losses on the lifetime of the device. A thermal analysis based on a mission profile (solar irradiance and temperature) is provided to account for the additional junction temperature rise due to the high dv/dt and the parasitic filter elements. Rainflow counting method has been used to identify the mean and amplitude of each thermal cycle. An analytical device model and Palgrem Miner rule is used to quantify the damage in the device. Comparisons have been carried out on basis of lifetime, for cases with and without the influence of parasitic capacitances. This analysis can be helpful in validating the importance of the design of filter inductors in these MV applications.}, booktitle={2019 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Anurag, Anup and Acharya, Sayan and Pal, Shruti and Bhattacharya, Subhashish}, year={2019}, month={Mar}, pages={3490–3496} }
 @inproceedings{acharya_anurag_bhattacharya_2019, title={Stability Analysis of a Medium Voltage Cascaded Converter System with Reduced DC-link Capacitance}, volume={2019-March}, ISBN={9781538683309}, url={http://dx.doi.org/10.1109/apec.2019.8722010}, DOI={10.1109/apec.2019.8722010}, abstractNote={Recent development of Silicon Carbide (SiC) based Medium Voltage (MV) power semiconductor devices have paved ways to build high power MV power converters with simple two level structures. One of the critical applications of these converters are solid state transformers (SSTs) which interconnects MV grid to a low voltage (LV) grid with high frequency isolation. SSTs are usually built with multi-stage cascaded conversion structures which includes ac-dc, dc-dc, and dc-ac stages, respectively. These converter structures need an intermediate MV DC bus to function. For MV applications, the DC bus structure is designed with low inductance bus bar and MV capacitors. At medium voltage levels, it is difficult to manufacture capacitors with high capacitance values with low footprint. Therefore, MV polypropylene film capacitors with low equivalent series inductance (ESL) are often utilized to build the MV DC Bus to meet the power density requirements. The small values of the effective DC bus capacitance create stability issues for cascaded converter structures for SSTs as it becomes difficult to completely decouple different power conversion stages. This paper delves into the interaction between different power conversion stages of a MV SST while transferring power. The study shows that low capacitance value of the MV DC bus can cause instability which needs to be mitigated.}, booktitle={2019 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Acharya, Sayan and Anurag, Anup and Bhattacharya, Subhashish}, year={2019}, month={Mar}, pages={1157–1164} }
 @inproceedings{anurag_acharya_gohil_bhattacharya_2018, title={A Gate Driver Design for Medium Voltage Silicon Carbide Power Devices with High dv / dt}, ISBN={9781509066841}, url={http://dx.doi.org/10.1109/iecon.2018.8591858}, DOI={10.1109/iecon.2018.8591858}, abstractNote={The use of silicon carbide (SiC) devices in medium voltage (MV) applications has become a possibility due to the development of reliable MV SiC power devices. However, when SiC devices are used in these MV applications, they are exposed to a high voltage peak stress (of up to 15 kV across the primary and secondary side of the gate driver) and a very high $dv/dt$ (of up to 100 kV/μs across the isolation transformer). The gate driver design is very critical for proper functioning of the MV devices under the presence of such high dv/dt. This paper presents a design of an improved gate driver power isolation method, with a low coupling capacitance between the primary and the secondary side. The footprint of the isolation transformer is minimized to meet the clearance and insulation requirements. Comparisons have been drawn with an existing gate driver topology, on the basis of size of the gate driver, and common mode performances for different $dv/dt$. Experimental results are provided to validate both the gate driver designs. The testing and analysis is carried out on a 10 kV SiC MOSFET developed and packaged by Wolfspeed. In addition, a brief discussion on the insulation standards for these kinds of applications is provided. The gate driver concept is aimed at providing a benchmark for building an efficient and reliable method to drive MV SiC devices.}, booktitle={IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society}, publisher={IEEE}, author={Anurag, Anup and Acharya, Sayan and Gohil, Ghanshyamsinh and Bhattacharya, Subhashish}, year={2018}, month={Oct}, pages={877–882} }
 @inproceedings{anurag_acharya_prabowo_gohil_kassa_bhattacharya_2018, title={An accurate calorimetric method for measurement of switching losses in silicon carbide (SiC) MOSFETs}, volume={2018-March}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85046966591&partnerID=MN8TOARS}, DOI={10.1109/apec.2018.8341245}, abstractNote={An accurate measurement of switching losses in SiC MOSFETs is necessary in order to design and evaluate the thermal performance of modern converter systems. Conventionally, electrical measurement methods, such as the double-pulse test (DPT) are used for calculating the hard-switching losses. However, with the advent of wide-bandgap devices, which have fast switching transients, it is rather difficult to capture the waveforms accurately during switching transitions, and consequently the measurement of switch loss suffers. This paper presents an accurate calorimetric method for measuring the switching losses. The conventional calorimetric measurement methods can accurately measure the device losses. However, the segregation of the conduction, turn-on and turn-off loss is not possible. This paper addresses this issue and proposes a method that can be used to determine individual loss components. The calorimetric test setup is described and a novel modulation scheme is introduced which enables the separation of turn-on and turn-off switching losses. The experimental test setup has been built and the method has been verified by measuring the losses of a Wolfspeed CMF10120D device.}, booktitle={Thirty-third annual ieee applied power electronics conference and exposition (apec 2018)}, author={Anurag, Anup and Acharya, Sayan and Prabowo, Y. and Gohil, G. and Kassa, H. and Bhattacharya, S.}, year={2018}, pages={1695–1700} }
 @inproceedings{anurag_acharya_prabowo_jakka_bhattacharya_2018, title={Design of a Medium Voltage Mobile Utilities Support Equipment based Solid State Transformer (MUSE-SST) with 10 kV SiC MOSFETs for Grid Interconnection}, ISBN={9781538667057}, url={http://dx.doi.org/10.1109/pedg.2018.8447766}, DOI={10.1109/pedg.2018.8447766}, abstractNote={A conventional transformer can withstand multiple electrical, mechanical and thermal faults which enables it to have a long lifetime. However, its inability to control the power flow through it has led researchers to look for alternate options such as the solid-state transformers. With the Silicon Carbide (SiC) semiconductor devices, it is now possible to go to high switching frequencies in medium voltage applications, which helps in reducing the overall size and weight of the transformer. The advent of medium voltage (MV) SiC devices has enabled the use of simple two-level and three-level topologies for medium voltage power transfer. This paper discusses a basic power topology for a medium voltage mobile utilities support equipment based solid state transformer (MUSE-SST) with the new 10 kV SiC MOS-FETs. A design of the MUSE-SST is presented followed by some of the practical considerations that needs to be taken, including gate driver design and heat sink configurations. Simulation results for a 100 kW, MV MUSE SST system is presented. Experimental results are provided validating the operation of these 10 kV devices in double pulse tests, buck and boost operation. This research helps in providing an overview regarding the usage of the 10 kV SiC devices in grid-interconnection and also discusses various challenges that comes along with it.}, booktitle={2018 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG)}, publisher={IEEE}, author={Anurag, Anup and Acharya, Sayan and Prabowo, Yos and Jakka, Venkat and Bhattacharya, Subhashish}, year={2018}, month={Jun} }
 @inproceedings{acharya_chattopadhyay_anurag_rengarajan_prabowo_bhattacharya_2018, title={High Power Medium Voltage 10 kV SiC MOSFET Based Bidirectional Isolated Modular DC–DC Converter}, ISBN={9784886864055}, url={http://dx.doi.org/10.23919/ipec.2018.8507406}, DOI={10.23919/ipec.2018.8507406}, abstractNote={Recent advancement in the packaging technology for the SiC MOSFETs with blocking voltage of 10 kV or higher have opened up opportunities to consider these devices for medium voltage and high power applications. This paper focuses on the design of a modular medium voltage, high power DC– DC converter enabled by 10 kV SiC MOSFETs which aims at increasing the efficiency, power density and inter-operability. The proposed DC–DC converter is suitable for applications like DC distribution for the data centres, sub-sea power transmission, offshore wind farms and photovolatic energy transmission -distribution - coordination, electric ship DC power transmission and distribution solid state transformer.}, booktitle={2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia)}, publisher={IEEE}, author={Acharya, Sayan and Chattopadhyay, Ritwik and Anurag, Anup and Rengarajan, Satish and Prabowo, Yos and Bhattacharya, Subhashish}, year={2018}, month={May}, pages={3564–3571} }
 @article{anurag_deshmukh_maguluri_anand_2018, title={Integrated DC–DC Converter Based Grid-Connected Transformerless Photovoltaic Inverter With Extended Input Voltage Range}, volume={33}, ISSN={0885-8993 1941-0107}, url={http://dx.doi.org/10.1109/tpel.2017.2779144}, DOI={10.1109/TPEL.2017.2779144}, abstractNote={Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims.}, number={10}, journal={IEEE Transactions on Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Deshmukh, Nachiketa and Maguluri, Avinash and Anand, Sandeep}, year={2018}, month={Oct}, pages={8322–8330} }
 @inproceedings{acharya_anurag_gohil_hazra_bhattacharya_2018, title={Mission Profile based Reliability Analysis of a Medium Voltage Power Conversion Architecture for PMSG based Wind Energy Conversion System}, ISBN={9781538645369}, url={http://dx.doi.org/10.1109/ias.2018.8544579}, DOI={10.1109/ias.2018.8544579}, abstractNote={The development of wide-bandgap (WBG) power semiconductor devices has opened up new areas of applications which were previously dominated by silicon based IGBTs. This paper presents one such application where a multi-megawatt permanent magnet synchronous generator based wind energy conversion system (PMSG-WECS) is used for medium voltage (MV) grid integration. The conversion of the low output voltage of the PMSG to medium voltage brings about a multitude of advantages including reduction in the cable diameter and consequently the cost and weight of the system. WBG devices enable the use of high frequency transformers which makes it possible to install the system on the tower of the wind turbine. With these kinds of installations, it becomes necessary to investigate the reliability of the system, since maintenance of the systems leads to additional incurred costs. This paper provides a mission-profile (i.e. wind speed and ambient temperature) based analysis, in order to determine the temperature rise in the devices and consequently, its effects on the lifetime of the devices. An analytical lifetime model has been used and the damage produced on the transistors has been quantified using Palgrem Miner rule. This analysis can be helpful in understanding the impacts of having a tower-top converter system on the overall cost.}, booktitle={2018 IEEE Industry Applications Society Annual Meeting (IAS)}, publisher={IEEE}, author={Acharya, Sayan and Anurag, Anup and Gohil, Ghanshyamsinh and Hazra, Samir and Bhattacharya, Subhashish}, year={2018}, month={Sep} }
 @inproceedings{anurag_acharya_prabowo_jakka_bhattacharya_2018, title={Mobile Utility Support Equipment based Solid State Transformer (MUSE-SST) for MV Grid Interconnection with Gen3 10 kV SiC MOSFETs}, ISBN={9781479973125}, url={http://dx.doi.org/10.1109/ecce.2018.8557388}, DOI={10.1109/ecce.2018.8557388}, abstractNote={With the increasing maturity of Silicon Carbide (SiC) semiconductor devices at medium voltage (MV) level, high switching frequencies and low conduction losses in MV applications is possible. Higher switching frequency operation enables the reduction in size and weight of transformers. In an application such as MV-MV or MV-LV grid-interconnection, a solid state transformer offers a multitude of advantages compared to conventional transformers. A reduction in size and weight, in addition to having active and reactive power flow control have made SSTs a lucrative replacement to conventional low frequency (LF) transformers. Lower conduction losses exhibited by SiC devices (as compared to their silicon counterparts) have made it possible to achieve similar efficiencies as compared to conventional LF transformers. This paper aims at providing an overview of a MV MUSE-SST topology. A brief idea on control and monitoring is also provided. Practical design considerations that are required to build a MV system is provided to aid researchers in designing converters for MV applications. The protection aspects of the MV MUSE-SST system is also highlighted. Basic experimental results for the gate driver is also shown. Initial testing results with the Gen3 10 kV SiC MOSFETs and the challenges associated with it are also discussed. This research aims at being a building block for implementation and testing of the medium voltage converter systems.}, booktitle={2018 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Anurag, Anup and Acharya, Sayan and Prabowo, Yos and Jakka, Venkat and Bhattacharya, Subhashish}, year={2018}, month={Sep}, pages={450–457} }
 @inproceedings{acharya_anurag_prabowo_bhattacharya_2018, title={Practical Design Considerations for MV LCL Filter Under High dv/dt Conditions Considering the Effects of Parasitic Elements}, ISBN={9781538667057}, url={http://dx.doi.org/10.1109/pedg.2018.8447701}, DOI={10.1109/pedg.2018.8447701}, abstractNote={For high power medium voltage (MV) grid connected applications LCL filter proves to be an attractive solution to filter out the current harmonics when compared to $L$ or LC filters. The inductance requirement reduces drastically to meet the same Total Harmonic Distortion (THD) standards for grid connections for LC L filters compared to $L$ filter which makes the system dynamics much faster. The increasing use of Silicon Carbide (SiC) based power devices for MV applications has made the effects of the parasitic elements in the filter more prominent, due to the high dv / dt experienced by the passive filter elements during device switching transients. This paper addresses the issues associated with the high dv / dt experienced by the LC L filters for SiC-based MV applications. In order to study these effects, the parasitic elements of the inductor are modeled and analyzed. A suitable solution is proposed to improve the overall system performance. The effect of high dv / dt on the filter and the effectiveness of the proposed solution are validated using simulation. Experimental data is also provided to validate the proposed concept.}, booktitle={2018 9th IEEE International Symposium on Power Electronics for Distributed Generation Systems (PEDG)}, publisher={IEEE}, author={Acharya, Sayan and Anurag, Anup and Prabowo, Yos and Bhattacharya, Subhashish}, year={2018}, month={Jun} }
 @inproceedings{jakka_acharya_anurag_prabowo_kumar_parashar_bhattacharya_2018, title={Protection Design Considerations of a 10 kV SiC MOSFET Enabled Mobile Utilities Support Equipment Based Solid State Transformer (MUSE-SST)}, ISBN={9781509066841}, url={http://dx.doi.org/10.1109/iecon.2018.8592886}, DOI={10.1109/iecon.2018.8592886}, abstractNote={Solid state transformers (SSTs) are evolved as an emerging technology which offer several key features in integrating different grids, storage devices, and renewable energy sources, etc. In this paper, a 10 kV SiC MOSFET enabled Mobile Utility Support Equipment based SST (MUSE-SST) is presented for integrating a medium voltage (MV) AC grid (4.16 kV L-L, 60 Hz) and a low voltage (LV) AC grid (480 V L-L, 60 Hz). The MUSE-SST consist of three power conversion stages: MV side active front end converter (AFEC: MV), dual active bridge (DAB), and LV side active front end converter (AFEC: LV). In order to protect MUSE-SST from various abnormal operating conditions, different protection schemes are discussed. Dedicated gate drivers incorporating device short-circuit protection are implemented for both the MV and the LV SiC MOSFETs. It is observed that the MV short circuit faults are found to be severe and resulting in very high inrush currents from the MV grid which can lead to the impairment of entire SST system. A bi-directional switch in parallel with a high impedance resistor (BSPHR) circuit based protection scheme is presented to limit the grid currents during MV dc-link short circuit conditions. The BSPHR scheme and efficacy of gate drivers are validated through simulations and experimental results, respectively. The avalanche ruggedness of 10kV, SiC MOSFETs is established experimentally using a single shot unclamped inductive switching (UIS) test and the critical avalanche energy for the MOSFET failure is obtained.}, booktitle={IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society}, publisher={IEEE}, author={Jakka, Venkat N. and Acharya, Sayan and Anurag, Anup and Prabowo, Yos and Kumar, Ashish and Parashar, Sanket and Bhattacharya, Subhashish}, year={2018}, month={Oct}, pages={5559–5565} }
 @article{anurag_gohil_acharya_han_vechalapu_baliga_bhattacharya_van brunt_sabri_hull_et al._2018, title={Static and Dynamic Characterization of a 3.3 Kv, 45 A 4H-Sic MOSFET}, volume={924}, ISSN={1662-9752}, url={http://dx.doi.org/10.4028/www.scientific.net/msf.924.739}, DOI={10.4028/www.scientific.net/msf.924.739}, abstractNote={Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.}, journal={Materials Science Forum}, publisher={Trans Tech Publications, Ltd.}, author={Anurag, Anup and Gohil, Ghanshyamsinh and Acharya, Sayan and Han, Ki Jeong and Vechalapu, Kasunaidu and Baliga, B. Jayant and Bhattacharya, Subhashish and van Brunt, Edward and Sabri, Shadi and Hull, Brett and et al.}, year={2018}, month={Jun}, pages={739–742} }
 @article{singh_anurag_anand_2017, title={Evaluation of V-ce at Inflection Point for Monitoring Bond Wire Degradation in Discrete Packaged IGBTs}, volume={32}, ISSN={["1941-0107"]}, DOI={10.1109/tpel.2016.2621757}, abstractNote={A novel scheme is proposed for online condition monitoring of bond wires present in insulated gate bipolar transistor (IGBT) package. The proposed method detects bond wire degradation using on-state collector emitter voltage at the inflection point. Previously reported condition monitoring methods based on on-state collector-emitter voltage as a precursor of aging require an accurate knowledge of junction temperature which is difficult to measure online during an inverter operation. The key advantage of the proposed scheme is that it monitors the bond wire degradation irrespective of the junction temperature. Therefore, this technique is not affected by increase in junction temperature due to die attach degradation or change in ambient temperature. The proposed scheme is verified experimentally under realistic operating conditions.}, number={4}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Singh, Arun and Anurag, Anup and Anand, Sandeep}, year={2017}, month={Apr}, pages={2481–2484} }
 @article{anurag_bal_sourav_nanda_2016, title={A review of maximum power-point tracking techniques for photovoltaic systems}, volume={35}, ISSN={1478-6451 1478-646X}, url={http://dx.doi.org/10.1080/14786451.2014.918979}, DOI={10.1080/14786451.2014.918979}, abstractNote={This paper provides a detailed review of the maximum power-point tracking (MPPT) techniques used in photovoltaic (PV) systems. The MPPT technique proves to be an essential part of the PV system, and hence the most appropriate method should be chosen in order to optimise the efficiency of the system, keeping in consideration the economic point of view. A small description of various MPPT techniques has been provided and comparison based on features, such as convergence speed, implementation complexity, accuracy, the relative cost of implementing the set-up and their commercial availability has been done. This paper aims at choosing the most appropriate technique for any particular PV application taking into account all the above-mentioned factors, especially the cost, complexity and accuracy, so as to maximise the effectiveness of the system by optimising all the parameters. It aims to serve as a useful guide for both users and manufacturers.}, number={5}, journal={International Journal of Sustainable Energy}, publisher={Informa UK Limited}, author={Anurag, Anup and Bal, Satarupa and Sourav, Suman and Nanda, Mrutyunjaya}, year={2016}, month={May}, pages={478–501} }
 @inproceedings{nune_anurag_anand_chauhan_2016, title={Comparative analysis of power density in Si MOSFET and GaN HEMT based flyback converters}, ISBN={9781467372930}, url={http://dx.doi.org/10.1109/cpe.2016.7544212}, DOI={10.1109/cpe.2016.7544212}, abstractNote={Gallium Nitride (GaN) based power devices have the potential to achieve higher efficiency and higher switching frequency than those possible with Silicon (Si) power devices. In literature, GaN based converters are claimed to offer higher power density. However, a detailed comparative analysis on the power density of GaN and Si based low power dc-dc flyback converter is not reported. In this paper, comparison of a 100 W, dc-dc flyback converter based on GaN and Si is presented. Both the converters are designed to ensure an efficiency of 80%. Based on this, the switching frequency for both the converters are determined. The analysis shows that the GaN based converter can be operated at approximately ten times the switching frequency of Si-based converter. This leads to a reduction in the area product of the flyback transformer required in GaN based converter. It is found that the volume of the flyback transformer can be reduced by a factor of six for a GaN based converter as compared to a Si based converter. Further, it is observed that the value of output capacitance used in the GaN based converter reduces by a factor of ten as compared to the Si based converter, implying a reduction in the size of the output capacitors. Therefore, a significant improvement in the power density of the GaN based converter as compared to the Si based converter is seen.}, booktitle={2016 10th International Conference on Compatibility, Power Electronics and Power Engineering (CPE-POWERENG)}, publisher={IEEE}, author={Nune, Rajender and Anurag, Anup and Anand, Sandeep and Chauhan, Yogesh Singh}, year={2016}, month={Jun} }
 @article{bal_anurag_nanda_sourav_2015, title={Comprehensive Analysis and Experimental Validation of an Improved Mathematical Modeling of Photovoltaic Array}, volume={2015}, ISSN={2090-181X 2090-1828}, url={http://dx.doi.org/10.1155/2015/654092}, DOI={10.1155/2015/654092}, abstractNote={This paper proposes a simple, accurate, and easy to model approach for the simulation of photovoltaic (PV) array and also provides a comparative analysis of the same with two other widely used models. It is highly imperative that the maximum power point (MPP) is achieved effectively and thus a simple and robust mathematical model is necessary that poses less mathematical complexity as well as low data storage requirement, in which the maximum power point tracking (MPPT) algorithm can be realized in an effective way. Further, the resemblance of the P-V and I-V curves as obtained on the basis of experimental data should also be taken into account for theoretical validation. In addition, the study incorporates the root mean square deviation (RMSD) from the experimental data, the fill factor (FF), the efficiency of the model, and the time required for simulation. Two models have been used to investigate the I-V and P-V characteristics. Perturb and Observe method has been adopted for MPPT. The MPP tracking is realized using field programmable gate array (FPGA) to prove the effectiveness of the proposed approach. 
All the systems are modeled and simulated in MATLAB/Simulink environment.}, journal={Advances in Power Electronics}, publisher={Hindawi Limited}, author={Bal, Satarupa and Anurag, Anup and Nanda, Mrutyunjaya and Sourav, Suman}, year={2015}, pages={1–11} }
 @inproceedings{anurag_yang_blaabjerg_2015, title={Impact of reactive power injection outside feed-in hours on the reliability of photovoltaic inverters}, ISBN={9781479985869}, url={http://dx.doi.org/10.1109/pedg.2015.7223032}, DOI={10.1109/pedg.2015.7223032}, abstractNote={Current energy paradigm of mixed renewables seems to urgently require reactive power provision at various feed-in points of the utility grid. Photovoltaic (PV) inverters are able to provide reactive power in a decentralized manner at the grid-connection point even outside active power feed-in operation, especially at night. This serves as a motivation for utilizing the PV inverters at night for reactive power compensation. Thus, a detailed analysis on the impact of reactive power injection by PV inverters outside feed-in operation on the thermal performance and also the reliability is performed in this paper. A thermal analysis based on the mission profile (i.e. solar irradiance and ambient temperature) has been incorporated, so as to determine the additional temperature rise in the components (IGBTs and diodes) outside feed-in operation for different values of reactive power injection. Consequently, the analysis enables the translation from long-term mission profiles to device thermal loading, considering the operation at night. An analytical lifetime model is then used for lifetime quantization based on the Palgrem Miner rule. Thereafter, considering the lifetime reduction of the PV inverter for different values of reactive power injection an assessment of the economic impacts is made. This analysis can be useful in choosing between conventional reactive power devices or PV inverters for injecting reactive power to the grid.}, booktitle={2015 IEEE 6th International Symposium on Power Electronics for Distributed Generation Systems (PEDG)}, publisher={IEEE}, author={Anurag, Anup and Yang, Yongheng and Blaabjerg, Frede}, year={2015}, month={Jun} }
 @inproceedings{anurag_yang_blaabjerg_2015, title={Reliability analysis of single-phase PV inverters with reactive power injection at night considering mission profiles}, ISBN={9781467371513}, url={http://dx.doi.org/10.1109/ecce.2015.7309961}, DOI={10.1109/ecce.2015.7309961}, abstractNote={The widespread adoption of mixed renewables urgently require reactive power exchange at various feed-in points of the utility grid. Photovoltaic (PV) inverters are able to provide reactive power in a decentralized manner at the grid-connection points even outside active power feed-in operation, especially at night when there is no solar irradiance. This serves as a motivation for utilizing the PV inverters at night for reactive power compensation. Thus, an analysis on the impact of reactive power injection by PV inverters outside feed-in operation on the thermal performance and the reliability has been performed in this paper. A thermal analysis is incorporated to determine the additional temperature rise in the power switching components outside the feed-in operation. This analysis enables the translation from long-term mission profiles (three different mission profiles) to device thermal loading, considering the operation outside active feed-in hours. An analytical lifetime model is then employed for lifetime quantization based on the Palgrem Miner rule. Thereafter, considering the lifetime reduction of the PV inverter under different mission profiles with reactive power injection at night, the impact of PV sites on the economic value of the inverter is assessed. This analysis can be useful in choosing between conventional reactive power compensation devices or PV inverters for injecting reactive power to the grid.}, booktitle={2015 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Anurag, Anup and Yang, Yongheng and Blaabjerg, Frede}, year={2015}, month={Sep} }
 @article{anurag_yang_blaabjerg_2015, title={Thermal Performance and Reliability Analysis of Single-Phase PV Inverters With Reactive Power Injection Outside Feed-In Operating Hours}, volume={3}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/jestpe.2015.2428432}, DOI={10.1109/jestpe.2015.2428432}, abstractNote={Reactive power support by photovoltaic (PV) systems is of increasing interest, when compared with the conventional reactive power compensation devices. The PV inverters can exchange reactive power with the utility grid in a decentralized manner even outside feed-in operation, especially at night when there is no solar irradiance. However, reactive power injection causes additional power losses in the switching components leading to a temperature rise in the devices. Thus, this paper analyzes the impact of reactive power injection by PV inverters outside feed-in operation on the thermal performance of their power switching components. A thermal analysis based on the mission profile (i.e., solar irradiance and ambient temperature) has been incorporated, so as to determine the additional temperature rise in the components induced by the operation outside feed-in hours. An analytical lifetime model has been used. The damage produced on the transistors has been quantified using the Palmgren-Miner rule. A reliability analysis has been carried out on a PV inverter with and without the injection of reactive power into the utility grid at night. Economic impacts of injecting reactive power from PV inverters outside feed-in operating hours have been analyzed thereafter. This analysis can be helpful to make a better choice while choosing between conventional reactive power devices or PV inverters for injecting reactive power to the grid.}, number={4}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Anurag, Anup and Yang, Yongheng and Blaabjerg, Frede}, year={2015}, month={Dec}, pages={870–880} }
 @inproceedings{amoiridis_anurag_ghimire_munk-nielsen_baker_2015, title={Vce-based chip temperature estimation methods for high power IGBT modules during power cycling — A comparison}, ISBN={9789075815221}, url={http://dx.doi.org/10.1109/epe.2015.7309449}, DOI={10.1109/epe.2015.7309449}, abstractNote={Temperature estimation is of great importance for performance and reliability of IGBT power modules in converter operation as well as in active power cycling tests. It is common to be estimated through Thermo-Sensitive Electrical Parameters such as the forward voltage drop (Vce) of the chip. This experimental work evaluates the validity and accuracy of two Vce based methods applied on high power IGBT modules during power cycling tests. The first method estimates the chip temperature when low sense current is applied and the second method when normal load current is present. Finally, a correction factor that eliminates the series resistance contribution on the Vce measured at high current, is proposed.}, booktitle={2015 17th European Conference on Power Electronics and Applications (EPE'15 ECCE-Europe)}, publisher={IEEE}, author={Amoiridis, Anastasios and Anurag, Anup and Ghimire, Pramod and Munk-Nielsen, Stig and Baker, Nick}, year={2015}, month={Sep} }
 @article{anurag_bal_sourav_2014, title={A Comparative Study of Mathematical Modeling of Photovoltaic Array}, volume={15}, ISSN={2194-5756 1553-779X}, url={http://dx.doi.org/10.1515/ijeeps-2013-0115}, DOI={10.1515/ijeeps-2013-0115}, abstractNote={Abstract}, number={4}, journal={International Journal of Emerging Electric Power Systems}, publisher={Walter de Gruyter GmbH}, author={Anurag, Anup and Bal, Satarupa and Sourav, Suman}, year={2014}, month={Aug}, pages={313–326} }
 @inproceedings{patri_nayak_anurag_2014, title={High Accuracy Back-Retreat Diffusion-Fuzzy Clustering of Breast Cancer Data for the Detection of Malignancy}, ISBN={9780889869714 9780889869684}, url={http://dx.doi.org/10.2316/p.2014.818-018}, DOI={10.2316/p.2014.818-018}, abstractNote={A novel fuzzy clustering method has been proposed here for separating the breast cancer data, which operates with reasonable accuracy, allows flexibility in dataset and is modestly time consuming. This method can be applied to any type of cancer data set with some initial labels to obtain high accuracy result in the classification of unlabeled samples. Further, the curse of dimensionality is not an issue for the proposed scheme as it can be applied to data having any number of dimensions or attributes. The DifFUZZY unsupervised clustering algorithm is applied at the initial stage, giving an accuracy of 96.28% over Wisconsin Breast Cancer Dataset (WBCD); the result is further improved to 98.14% by using the proposed Back-Retreat algorithm. The formed clusters are estimated using three internal cluster validation indices and the performance of the method is evaluated using receiver operating characteristic (ROC) curves. The clustering algorithm is compared with Fuzzy C-Means (FCM) algorithm and the results are compared with different classifiers and clustering techniques.}, booktitle={Biomedical Engineering / 817: Robotics Applications}, publisher={ACTAPRESS}, author={Patri, Ashutosh and Nayak, Abhijit and Anurag, Anup}, year={2014} }
 @article{babu_anurag_sowmya_marandi_bal_2013, title={Decoupled Control Strategy of Grid Interactive Inverter System with Optimal LCL Filter Design}, volume={14}, ISSN={2194-5756 1553-779X}, url={http://dx.doi.org/10.1515/ijeeps-2013-0015}, DOI={10.1515/ijeeps-2013-0015}, abstractNote={Abstract}, number={5}, journal={International Journal of Emerging Electric Power Systems}, publisher={Walter de Gruyter GmbH}, author={Babu, B. Chitti and Anurag, Anup and Sowmya, Tontepu and Marandi, Debati and Bal, Satarupa}, year={2013}, month={Sep}, pages={477–486} }
 @phdthesis{anurag_2013, place={Rourkela, India}, title={Decoupled control strategy of grid interactive inverter system with optimal LCL filter design}, school={National Institute of Technology}, author={Anurag, Anup}, year={2013} }
 @article{bal_anurag_babu_2013, title={Design and Analysis of Improved Soft Switching DC–DC Boost Converter for Low Power Photovoltaic Applications}, volume={9}, ISSN={1546-1998}, url={http://dx.doi.org/10.1166/jolpe.2013.1267}, DOI={10.1166/jolpe.2013.1267}, number={3}, journal={Journal of Low Power Electronics}, publisher={American Scientific Publishers}, author={Bal, Satarupa and Anurag, Anup and Babu, B. Chitti}, year={2013}, month={Oct}, pages={303–312} }
 @inproceedings{anurag_bal_chitti babu_2012, title={A detailed comparative analysis between two soft switching techniques used in PV applications}, ISBN={9781467322720 9781467322706 9781467322713}, url={http://dx.doi.org/10.1109/indcon.2012.6420807}, DOI={10.1109/indcon.2012.6420807}, abstractNote={This paper presents a detailed comparative study between two different soft switching techniques used in PV applications. An extended range ZVS active clamped current fed full-bridge isolated boost converter has been studied and the comparison has been done with a soft switching boost converter using an auxiliary resonant circuit. The former uses the energy stored in the leakage inductance of the transformer and its magnetizing inductance to perform the soft switching whereas the latter uses a resonant circuit in order to carry out the same. A typical 500 W converter is employed to investigate both the converters. Comparisons have been made on the basis of operating modes and range of operation. Detailed operation, analysis and simulation results for the designs have been presented. The systems are modeled and simulated in PSIM 64 bit version 9.0 Environment.}, booktitle={2012 Annual IEEE India Conference (INDICON)}, publisher={IEEE}, author={Anurag, Anup and Bal, Satarupa and Chitti Babu, B.}, year={2012}, month={Dec} }
 @inproceedings{bal_anurag_babu_2012, title={An Improved Soft Switching DC-DC Converter for Low Power PV Applications}, ISBN={9781467347044 9780769549026}, url={http://dx.doi.org/10.1109/ised.2012.34}, DOI={10.1109/ised.2012.34}, abstractNote={This paper presents the analysis of a soft switching boost converter for PV applications. The designed converter maintains Zero Voltage Switching (ZVS) turn on and turn off of the main switch and Zero Current Switching (ZCS) turn on and ZVS turn off of the auxiliary switch. Detailed operation, analysis and simulation results for the design have been presented. Switching and conduction losses across the switches and the diodes have also been calculated and analyzed. Some light has been thrown on the design of inductor for the practical implementation of the same. The Perturbation and Observation (P &O) method has been used in order to track the Maximum Power Point (MPP) from the PV panel. This soft switching technique can be used in telecom services where there is a necessity of high voltage with low DC power. The systems are modeled and simulated in PSIM 64 bit version 9.0 environment.}, booktitle={2012 International Symposium on Electronic System Design (ISED)}, publisher={IEEE}, author={Bal, Satarupa and Anurag, Anup and Babu, B. Chitti}, year={2012}, month={Dec} }
 @inproceedings{bal_anurag_babu_2012, title={Comparative analysis of mathematical modeling of Photo-Voltaic (PV) array}, ISBN={9781467322720 9781467322706 9781467322713}, url={http://dx.doi.org/10.1109/indcon.2012.6420627}, DOI={10.1109/indcon.2012.6420627}, abstractNote={This paper presents a comparative study between various models of Photo-Voltaic (PV) array which have been formulated exclusively using the data sheet parameters. The models used for comparative study in this paper includes single diode model, the two diode model, the simplified single diode model and the improved single diode model. PV systems are generally integrated with specific control algorithms in order to extract the maximum possible power. Hence it is highly imperative that the Maximum Power Point (MPP) is achieved effectively and thus we need to design a model from which the MPPT algorithm can be realized in an efficient way. Also other parameters should be taken into account for finding the best model for the use in simulator. In this paper, comparisons have been made on basis of the MPP tracking, the RMSD from the experimental data. Further, the resemblance of the P-V and I-V curves as obtained on the basis of experimental data has also been included in this study. On the basis of all these, the best model that can be used for simulation purposes has been selected. It is envisaged that the work can be very useful for professionals who require simple and accurate PV simulators for their design. All the systems here are modeled and simulated in MATLAB/Simulink environment.}, booktitle={2012 Annual IEEE India Conference (INDICON)}, publisher={IEEE}, author={Bal, Satarupa and Anurag, Anup and Babu, B. Chitti}, year={2012}, month={Dec} }
 @inproceedings{anurag_babu_2012, title={Control of Grid Connected Inverter system for sinusoidal current injection with improved performance}, ISBN={9781467304559 9781467304566 9781467304542}, url={http://dx.doi.org/10.1109/sces.2012.6199022}, DOI={10.1109/sces.2012.6199022}, abstractNote={This paper presents a control strategy for a three-phase Grid Connected Inverter (GCI) under abnormal conditions of the grid like voltage sag, line to ground fault and presence of harmonics. This technique intends to overcome the hitches faced by the conventional controller working under abnormal conditions of the grid. The control strategy adopted here counterbalances the distortions in grid voltage by injecting sinusoidal current into the grid. In addition to this, active and reactive power control during the step changes of the load has also been studied. In order to study the dynamic performance of the system, the models are simulated and the results are analyzed. Simulation results exhibits improved performance under grid disturbances and the studied system is modeled and simulated in the MATLAB/Simulink environment.}, booktitle={2012 Students Conference on Engineering and Systems}, publisher={IEEE}, author={Anurag, Anup and Babu, B. Chitti}, year={2012}, month={Mar} }