Aydin Aysu

A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature

2024 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, pp. 90–100.

Enabling Secure and Efficient Sharing of Accelerators in Expeditionary Systems

Journal of Hardware and Systems Security, 8(2), 94–112.

Extended Abstract: Pre-Silicon Vulnerability Assessment for AI/ML Hardware

PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024, pp. 495–495.

Leaking secrets in homomorphic encryption with side-channel attacks

Aydin, F., & Aysu, A. (2024, January 12). JOURNAL OF CRYPTOGRAPHIC ENGINEERING.

Masking FALCON’s Floating-Point Multiplication in Hardware

IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024(4), 483–508.

Pre-Silicon Side-Channel Analysis of AI/ML Systems

RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 17(4).

TPUXtract: An Exhaustive Hyperparameter Extraction Framework

IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 78–103.

A Full-Stack Approach for Side-Channel Secure ML Hardware

A Survey of Software Implementations for the Number Theoretic Transform

In C. Silvano, C. Pilato, & M. Reichenbach (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023 (pp. 328–344).

Hardware-Software Co-design for Side-Channel Protected Neural Network Inference

2023 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, pp. 155–166.

Introduction to the Special Issue on the Digital Threats of Hardware Security

Digital Threats: Research and Practice, 4(2), 1–2.

SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs

2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS.

SeqL plus : Secure Scan-Obfuscation With Theoretical and Empirical Validation

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 42(5), 1406–1410.

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform

IEEE TRANSACTIONS ON COMPUTERS, 71(11), 2829–2843.

Apple vs. EMA Electromagnetic Side Channel Attacks on Apple CoreCrypto

PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, pp. 247–252.

Better Performance, Higher Reliability, More Security: Research Highlights from the Center for Advanced Electronics through Machine Learning

Electronic Device Failure Analysis, 24(2), 34–36.

Exposing Side-Channel Leakage of SEAL Homomorphic Encryption Library

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS

Guarding Machine Learning Hardware Against Physical Side-channel Attacks

ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(3).

Hands-On Teaching of Hardware Security for Machine Learning

High-Fidelity Model Extraction Attacks via Remote Power Monitors

2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA, pp. 328–331.

Multi-Tenant Cloud FPGAs: Side-Channel Security and Safety

In F. Regazzoni & M. van Dijk (Eds.), CCSW'22: Proceedings of the 2022 on Cloud Computing Security Workshop (pp. 7–8).

PR Crisis

RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library

Towards AI-Enabled Hardware Security: Challenges and Opportunities

2022 IEEE 28TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2022).

2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 40(6), 1217–1229.

An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum Signature

2021 IEEE 39TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2021), pp. 583–590.

Efficient, Flexible, and Constant-Time Gaussian Sampling Hardware for Lattice Cryptography

IEEE TRANSACTIONS ON COMPUTERS, 71(8), 1810–1823.

FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel Attacks

2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), pp. 691–696.

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols

ACM Transactions on Embedded Computing Systems, 20(6), 1–22.

ModuloNET: Neural Networks Meet Modular Arithmetic for Efficient Hardware Masking

IACR Transactions on Cryptographic Hardware and Embedded Systems, 506–556.

Single-Trace Side-Channel Attacks on omega-Small Polynomial Sampling

2021 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), pp. 35–45.

Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware

2021 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN (ICCAD).

iTimed: Cache Attacks on the Apple A10 Fusion SoC

2021 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), pp. 80–90.

A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography

BoMaNet: Boolean Masking of an Entire Neural Network

2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD).

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks

Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors

High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems

IEEE EMBEDDED SYSTEMS LETTERS, 12(4), 133–136.

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk

2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD).

MaskedNet: The First Hardware Inference Engine Aiming Power Side-Channel Protection

RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform

2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), pp. 26–32.

SeqL: Secure Scan-Locking for IP Protection

Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers

GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, pp. 237–242.

Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems

Binary Ring-LWE hardware with power side-channel countermeasures

Fresh re-keying with strong PUFs: A new approach to side-channel security

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols

A new maskless debiasing method for lightweight physical unclonable functions

Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA

A Design Method for Remote Integrity Checking of Complex PCBs

Compact and low‐power ASIP design for lightweight PUF‐based authentication protocols

IET Information Security, 10(5), 232–241.

Precomputation Methods for Hash-Based Signatures on Energy-Harvesting Platforms

IEEE Transactions on Computers, 65(9), 2925–2931.

A Flexible and Compact Hardware Architecture for the SIMON Block Cipher

BitCryptor: Bit-Serialized Flexible Crypto Engine for Lightweight Applications

End-To-End Design of a PUF-Based Privacy Preserving Authentication Protocol

Hardware/software co-design of physical unclonable function based authentications on FPGAs

Microprocessors and Microsystems, 39(7), 589–597.

The Future of Real-Time Security

ACM Transactions on Embedded Computing Systems, 14(3), 1–18.

A low power adaptive H.264 video encoder hardware

Analyzing and eliminating the causes of fault sensitivity analysis

SIMON Says: Break Area Records of Block Ciphers on FPGAs

IEEE Embedded Systems Letters, 6(2), 37–40.

Digital fingerprints for low-cost platforms using MEMS sensors

Low cost FPGA design and implementation of a stereo matching system for 3D-TV applications

Low-cost and area-efficient FPGA implementations of lattice-based cryptography

PASC: Physically authenticated stable-clocked soc platform on low-cost FPGAs

Three Design Dimensions of Secure Embedded Systems

A low energy adaptive hardware for H.264 multiple reference frame motion estimation

IEEE Transactions on Consumer Electronics, 57(3), 1377–1383.

A reconfigurable H.264 video encoder hardware

Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing

Presented at the SIN '10: 3rd International Conference of Security of Information and Networks.