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Works (22)
Updated: April 5th, 2024 11:05
2024 article
Leaking secrets in homomorphic encryption with side-channel attacks
Aydin, F., & Aysu, A. (2024, January 12). JOURNAL OF CRYPTOGRAPHIC ENGINEERING.
author keywords: Homomorphic encryption; SEAL; Number theoretic transform; Compiler optimizations; Side-channel attacks; Machine learning
TL;DR:
This article demonstrates side-channel leakages of the Microsoft SEAL HE library and proposes two attacks that can steal encryption keys during the key generation phase by abusing the leakage of ternary value assignments that occurs during the number theoretic transform (NTT) algorithm.
(via Semantic Scholar)
doi.org (repository)
Source: Web Of Science
Added: January 29, 2024
2023 article
Hardware-Software Co-design for Side-Channel Protected Neural Network Inference
2023 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST, HOST, pp. 155–166.
author keywords: machine learning inference; side-channel analysis; masking; flexibility
TL;DR:
This paper develops a secure RISCV-based coprocessor design that can execute a neural network implemented in C/C++ that uses masking to execute various neural network operations like weighted summations, activation functions, and output layer computation in a sidechannel secure fashion.
(via Semantic Scholar)
Source: Web Of Science
Added: August 7, 2023
2023 article
SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs
2023 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS.
author keywords: Multi-tenant cloud FPGAs; access control mechanism; memory isolation
TL;DR:
This paper proposes an improved access control mechanism for multi-tenant cloud FPGAs that allows dynamic configuration of access control privileges and has three advantages: enabling secure resource sharing of on-chip BRAMs to tenants, enabling safe sharing by resolving deadlocks and faulty access requests, and improvement in latency and throughput.
(via Semantic Scholar)
Source: Web Of Science
Added: September 11, 2023
2023 journal article
SeqL plus : Secure Scan-Obfuscation With Theoretical and Empirical Validation
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 42(5), 1406–1410.
author keywords: Flip-flops; Logic gates; Security; Complexity theory; Resists; Resilience; Iterative algorithms; IP piracy; scan-chains; scan-scrambling
TL;DR:
This study reveals the first formulation and complexity analysis of Boolean satisfiability (SAT)-based attack on scan-scrambling and proposes an iterative swapping-based scan-cell scrambling algorithm to defeat SAT-based attack.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
16. Peace, Justice and Strong Institutions
(OpenAlex)
Source: Web Of Science
Added: June 5, 2023
2022 journal article
An Extensive Study of Flexible Design Methods for the Number Theoretic Transform
IEEE TRANSACTIONS ON COMPUTERS, 71(11), 2829–2843.
author keywords: NTT; flexible; hardware; HLS; RISC-V
TL;DR:
An extensive study of flexible design methods for NTT implementation by evaluating three cases: parametric hardware design, high-level synthesis (HLS) design approach, and design for software implementation compiled on soft-core processors, where all are targeted on reconfigurable hardware devices.
(via Semantic Scholar)
Source: Web Of Science
Added: October 24, 2022
2022 article
Apple vs. EMA Electromagnetic Side Channel Attacks on Apple CoreCrypto
PROCEEDINGS OF THE 59TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC 2022, pp. 247–252.
TL;DR:
This work implements an optimized side channel acquisition infrastructure involving both custom iPhone software and accelerated analysis code and finds that an adversary which can observe 5--30 million known-ciphertext traces can reliably extract secret AES keys using electromagnetic (EM) radiation as a side channel.
(via Semantic Scholar)
Source: Web Of Science
Added: September 11, 2023
2022 article
FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS
2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022), pp. 113–121.
TL;DR:
An FPGA-based XGBoost accelerator designed with High-Level Synthesis (HLS) tools and design flow accelerating binary classification inference is showcased, showing a latency speedup of the proposed design over state-of-art CPU and GPU implementations, including energy efficiency and cost-effectiveness.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: October 11, 2022
2022 journal article
Guarding Machine Learning Hardware Against Physical Side-channel Attacks
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 18(3).
author keywords: Side-channel attack; neural networks; masking
TL;DR:
This work develops and combines different flavors of side-channel defenses for ML models in the hardware blocks and proposes and optimize the first defense based on Boolean masking, which impedes a straightforward second-order attack on the first-order masked implementation.
(via Semantic Scholar)
Source: Web Of Science
Added: December 5, 2022
2022 article
High-Fidelity Model Extraction Attacks via Remote Power Monitors
2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA, pp. 328–331.
author keywords: Neural networks; model stealing; time-to-digital converters; secure virtualization
TL;DR:
It is demonstrated that a remote monitor implemented with time-to-digital converters can be exploited to steal the weights from a hardware implementation of NN inference, which expands the attack vector to multi-tenant cloud FPGA platforms.
(via Semantic Scholar)
Source: Web Of Science
Added: November 7, 2022
2022 article
Towards AI-Enabled Hardware Security: Challenges and Opportunities
2022 IEEE 28TH INTERNATIONAL SYMPOSIUM ON ON-LINE TESTING AND ROBUST SYSTEM DESIGN (IOLTS 2022).
TL;DR:
The growing role of AI/ML techniques in hardware and architecture security field is highlighted and insightful discussions on pressing challenges, opportunities, and future directions of designing accurate and efficient machine learning-based attacks and defense mechanisms in response to emerging hardware security vulnerabilities in modern computer systems and next generation of cryptosystems are provided.
(via Semantic Scholar)
Source: Web Of Science
Added: October 24, 2022
2021 journal article
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 40(6), 1217–1229.
author keywords: Resistance; Performance evaluation; Deep learning; Protocols; Power measurement; Side-channel attacks; NIST; Cross-device; data-augmentation; deep learning (DL); lattice-based key-exchange protocols; power side channels
TL;DR:
2Deep—a deep-learning (DL)-based SCA—targeting parallelized implementations of PQKE protocols, namely, Frodo and NewHope with data augmentation techniques are proposed, exploring approaches that convert 1-D time-series power measurement data into 2-D images to formulate SCA an image recognition task.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: June 10, 2021
2021 article
An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum Signature
2021 IEEE 39TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2021), pp. 583–590.
author keywords: Hardware Security; Post-quantum Cryptography; Correlation Power Analysis; Digital Signature; Number Theoretic Transform
TL;DR:
This work proposes an efficient non-profiled Correlation Power Analysis (CPA) strategy on Dilithium to recover the secret key by targeting the underlying polynomial multiplication arithmetic and constructs a hybrid scheme that combines the advantages of both schemes.
(via Semantic Scholar)
Source: Web Of Science
Added: March 28, 2022
2021 journal article
Efficient, Flexible, and Constant-Time Gaussian Sampling Hardware for Lattice Cryptography
IEEE TRANSACTIONS ON COMPUTERS, 71(8), 1810–1823.
author keywords: Hardware; Cryptography; Gaussian distribution; Standards; Timing; Optimization; Encryption; Discrete gaussian sampling; lattice cryptography; FPGA
TL;DR:
The proposed hardware can support all the discrete Gaussian distributions used in post-quantum digital signatures and key encapsulation algorithms, the homomorphic encryption library of SEAL, and other algorithms such BLISS digital signature and LP public-key encryption.
(via Semantic Scholar)
Source: Web Of Science
Added: July 18, 2022
2021 article
FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel Attacks
2021 58TH ACM/IEEE DESIGN AUTOMATION CONFERENCE (DAC), pp. 691–696.
author keywords: side-channel attacks; post-quantum cryptography; digital signatures
TL;DR:
The first side-channel attack on FALCON—a NIST Round-3 finalist for the post-quantum digital signature standard—is proposed and a known-plaintext attack that uses the electromagnetic measurements of the device to extract the secret signing keys, which then can be used to forge signatures on arbitrary messages.
(via Semantic Scholar)
Source: Web Of Science
Added: March 28, 2022
2021 article
Single-Trace Side-Channel Attacks on omega-Small Polynomial Sampling
2021 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), pp. 35–45.
author keywords: Side-channel attacks; Post-quantum cryptography; NTRU; CRYSTALS-DILITHIUM
TL;DR:
A new single-trace side-channel attack on lattice-based post-quantum protocols is proposed, revealing that the sorting implementation in NTRU/NTRU Prime and the shuffling in CRYSTALS-DILITHIUM's ω-small polynomial sampling process leaks information about the ‘-1’’0’, or ’+1' assignments made to the coefficients.
(via Semantic Scholar)
Source: Web Of Science
Added: June 13, 2022
2021 article
Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware
2021 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN (ICCAD).
TL;DR:
This paper shows a new style of attack, for the first time, on ML models running on embedded devices by abusing the scan-chain infrastructure, and outperforms mathematical model extraction proposed in CRYPTO 2020, USENIX 2020, and ICML 2020.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure
(OpenAlex)
Source: Web Of Science
Added: February 21, 2022
2021 article
iTimed: Cache Attacks on the Apple A10 Fusion SoC
2021 IEEE INTERNATIONAL SYMPOSIUM ON HARDWARE ORIENTED SECURITY AND TRUST (HOST), pp. 80–90.
TL;DR:
It is found that the first cache timing side-channel attack on one of Apple's mobile devices can reduce the security of OpenSSL AES-128 by 50 more bits than a straightforward adaptation of PRIME+PROBE, while requiring only half as many side channel measurement traces.
(via Semantic Scholar)
Source: Web Of Science
Added: June 13, 2022
2020 article
BoMaNet: Boolean Masking of an Entire Neural Network
2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD).
author keywords: Masking; neural networks; side-channel attacks; model stealing
TL;DR:
This work proposes the first fully-masked neural network inference engine design and improves the traditional Trichina's AND gates by adding pipelining elements for better glitch-resistance and architecting the whole design to sustain a throughput of 1 masked addition per cycle.
(via Semantic Scholar)
Source: Web Of Science
Added: August 30, 2021
2020 journal article
High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems
IEEE EMBEDDED SYSTEMS LETTERS, 12(4), 133–136.
author keywords: Field programmable gate array (FPGA); hardware design; high-level synthesis (HLS); lattice-based cryptography; post-quantum cryptography
TL;DR:
A fast yet extensive design space exploration of NTT is demonstrated through the Vivado HLS tool, the shortcomings/challenges of optimized configurations are analyzed, and the results are quantitatively compared to software-based and hand-coded hardware designs.
(via Semantic Scholar)
Source: Web Of Science
Added: January 4, 2021
2020 article
Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk
2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD).
author keywords: machine learning; hardware security
TL;DR:
Novel applications of machine learning for hardware security, such as evaluation of post quantum cryptography hardware and extraction of physically unclonable functions from neural networks and practical model extraction attack based on electromagnetic side-channel measurements are demonstrated.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 30, 2021
2020 article
RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform
2020 30TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS (FPL), pp. 26–32.
author keywords: Lattice-Based Cryptography; RISC-V; NTT
TL;DR:
The proposed design is respectively 6x, 40x, and 3x more efficient than the baseline solution, Berkeley Out-of-Order Machine, and a prior HW/SW co-design, while providing the needed flexibility.
(via Semantic Scholar)
Source: Web Of Science
Added: August 23, 2021
2019 article
Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers
GLSVLSI '19 - PROCEEDINGS OF THE 2019 ON GREAT LAKES SYMPOSIUM ON VLSI, pp. 237–242.
author keywords: education; hardware security; post-quantum cryptography; FPGA
TL;DR:
A new graduate course on hardware security taught at North Carolina State University during Fall 2018 targets an audience with no background on cryptography or hardware vulnerabilities, and evolves into designing specialized hardware accelerators for post-quantum cryptography, executing sophisticated implementation attacks, and building countermeasures on such hardware designs.
(via Semantic Scholar)
Source: Web Of Science
Added: July 29, 2019
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