Aydin Aysu

A Comparison of Unified Multiplier Designs for the Falcon Post-quantum Digital Signature

Magesh, R., Ayyagari, M., Pendyala, S., & Aysu, A. (2026, January 1). Lecture Notes in Computer Science, Vol. 1.

ASIC Tape-Out of the First Side-Channel Protected Neural Network Design

Dubey, A., Cammarota, R., & Aysu, A. (2026, January 1). IEEE Design and Test.

Preemption-Enhanced Benchmark Suite for FPGAs

Malik, A. A., Buchanan, J., & Aysu, A. (2026, January 1). IEEE Access, Vol. 1.

CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon

Malik, A. A., Mihir, H., & Aysu, A. (2025, October 17).

Craft: Characterizing and root-causing fault injection threats at pre-silicon

ArXiv Preprint ArXiv:2503.03877.

Exploiting Power Side-Channel Vulnerabilities in XGBoost Accelerator

GateBleed: Exploiting On-Core Accelerator Power Gating for High Performance and Stealthy Attacks on AI

Hardware-Enabled Mechanisms for Verifying Responsible AI Development

Aidan, O. G., Kulp, G., Hodgkins, W., Petrie, J., Immler, V., Aysu, A., … Srivastava, A. (2025, July 20). SuperIntelligence - Robotics - Safety & Alignment.

Hardware-Enabled Mechanisms for Verifying Responsible AI Development

ArXiv Preprint ArXiv:2505.03742.

Integrating Cybersecurity in K-12 Education Through Hybrid Experiential Professional Development for Middle and High School Teachers

Journal of Technology and Teacher Education, 33(4), 721–752.

Machine Learning-Aided Detection of DoS Attacks in Power Systems using Side-Channel Monitoring

Khatua, R., Aysu, A., & Chakrabortty, A. (2025, October 26). (Vol. 10). Vol. 10.

Precision Strike: Targeted Misclassification of Accelerated CNNs with a Single Clock Glitch

Malik, A. A., Aydin, F., & Aysu, A. (2025, October 14). (Vol. 10). Vol. 10.

Quantum Leak: Timing Side-Channel Attacks on Cloud-Based Quantum Services

Lu, C., Telang, E., Aysu, A., & Basu, K. (2025, June 27).

SHIFT SNARE: Uncovering Secret Keys in FALCON via Single-Trace Analysis

Cryptology EPrint Archive.

Side-Channel Aware Training for Commercial Machine Learning Accelerators

Dubey, A., & Aysu, A. (2025, May).

Stochastic Training for Side-Channel Resilient AI

ArXiv Preprint ArXiv:2506.06597.

THEMIS: Time, Heterogeneity, and Energy Minded Scheduling for Fair Multi-Tenant Use in FPGAs

Karabulut, E., Malik, A. A., Awad, A., & Aysu, A. (2025, May 5). IEEE Transactions on Computers, Vol. 5.

THEMIS: Time, Heterogeneity, and Energy Minded Scheduling for Fair Multi-Tenant Use in FPGAs

IEEE Transactions on Computers.

TPUXtract: An Exhaustive Hyperparameter Extraction Framework

IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 78–103.

The Fellowship of the Leak: Power Analysis of a Masked FrodoKEM Hardware Accelerator

Schmid, M., Manzoni, G., Aysu, A., & Kavun, E. B. (2025, October 26). (Vol. 10). Vol. 10.

Timed Physical Password or Authentication Keys

Martin, A., Kiptoo, D. J., Kanoy, D. S., Li, S., Du, C., Kumar, M., … Thuo, M. (2025, May 16). ACS Applied Materials & Interfaces, Vol. 5.

Timed Physical Password or Authentication Keys

ACS Applied Materials & Interfaces.

A Hardware-Software Co-Design for the Discrete Gaussian Sampling of FALCON Digital Signature

Karabulut, E., & Aysu, A. (2024, May 6).

A hardware-software co-design for the discrete gaussian sampling of falcon digital signature

2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 90–100.

An Open Source Ecosystem for Implementation Security Testing

Cryptology EPrint Archive.

Enabling Secure and Efficient Sharing of Accelerators in Expeditionary Systems

Journal of Hardware and Systems Security, 8(2), 94–112.

Extended Abstract: Pre-Silicon Vulnerability Assessment for AI/ML Hardware

Aydin, F., Karabulut, E., & Aysu, A. (2024, June 10). (Vol. 6). Vol. 6.

Leaking secrets in homomorphic encryption with side-channel attacks

Aydin, F., & Aysu, A. (2024, January 12). Journal of Cryptographic Engineering.

Leaking secrets in homomorphic encryption with side-channel attacks

Journal of Cryptographic Engineering, 14(2), 241–251.

Masking FALCON’s Floating-Point Multiplication in Hardware

IACR Transactions on Cryptographic Hardware and Embedded Systems, 2024(4), 483–508.

Pre-Silicon Side-Channel Analysis of AI/ML Systems

Pre-Silicon Side-Channel Analysis of AI/ML Systems

2024 IEEE Physical Assurance and Inspection of Electronics (PAINE), 1–7.

Pre-silicon vulnerability assessment for AI/ML hardware

Proceedings of the Great Lakes Symposium on VLSI 2024, 495–495.

Quantum leak: Timing side-channel attacks on cloud-based quantum services

ArXiv Preprint ArXiv:2401.01521.

RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost

Gajjar, A., Kashyap, P., Aysu, A., Franzon, P., Choi, Y., Cheng, C., … Ignowski, J. (2024, August 12). ACM Transactions on Reconfigurable Technology and Systems, Vol. 8.

RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost

ACM Transactions on Reconfigurable Technology and Systems, 17(4), 1–33.

Side-Channel Aware Training for Commercial Machine Learning Accelerators

(US Patent Application No. 18/950,948).

TPUXtract: An Exhaustive Hyperparameter Extraction Framework

IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1), 78–103.

Technology and Systems

ACM Transactions On, 17(4).

A Full-Stack Approach for Side-Channel Secure ML Hardware

A Survey of Software Implementations for the Number Theoretic Transform

In C. Silvano, C. Pilato, & M. Reichenbach (Eds.), Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2023 (pp. 328–344).

A full-stack approach for side-channel secure ML hardware

2023 IEEE international test conference (ITC), 186–195.

Hardware-Software Co-design for Side-Channel Protected Neural Network Inference

Dubey, A., Cammarota, R., Varna, A., Kumar, R., & Aysu, A. (2023, May 1).

Hardware-Software Co-design for Side-Channel Protected Neural Network Inference

Cryptology EPrint Archive.

Introduction to the Special Issue on the Digital Threats of Hardware Security

Digital Threats: Research and Practice, 4(2), 1–2.

Introduction to the Special Issue on the Digital Threats of Hardware Security

Digital Threats: Research and Practice, Vol. 4, pp. 1–2. ACM New York, NY.

SS-AXI: Secure and Safe Access Control Mechanism for Multi-Tenant Cloud FPGAs

Karabulut, E., Awad, A., & Aysu, A. (2023, May 21). (Vol. 5). Vol. 5.

Apple vs. EMA

Haas, G., & Aysu, A. (2022, July 10). Proceedings of the 59th ACM/IEEE Design Automation Conference, Vol. 7.

Apple vs. EMA: electromagnetic side channel attacks on apple CoreCrypto

Proceedings of the 59th ACM/IEEE Design Automation Conference, 247–252.

Better Performance, Higher Reliability, More Security: Research Highlights from the Center for Advanced Electronics through Machine Learning

Electronic Device Failure Analysis, 24(2), 34–36.

Exposing Side-Channel Leakage of SEAL Homomorphic Encryption Library

Exposing Side-Channel Leakage of SEAL Homomorphic Encryption Library

Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 95–100.

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS

FAXID: FPGA-Accelerated XGBoost Inference for Data Centers using HLS

2022 IEEE 30th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 1–9.

Guarding Machine Learning Hardware Against Physical Side-channel Attacks

Dubey, A., Cammarota, R., Suresh, V., & Aysu, A. (2022, February 2). ACM Journal on Emerging Technologies in Computing Systems.

Guarding machine learning hardware against physical side-channel attacks

ACM Journal on Emerging Technologies in Computing Systems (JETC), 18(3), 1–31.

Hands-On Teaching of Hardware Security for Machine Learning

Hands-On Teaching of Hardware Security for Machine Learning

Proceedings of the Great Lakes Symposium on VLSI 2022, 455–461.

High-Fidelity Model Extraction Attacks via Remote Power Monitors

Dubey, A., Karabulut, E., Awad, A., & Aysu, A. (2022, June 13). 2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS).

High-Fidelity Model Extraction Attacks via Remote Power Monitors

2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 328–331.

Modulonet: neural networks meet modular arithmetic for efficient hardware masking

IACR Transactions on Cryptographic Hardware and Embedded Systems, 506–556.

Multi-Tenant Cloud FPGAs: Side-Channel Security and Safety

In F. Regazzoni & M. van Dijk (Eds.), CCSW'22: Proceedings of the 2022 on Cloud Computing Security Workshop (pp. 7–8).

PR Crisis

PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs

Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 101–106.

RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library

Reveal: Single-trace side-channel leakage of the seal homomorphic encryption library

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1527–1532.

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation

Potluri, S., Kundu, S., Kumar, A., Basu, K., & Aysu, A. (2022, August 15). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 8.

SeqL+: Secure Scan-Obfuscation with Theoretical and Empirical Validation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Towards AI-Enabled Hardware Security: Challenges and Opportunities

Sayadi, H., Aliasgari, M., Aydin, F., Potluri, S., Aysu, A., Edmonds, J., & Tehranipoor, S. (2022, September 12).

Towards AI-Enabled Hardware Security: Challenges and Opportunities

2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS), 1–10.

An Efficient Non-Profiled Side-Channel Attack on the CRYSTALS-Dilithium Post-Quantum Signature

Chen, Z., Karabulut, E., Aysu, A., Ma, Y., & Jing, J. (2021, October 1).

An efficient non-profiled side-channel attack on the CRYSTALS-Dilithium post-quantum signature

2021 IEEE 39th International Conference on Computer Design (ICCD), 583–590.

Efficient, flexible, and constant-time gaussian sampling hardware for lattice cryptography

IEEE Transactions on Computers, 71(8), 1810–1823.

Efficient,Flexible,and Constant-Time Gaussian Sampling Hardware for Lattice Cryptography

Karabulut, E., Alkim, E., & Aysu, A. (2021, January 1). IEEE Transactions on Computers.

FALCON Down: Breaking FALCON Post-Quantum Signature Scheme through Side-Channel Attacks

Karabulut, E., & Aysu, A. (2021, November 8).

Falcon Down: Breaking Falcon Post-Quantum Signature Scheme through Side-Channel Attacks

Design Automation Conference (DAC).

Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols

ACM Transactions on Embedded Computing Systems, 20(6), 1–22.

ModuloNET: Neural Networks Meet Modular Arithmetic for Efficient Hardware Masking

IACR Transactions on Cryptographic Hardware and Embedded Systems, 506–556.

Single-Trace Side-Channel Attacks on ω-Small Polynomial Sampling: With Applications to NTRU, NTRU Prime, and CRYSTALS-DILITHIUM

Karabulut, E., Alkim, E., & Aysu, A. (2021, December 12).

Single-trace side-channel attacks on $ω$-small polynomial sampling: with applications to NTRU, NTRU prime, and crystals-dilithium

2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 35–45.

Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware

Potluri, S., & Aysu, A. (2021, November 1). 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware

iTimed: Cache Attacks on the Apple A10 Fusion SoC

Haas, G., Potluri, S., & Aysu, A. (2021, December 12).

iTimed: Cache Attacks on the Apple A10 Fusion SoC

2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning

Kashyap, P., Aydin, F., Potluri, S., Franzon, P. D., & Aysu, A. (2020, November 17). IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 6, pp. 1–1.

2deep: Enhancing side-channel attacks on lattice-based key-exchange via 2-d deep learning

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 40(6), 1217–1229.

A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum Cryptography

A flexible and scalable NTT hardware: Applications from homomorphically encrypted deep learning to post-quantum cryptography

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 346–351.

An Extensive Study of Flexible Design Methods for the Number Theoretic Transform

Mert, A. C., Karabulut, E., Ozturk, E., Savas, E., & Aysu, A. (2020, August 19). IEEE Transactions on Computers, Vol. 8.

An extensive study of flexible design methods for the number theoretic transform

IEEE Transactions on Computers, 71(11), 2829–2843.

BoMaNet

Dubey, A., Cammarota, R., & Aysu, A. (2020, November 2). (Vol. 11). Vol. 11.

BoMaNet: Boolean masking of an entire neural network

Proceedings of the 39th International Conference on Computer-Aided Design, 1–9.

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors

Efficacy of satisfiability-based attacks in the presence of circuit reverse-engineering errors

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1–5.

Machine learning and hardware security

Regazzoni, F., Bhasin, S., Pour, A. A., Alshaer, I., Aydin, F., Aysu, A., … Yli-Mäyry, V. (2020, November 2). 2020 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED-DESIGN (ICCAD), Vol. 11.

Machine learning and hardware security: Challenges and opportunities

Proceedings of the 39th International Conference on Computer-Aided Design, 1–6.

MaskedNet: The First Hardware Inference Engine Aiming Power Side-Channel Protection

Maskednet: The first hardware inference engine aiming power side-channel protection

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 197–208.

RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform

Karabulut, E., & Aysu, A. (2020, August 1).

RANTT: A RISC-V Architecture Extension for the Number Theoretic Transform

30th International Conference on Field-Programmable Logic (FPL).

SeqL: Secure Scan-Locking for IP Protection

Seql: Secure scan-locking for ip protection

2020 21st International Symposium on Quality Electronic Design (ISQED), 7–13.

Trustworthy ai inference systems: An industry research view

ArXiv Preprint ArXiv:2008.04449.

Fast and efficient implementation of lightweight crypto algorithm PRESENT on FPGA through processor instruction set extension

2019 IEEE East-West Design & Test Symposium (EWDTS), 1–5.

High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems

Ozcan, E., & Aysu, A. (2019, December 17). IEEE Embedded Systems Letters.

High-level synthesis of number-theoretic transform: A case study for future cryptosystems

IEEE Embedded Systems Letters, 12(4), 133–136.

Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers

Aysu, A. (2019, May 13).

Teaching the Next Generation of Cryptographic Hardware Design to the Next Generation of Engineers

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 237–242.

Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems

Using power-anomalies to counter evasive micro-architectural attacks in embedded systems

2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 111–120.

Binary Ring-LWE hardware with power side-channel countermeasures

Binary Ring-LWE hardware with power side-channel countermeasures

2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1253–1258.

Fresh re-keying with strong PUFs: A new approach to side-channel security

Fresh re-keying with strong PUFs: A new approach to side-channel security

2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 118–125.

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols

Horizontal side-channel vulnerabilities of post-quantum key exchange protocols

2018 IEEE international symposium on hardware oriented security and trust (HOST), 81–88.

A new maskless debiasing method for lightweight physical unclonable functions

A new maskless debiasing method for lightweight physical unclonable functions

2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 134–139.

Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA

Secure and Private, yet Lightweight, Authentication for the IoT via PUF and CBKA

Information Security and Cryptology--ICISC 2016: 19th International Conference, Seoul, South Korea, November 30--December 2, 2016, Revised Selected Papers 19, 28–48.

Security protocols for unified near field communication infrastructures

Statement of Research Interests

Https://Research.ece.ncsu.edu/Aaysu/Wp-Content/Uploads/Research_Statement.Pdf.

A Design Method for Remote Integrity Checking of Complex PCBs

A design method for remote integrity checking of complex PCBs

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1517–1522.

Compact and low‐power ASIP design for lightweight PUF‐based authentication protocols

IET Information Security, 10(5), 232–241.

Resource-constrained and resource-efficient modern cryptosystem design

(Doctoral Dissertation). Virginia Polytechnic Institute and State University.

Security protocols for unified near field communication infrastructures

(US Patent No. 9497573 B2).

Security protocols for unified near field communication infrastructures

Guo, X., & Aysu, A. (2016, November).

A Flexible and Compact Hardware Architecture for the SIMON Block Cipher

A flexible and compact hardware architecture for the SIMON block cipher

Lightweight Cryptography for Security and Privacy: Third International Workshop, LightSec 2014, Istanbul, Turkey, September 1-2, 2014, Revised Selected Papers 3, 34–50.