@inproceedings{azidehak_agarwal_yousefpoor_dean_bhattacharya_2017, title={Resilient two dimensional redundancy based fault-tolerant controller array for modular multi-level converters}, volume={2017-January}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85041490609&partnerID=MN8TOARS}, DOI={10.1109/ecce.2017.8095856}, abstractNote={In this paper, a state-of-the-art controller architecture for controlling modular multi-level converter (MMC) family is proposed. By using this controller architecture, single point of failure in the power converter, controller board or the communication network does not interrupt the functionality of the system. In order to achieve that, a two-dimensional array of controllers are formed to handle the MMC. In this architecture, a selected master controller is synchronizing slave controllers. In addition, adjacent slave controllers check the internal functionality of each other. In case of failure detection, the failed component will be isolated from system and the converter may continue its operation without interruption. This paper covers synchronization mechanism for slave controllers, master controller selection, and presents experimental results for the proposed controller.}, booktitle={2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017}, author={Azidehak, A.H. and Agarwal, R. and Yousefpoor, N. and Dean, A.G. and Bhattacharya, Subhashish}, year={2017}, pages={722–729} }
 @inproceedings{hazra_dean_bhattacharya_2015, title={Doubly-fed induction generator enabled power generation in ocean wave energy conversion system}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84963576837&partnerID=MN8TOARS}, DOI={10.1109/ecce.2015.7310637}, abstractNote={This paper proposes a power architecture to utilize doubly-fed induction generator (DFIG) for power generation from oscillating wave energy converter (WEC). Unlike in wind energy conversion system, the stator circuit of the DFIG can not be tied directly with the grid in wave energy conversion system (WECS). In WECS, the speed of the DFIG oscillates from one direction to another. Due to the change of direction of the speed, the stator of the DFIG is proposed to be connected with the grid with switched phase sequence. Also, at low operating speed the DFIG slip speed increases which requires higher voltage rating of the rotor side converter. Therefore, to operate the DFIG with limited rotor side voltage the stator circuit is short circuited at low speed. With these modifications, the DFIG based power architecture is proposed to generate power from WECS. In this paper, the overall hardware and control architecture and system operation are presented. System operation is validated through simulation in MATLAB-Simulink platform. For simulation of the whole system, a WEC model is considered.}, booktitle={2015 IEEE Energy Conversion Congress and Exposition, ECCE 2015}, author={Hazra, S. and Dean, A.G. and Bhattacharya, Subhashish}, year={2015}, pages={6978–6985} }
 @article{moore_dean_2015, title={Intra-Operation Dynamic Voltage Scaling}, DOI={10.1109/cpsna.2015.22}, abstractNote={Embedded peripheral devices are often specified with a range of performance characteristics that are determined by their supply voltage. Recent research explored the benefits of modulating peripheral supply voltage with task-level granularity. With Intra-Operation Dynamic Voltage Scaling (IODVS), we further reduce the energy consumption of peripheral devices by modulating the peripheral supply voltage at critical states occurring during operation of the peripheral device. IODVS is designed to have minimal impact on CPU utilization through the use of a lookup table that designates an ideal voltage on a per-state basis. IODVS is unique in that during high-performance states such as data-transmission, peripherals can have the high supply voltage required to reduce overall energy-delay product. Likewise, during low-performance states such as mandatory delays, the system decreases peripheral domain voltage thus reducing energy consumption without adversely affecting performance or correctness. We demonstrate this method on various peripherals common to wireless sensor nodes and have found total energy savings of up to 40%.}, journal={2015 IEEE 3RD INTERNATIONAL CONFERENCE ON CYBER-PHYSICAL SYSTEMS, NETWORKS, AND APPLICATIONS CPSNA 2015}, author={Moore, Daniel R. and Dean, Alexander G.}, year={2015}, pages={70–77} }
 @inproceedings{juneja_dean_bhattacharya_2015, title={Using real-time system design methods to integrate SMPS control software with application software}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84963563112&partnerID=MN8TOARS}, DOI={10.1109/ecce.2015.7310485}, abstractNote={A switch-mode power supply (SMPS) converts power efficiently between different voltage levels, making power optimizations through voltage scaling feasible. SMPS controllers are generally dedicated hardware (analog/digital circuits, microcontroller (MCU), digital signal processor (DSP)), and so are expensive to add to very low cost embedded applications. In this work, we show how to integrate SMPS control software into the MCU running application software, which reduces system cost while increasing the design space and flexibility for developers. Real-time system design methods are employed to ensure SMPS voltage regulation quality, while retaining the original embedded application behavior. Our methods apply to a wide range of software task schedulers, from simple interrupt-based foreground/background systems to sophisticated preemptive real-time kernels (RTOS). We demonstrate our methods on a position-logging embedded system, with multiple voltage domains controlled in software, resulting in power savings.}, booktitle={2015 IEEE Energy Conversion Congress and Exposition, ECCE 2015}, author={Juneja, A. and Dean, A.G. and Bhattacharya, Subhashish}, year={2015}, pages={5880–5887} }
 @inproceedings{stout_dean_2015, title={Voltage source based voltage-to-time converter}, DOI={10.1109/mwscas.2015.7282107}, abstractNote={Voltage-to-time converter (VTC) circuits are used as the core component of single-slope analog to digital converters (ADCs). These VTC circuits have traditionally depended on the use of a constant current source as part of their implementation in order to have good linearity. An alternative approach is presented where only voltage sources and a few discrete components are needed without sacrificing linearity. This circuit can be realized in hardware using general purpose IO (GPIO) pins that are available on all microcontrollers, FPGAs, and CPLDs. This provides more flexibility than current source based VTCs that rely on specialized hardware, allowing for a full ADC to be built using GPIO pins with no specialized ADC hardware.}, booktitle={2015 ieee 58th international midwest symposium on circuits and systems (mwscas)}, author={Stout, T. and Dean, A.}, year={2015} }
 @article{so_dean_2013, title={Software thread integration for instruction-level parallelism}, volume={13}, DOI={10.1145/2501626.2512466}, abstractNote={Multimedia applications require a significantly higher level of performance than previous workloads of embedded systems. They have driven digital signal processor (DSP) makers to adopt high-performance architectures like VLIW (Very-Long Instruction Word). Despite many efforts to exploit instruction-level parallelism (ILP) in the application, the speed is a fraction of what it could be, limited by the difficulty of finding enough independent instructions to keep all of the processor's functional units busy.}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={So, W. and Dean, A. G.}, year={2013} }
 @book{dean_conrad_2012, title={Creating fast, responsive and energy-efficient embedded systems using the Renesas RL78 microcontroller}, publisher={Weston, Florida: Micrium Press}, author={Dean, A. G. and Conrad, J. M.}, year={2012} }
 @inproceedings{shah_juneja_bhattacharya_dean_2012, title={High frequency GaN device-enabled CubeSat EPS with real-time scheduling}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84870948186&partnerID=MN8TOARS}, DOI={10.1109/ecce.2012.6342522}, abstractNote={This paper describes the hardware and software architectures and experimental results of a flexible and scalable electric power system (EPS) for CubeSat applications. The EPS has the three flexible battery charging modules (FBCM) to charge the battery and the four flexible digital point of load (FDPOL) converters to drive loads. It uses the maximum power point tracking (MPPT) algorithm to maximize output power from the solar arrays along with the battery state of health and state of charge determination algorithms to determine the health of the Li-ion batteries. This paper also evaluates converter performance with GaN devices driven at high frequencies in order to reduce the size of the filter components and provide better control of the converters. Analysis of a sample load's transients and its voltage regulation, using a real-time operating system (RTOS), is also discussed briefly in this paper.}, booktitle={2012 IEEE Energy Conversion Congress and Exposition, ECCE 2012}, author={Shah, M. and Juneja, A. and Bhattacharya, Subhashish and Dean, A.G.}, year={2012}, pages={2934–2941} }
 @article{kang_dean_2012, title={Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation}, ISSN={["1545-3421"]}, DOI={10.1109/rtas.2012.22}, abstractNote={Although a data cache provides fast access latency, it degrades the timing predictability of real-time embedded systems due to misses which are difficult to predict. Scratch pad memory is accessed as fast as a data cache, but does not suffer from unpredicted misses thanks to its software-controlled mechanism. This study presents how scratch pad memory reduces data cache pollution and misses for preemptive real-time embedded systems, so that both of the fast memory subsystems can work together with synergy. First, by classifying data cache misses into intrinsic misses and interference misses we reveal previously hidden characteristics of the interactions between data in the cache. Second, we suggest a heuristic method of data allocation to scratch pad memory using the new perspective, which reduces the cache pollution and finally improve the cache performance. Third, we examine these concepts with several tasks running on a real hardware platform and a preemptive real-time operating system. In addition, we perform a supplementary case study which shows how sensitive the data cache is to small changes of data memory layout and its dynamic contents. Our proposed scheme guides us through the synergetic process by using scratch pad memory beyond the sensitive data cache. In our experiments, the proposed data allocation scheme significantly reduces inter-task cache pollution as well as the intrinsic cache misses of the tasks themselves.}, journal={2012 IEEE 18TH REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS)}, author={Kang, Sangyeol and Dean, Alexander G.}, year={2012}, pages={119–128} }
 @article{peng_parsons_dean_2012, title={RESOURCE-FOCUSED TOOLCHAIN FOR RAPID PROTOTYPING OF EMBEDDED SYSTEMS}, volume={21}, ISSN={["1793-6454"]}, DOI={10.1142/s0218126612400038}, abstractNote={ This paper introduces the RaPTEX toolchain and its use for rapid prototyping and evaluation of embedded communication systems. This toolchain is unique for several reasons. First, by using static code analysis techniques, it is able to predict both the typical case and bounds for resource usage, such as computational, memory (both static and dynamic), and energy requirements. Second, it provides a graphical user interface with configurable software building blocks which allows easy creation and customization of protocol stacks. Third, it targets low-cost, low-energy hardware, allowing the creation of low-cost systems. We demonstrate the RaPTEX toolchain by evaluating different design options for an experimental ultrasonic communication system for biotelemetry in extremely shallow waters. The power, size, mass, and cost constraints of this application make it critical to pack as much processing into the available resources as possible. The RaPTEX toolchain analyzes resource use, enabling the system to safely operate closer to the edge of the resource envelope. The toolchain also helps users with the rapid prototyping of communication protocols by providing users with quick feedback on resource requirements. We demonstrate the use and output of the toolchain. We compare the accuracy of its predictions against measurements of the real hardware. }, number={2}, journal={JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS}, author={Peng, Shaolin and Parsons, Gregory and Dean, Alexander G.}, year={2012}, month={Apr} }
 @article{sachidananda_dean_2011, title={EMI- and Energy-Aware Scheduling of Switching Power Supplies in Hard Real-Time Embedded Systems}, ISSN={["1080-1812"]}, DOI={10.1109/rtas.2011.20}, abstractNote={In this paper we present the Make And Take(MAT) approach for adding switch-mode power supply (SMPS) control to hard real-time systems. MAT enables control of the SMPS with the task scheduler and this allows the designer to use a less expensive and smaller (but noisier) SMPS without it affecting circuits sensitive to electromagnetic interference (EMI) such as high-impedance input signals and amplifiers. The MAT concept is both energy and EMI aware and schedules the tasks based on the total energy in the system by segregating them as either a producer or consumer of energy. We discuss MAT in detail and show how it can be applied to both preemptive and non-preemptive scheduling approaches. We present several properties of MAT and their impact on the system, in terms of energy and real-time scheduling decisions. We demonstrate its usage by implementing a simple processor controlled boost SMPS on a non-preemptive real-time embedded platform.}, journal={17TH IEEE REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS 2011)}, author={Sachidananda, Subash and Dean, Alexander}, year={2011}, pages={123–133} }
 @article{lim_jang_yoon_sichitiu_dean_2010, title={RaPTEX: Rapid Prototyping Tool for Embedded Communication Systems}, volume={7}, ISSN={["1550-4859"]}, DOI={10.1145/1806895.1806902}, abstractNote={Advances in microprocessors, memory, and radio technology have enabled the emergence of embedded systems that rely on communication systems to exchange information and coordinate their activities in spatially distributed applications. However, developing embedded communication systems that satisfy specific application requirements is a challenge due to the many tradeoffs imposed by different choices of underlying protocols and their parameters. Furthermore, evaluating the correctness and performance of the design and implementation before deploying it is a nontrivial task due to the complexity of the resulting system. This article presents the design and implementation of RaPTEX, a rapid prototyping tool for embedded communication systems, especially well suited for wireless sensor networks (WSNs), consisting of three major subsystems: a toolbox, an analytical performance estimation framework, and an emulation environment. We use a hierarchical approach in the design of the toolbox to facilitate the composition of the network stack. For fast exploration of the tradeoff space at design time, we build an analytical performance estimation model for energy consumption, delay, and throughput. For realistic performance evaluation, we design and implement a hybrid, accurate, yet scalable, emulation environment. Through three use cases, we study the tradeoff space for different protocols and topologies, and highlight the benefits of using RaPTEX for designing and evaluating embedded communication systems for WSNs.}, number={1}, journal={ACM TRANSACTIONS ON SENSOR NETWORKS}, author={Lim, Jun Bum and Jang, Beakcheol and Yoon, Suyoung and Sichitiu, Mihail L. and Dean, Alexander G.}, year={2010}, month={Aug} }
 @article{berekovic_chaudhary_dean_fritts_2009, volume={33}, ISSN={0141-9331}, url={http://dx.doi.org/10.1016/j.micpro.2009.02.001}, DOI={10.1016/j.micpro.2009.02.001}, number={4}, journal={Microprocessors and Microsystems}, publisher={Elsevier BV}, author={Berekovic, Mladen and Chaudhary, Vipin and Dean, Alex and Fritts, Jason}, year={2009}, month={Jun}, pages={233–234} }
 @article{berekovic_chaudhary_dean_fritts_2009, title={Special issue: Media and stream processing}, volume={33}, number={4}, journal={Microprocessors and Microsystems}, author={Berekovic, M. and Chaudhary, V. and Dean, A. and Fritts, J.}, year={2009}, pages={233–234} }
 @article{kumar_asokan_shivshankar_dean_2007, title={Efficient software implementation of embedded communication protocol controllers using asynchronous software thread integration with time- and space-efficient procedure calls}, volume={6}, ISSN={["1558-3465"]}, DOI={10.1145/1210268.1210270}, abstractNote={The overhead of context switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. A software-implemented protocol controller may be crippled by this problem. The available idle time may be too short to recover through context switching, so only the primary thread can execute during message activity, slowing the secondary threads and potentially missing deadlines. Asynchronous software thread integration (ASTI) uses coroutine calls and integration, letting threads make independent progress efficiently, and reducing the needed context switches. We demonstrate the methods with a software implementation of an automotive communication protocol (J1850) and several secondary threads.}, number={1}, journal={ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS}, author={Kumar, Nagendra J. and Asokan, Vasanth and Shivshankar, Siddhartha and Dean, Alexander G.}, year={2007}, month={Feb} }
 @article{so_dean_2005, title={Complementing software pipelining with software thread integration}, volume={40}, ISSN={["1558-1160"]}, DOI={10.1145/1070891.1065930}, abstractNote={Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in high-performance embedded applications such as digital signal processing. Software thread integration (STI) can often improve the performance of looping code in cases where software pipelining performs poorly or fails. This paper examines both situations, presenting methods to determine what and when to integrate.We evaluate our methods on C-language image and digital signal processing libraries and synthetic loop kernels. We compile them for a very long instruction word (VLIW) digital signal processor (DSP) -- the Texas Instruments (TI) C64x architecture. Loops which benefit little from software pipelining (SWP-Poor) speed up by 26% (harmonic mean, HM). Loops for which software pipelining fails (SWP-Fail) due to conditionals and calls speed up by 16% (HM). Combining SWP-Good and SWP-Poor loops leads to a speedup of 55% (HM).}, number={7}, journal={ACM SIGPLAN NOTICES}, author={So, W and Dean, AG}, year={2005}, month={Jul}, pages={137–146} }
 @article{welch_kanaujia_seetharam_thirumalai_dean_2005, title={Supporting demanding hard-real-time systems with STI}, volume={54}, ISSN={["1557-9956"]}, DOI={10.1109/TC.2005.169}, abstractNote={Software thread integration (STI) is a compilation technique which enables the efficient use of an application's fine-grain idle time on generic processors without special hardware support. With STI, a primary function is automatically interleaved with a secondary function to create a single implicitly multithreaded function which minimizes context switching and, hence, both improves performance and also offers very fine-grain concurrency. In this work, we extend STI techniques to address two challenges. First, we reduce response time for interrupts or other high-priority threads by introducing polling servers into integrated threads. Second, we enable integration with long host threads, expanding the domain of STI. We derive methods to evaluate the response time for threads in systems with and without these new integration methods. We demonstrate these concepts with the integration of various threads in a sample hard-real-time system on a highly-constrained microcontroller. We use an inexpensive 20 MHz AVR 8-bit microcontroller to generate monochrome NTSC video while servicing a high-speed (115,2 kbaud) serial communication link. We have built and tested this system, achieving graphics rendering speed-ups of 3.99/spl times/ to 13.5/spl times/.}, number={10}, journal={IEEE TRANSACTIONS ON COMPUTERS}, author={Welch, BJ and Kanaujia, SO and Seetharam, A and Thirumalai, D and Dean, AG}, year={2005}, month={Oct}, pages={1188–1202} }
 @article{kumar_shivshankar_dean_2004, title={Asynchronous software thread integration for efficient software implementations of embedded communication protocol controllers}, volume={39}, ISSN={["1558-1160"]}, DOI={10.1145/998300.997170}, abstractNote={
            The overhead of context-switching limits efficient scheduling of multiple concurrent threads on a uniprocessor when real-time requirements exist. Existing software thread integration (STI) methods reduce context switches, but only provide synchronous thread progress within integrated functions. For the remaining, non-integrated portions of the secondary threads to run and avoid starvation, the primary thread must have adequate amounts of coarse-grain idle time (longer than two context-switches). We have developed
            asynchronous
            software thread integration (ASTI) methods which address starvation through the efficient use of coroutine calls and integration. ASTI allows threads to make independent progress efficiently and reduces the number of context switches needed through integration.Software-implemented protocol controllers are crippled by this problem; the primary thread "bit-bangs" each bit of a message onto or off of the bus, leaving only fragments of idle time shorter than a bit time. This fragmented time may be too short to recover through context switching, so only the primary thread can execute during message transmission or reception, slowing the secondary threads and potentially making them miss their deadlines. ASTI simplifies the implementation of embedded communication protocols on low-cost, moderate speed (1 - 100 MHz, 8- and 16-bit) microcontrollers. We demonstrate ASTI by replacing a standard automotive communication protocol controller (J1850) with software and generic hardware. Secondary thread performance improves significantly when compared with a traditional interrupt-based software approach.
          }, number={7}, journal={ACM SIGPLAN NOTICES}, author={Kumar, NJ and Shivshankar, S and Dean, AG}, year={2004}, month={Jul}, pages={37–46} }
 @article{dean_2004, title={Efficient real-time fine-grained concurrency on low-cost microcontrollers}, volume={24}, number={4}, journal={IEEE Micro}, author={Dean, A. G.}, year={2004}, pages={38282} }