@article{liu_zhang_isukapati_ashik_morgan_lee_sung_fayed_white_agarwal_2022, title={SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology}, volume={10}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2022.3150364}, abstractNote={Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Liu, Tianshi and Zhang, Hua and Isukapati, Sundar Babu and Ashik, Emran and Morgan, Adam J. and Lee, Bongmook and Sung, Woongje and Fayed, Ayman and White, Marvin H. and Agarwal, Anant K.}, year={2022}, pages={129–138} }
 @inproceedings{mehrotra_morgan_hopkins_2021, title={Design and Characterization of 3.3 kV-15 kV rated DBC Power Modules for Developmental Testing of WBG devices}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487311}, DOI={10.1109/APEC42165.2021.9487311}, abstractNote={An increasing number of power circuit designers are moving into designs at the bare die module-level to achieve greater circuit integration for lower inductance and better thermal management. Similarly, those who will use off-the-self modules are looking deeper inside the power modules to understand, discern, and optimize differences that impact gate driver design, power-loop designs and electro-physical layout between bare die. The ability for designers to have a greater understanding of the die-level module further advances adoption of WBG devices. This paper provides a description of open-source designs, fabrication, and test results for two DBC-based power modules. One is a SOT-227 footprint -based 6.5 kV DBC module, while the other is a 15 kV DBC module. The modules are specifically designed for mounting and testing new WBG power semiconductors under development, and as such, are designed for extreme operations under test. The characterization of the two modules and detailed insight into the ‘why’ in the design decisions provides the working engineer a clear understanding of variances in power module parameters and resulting effects on the module performance. The module designs are scalable, house single and multiple diodes and/or MOSFETs, include built-in current-sense and temperature monitoring, have Kelvin drain-source connections to reduce blanking-time, and utilize techniques to reduce stray inductance and resistance. The full designs are available for anyone’s use at www.go.ncsu.edu/prees_open_source}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Morgan, Adam J. and Hopkins, Douglas C.}, year={2021}, month={Jun}, pages={2351–2356} }
 @inproceedings{gao_morgan_xu_zhao_hopkins_2018, title={6.0kV, 100A, 175kHz super cascode power module for medium voltage, high power applications}, url={https://www.lens.org/131-133-888-704-704}, DOI={10.1109/apec.2018.8341182}, abstractNote={A new 6.0kV/100A Super Cascode Power Module (SCPM) topology is proposed using dual serial strings of six SiC-JFETs with a common balancing circuit, and extendable to 8.0kV/200A for high-frequency, medium-voltage applications. Electrical and multi-physics simulations show improvements in dynamic response, and improved electro-thermal performance that exceed state-of-the-art Si-IGBT power module technology. The SCPM is fabricated and tested. Results are reported showing 47.8mΩ dynamic response, and ≤50ns rise and fall in current at 4kV for 110A switching from double-pulse testing (DPT).}, note={\urlhttps://ieeexplore.ieee.org/document/8341182}, booktitle={Thirty-third annual ieee applied power electronics conference and exposition (apec 2018)}, author={Gao, B. and Morgan, A. J. and Xu, Y. and Zhao, X. and Hopkins, Douglas C}, year={2018}, pages={1288–1293} }
 @article{de_morgan_iyer_ke_zhao_vechalapu_bhattacharya_hopkins_2018, title={Design, Package, and Hardware Verification of a High-Voltage Current Switch}, volume={6}, ISSN={2168-6777}, url={http://dx.doi.org/10.1109/JESTPE.2017.2727051}, DOI={10.1109/jestpe.2017.2727051}, abstractNote={In this paper, an attempt has been made to demonstrate various package design considerations to accommodate series connection of high voltage Si-IGBT (6500V/25A die) and SiC-Diode (6500V/25A die). The effects of connecting the cathode of the series diode to the collector of the IGBT versus connecting the emitter of the IGBT to the anode of the series diode have been analyzed in regards to parasitic line inductance of the structure. Various simulation results have then been used to redesign and justify the optimized package structure for the final current switch design. The package is fabricated using the optimized parameters. A double pulse test-circuit has been assembled. Initial hardware results have been shown to verify functioning. The main motivation of this work is to enumerate detailed design considerations for packing a high voltage current switch package.}, note={\urlhttps://ieeexplore.ieee.org/document/7981339/}, number={1}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={De, A. and Morgan, A. J. and Iyer, V. Mahadeva and Ke, H. and Zhao, X. and Vechalapu, K. and Bhattacharya, S. and Hopkins, D. C.}, year={2018}, month={Mar}, pages={441–450} }
 @inproceedings{morgan_choobineh_fresne_hopkins_2017, title={Numerical and Experimental Determination of Temperature Distribution in 3D Stacked Power Devices}, url={http://dx.doi.org/10.1115/IPACK2017-74222}, DOI={10.1115/ipack2017-74222}, abstractNote={During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.}, note={\urlhttps://proceedings.asmedigitalcollection.asme.org/proceeding.aspx?articleid=2660938 ; \urlhttp://proceedings.asmedigitalcollection.asme.org/proceeding.aspx?articleid=2660938 ; \urlhttps://asmedigitalcollection.asme.org/InterPACK/proceedings/InterPACK2017/58097/V001T01A002/266226}, booktitle={ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems}, publisher={American Society of Mechanical Engineers}, author={Morgan, Adam and Choobineh, Leila and Fresne, David and Hopkins, Douglas C.}, year={2017}, month={Aug} }
 @inproceedings{morgan_xu_hopkins_husain_yu_2016, title={Decomposition and electro-physical model creation of the CREE 1200V, 50A 3-Ph SiC module}, url={https://www.lens.org/005-651-099-193-878}, DOI={10.1109/apec.2016.7468163}, abstractNote={The CREE 1200V/50A, 25mΩ 6-Pack SiC MOSFET module (CCS050M12CM2) is decomposed into a full 3D CAD model, and materials identified, for use in electrical circuit and multi-physics simulations. A reverse engineering technique is first developed, outlined, and then demonstrated on the CREE module. The ANSYS Q3D Extractor is applied to the 3D CAD model where electrical, lumped parameter, parasitic circuit elements are determined. The model is also analyzed with a multi-physics simulator to provide in-situ thermal maps of the baseplate surface for application scenarios, e.g. with a thermal interface material and pin fin heat sink to capture the thermal spreading from junction to case. The complete model is made open source and freely distributed for use by the reader.}, note={\urlhttps://ieeexplore.ieee.org/document/7468163 ; \urlhttps://works.bepress.com/kang-peng/10/download/ ; \urlhttps://works.bepress.com/kang-peng/10/}, booktitle={Apec 2016 31st annual ieee applied power electronics conference and exposition}, author={Morgan, A. J. and Xu, Y. and Hopkins, Douglas C and Husain, I. and Yu, W. S.}, year={2016}, pages={2141–2146} }
 @inproceedings{de_morgan_iyer_ke_zhao_vechalapu_bhattacharya_hopkins_2016, title={Design, package, and hardware verification of a high voltage current switch}, volume={2016-May}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84973664278&partnerID=MN8TOARS}, DOI={10.1109/apec.2016.7467887}, abstractNote={This paper demonstrates various electrical and package design considerations in series connecting a high-voltage (HV) silicon (Si)-IGBT (6500-V/25-A die) and a silicon carbide-junction barrier Schottky diode (6500-V/25-A die) to form an HV current switch. The effects of connecting the cathode of the series diode to an IGBT collector, versus connecting the IGBT emitter to the anode of the series diode, are analyzed in regards to minimizing the parasitic inductance. An optimized package structure is discussed and an HV current switch module is custom fabricated in the laboratory. An HV double pulse test circuit is used to verify the switching performance of the current switch module. Low-voltage and HV converter prototypes are developed and tested to ensure thermal stability of the same. The main motivation of this paper is to enumerate detailed design considerations for packaging an HV current switch.}, note={\urlhttps://ieeexplore.ieee.org/document/7467887/}, booktitle={Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC}, author={De, A. and Morgan, A. and Iyer, V.M. and Ke, H. and Zhao, X. and Vechalapu, K. and Bhattacharya, Subhashish and Hopkins, D.C.}, year={2016}, pages={295–302} }
 @inproceedings{de_morgan_bhattacharya_hopkins_2015, title={Design considerations of packaging a high voltage current switch}, booktitle={International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, 2015, vol 3}, author={De, A. and Morgan, A. and Bhattacharya, S. and Hopkins, D. C.}, year={2015} }