Aravindh Anantaraman

Works (8)

Updated: July 5th, 2023 15:55

2008 patent

System and method for reducing jet streaks in hydroentangled fibers

By: B. Pourdeyhimi , H. Tafreshi  & N. Anantharamaiah

Source: NC State University Libraries
Added: August 6, 2018

2006 journal article

FAST: Frequency-Aware Static Timing Analysis

ACM Transactions on Programming Languages and Systems, 5(1), 200–224.

By: K. Seth, A. Anantaraman, F. Mueller & E. Rotenberg

Source: NC State University Libraries
Added: August 6, 2018

2006 journal article

Non-uniform program analysis & repeatable execution constraints: Exploiting out-of-order processors in real-time systems

Non-uniform program analysis & repeatable execution constraints: Exploiting out-of-order processors in real-time systems. SIGBED Review, 3(1).

By: A. Anantaraman n & E. Rotenberg n

TL;DR: The objective of this paper is to enable easy, tight, and safe timing analysis of contemporary complex processors by exploiting the fact that out-of-order processors can be analyzed via simulation in the absence of variable control-flow. (via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018

2005 chapter

Architecture of embedded microprocessors

In W. Wolf & A. Jerraya (Eds.), Multiprocessor systems on chips (pp. 81–112).

By: E. Rotenberg* & A. Anantaraman*

Ed(s): W. Wolf & A. Jerraya

TL;DR: This chapter reviews the reasons for the parallel evolution of embedded and desktop processors and reasons for dual tracks targeting open versus closed embedded systems—these systems constrain microarchitectural evolution due to the need for timing predictability. (via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018

2005 article

Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (VISA)

25TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 114–125.

By: A. Anantaraman n, K. Seth*, E. Rotenberg n & F. Mueller n

TL;DR: A VISA variant is proposed that dynamically accrues the slack needed to facilitate speculation in the complex mode, eliminating the need to statically pad WCETs and thereby enabling VISA-style speculation even in highly-utilized systems. (via Semantic Scholar)
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Source: Web Of Science
Added: August 6, 2018

2005 conference paper

Virtual multiprocessor: An analyzable, high-performance microarchitecture for real-time computing

CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 24-27, 2005, San Francisco, California, USA, 213–224.

By: A. El-Haj-Mahmoud n, A. Al-Zawawi n, A. Anantaraman n & E. Rotenberg n

TL;DR: The novel Real-time Virtual Multiprocessor (RVMP) successfully combines the analyzability of multiple processors with the flexibility of simultaneous multithreading (SMT) to provide a real-time formalism that SMT does not currently provide. (via Semantic Scholar)
Source: NC State University Libraries
Added: August 6, 2018

2004 article

FAST: Frequency-aware static timing analysis

RTSS 2003: 24TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 40–51.

By: K. Seth n, A. Anantaraman n, F. Mueller n & E. Rotenberg n

TL;DR: Novel techniques for tight and flexible static timing analysis particularly well-suited for dynamic scheduling schemes are contributed, including a parametric approach towards bounding the WCET statically with respect to the frequency and an improved parametric model for improving existing DVS scheduling schemes. (via Semantic Scholar)
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Source: Web Of Science
Added: August 6, 2018

2003 conference paper

Virtual Simple Architecture (VISA): Exceeding the complexity limit in safe real-time systems

Computers and their applications :|bproceedings of the ISCA 16th International Conference, Seattle, Washington, USA, March 28-30, 2001, 350–361. Cary, NC: ISCA.

By: A. Anantaraman, K. Seth, K. Patil, E. Rotenberg & F. F. Mueller

Source: NC State University Libraries
Added: August 6, 2018

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