@article{hari_ellington_floyd_2023, title={A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz}, volume={1}, ISSN={["1558-173X"]}, DOI={10.1109/JSSC.2023.3235976}, abstractNote={A 6-to-31-GHz reflection-mode $N$ -path filter is implemented in 45-nm SOI technology. The filter includes an on-chip hybrid coupler with through and coupled ports terminated with four-phase passive mixers. Each mixer provides a high impedance in-band and a matched, 50- $\Omega $ impedance out-of-band (OOB) that is provided by the ON-resistance of the switches. As such, in-band signals are reflected by the mixers, and OOB signals are absorbed. This enables reflection-mode bandpass filtering of the signal, with the center frequency set by the local-oscillator frequency. To increase selectivity, an active baseband (BB) load with adjustable bandwidth can be enabled to provide a second-order capacitive response, which increases the roll-off to 12 dB/octave. Measurements show that the filter can be tuned across 6–31 GHz with a maximum 3-dB RF bandwidth of 0.47 GHz for the passive BB and either 0.22 or 1.22 GHz for the active BB in narrowband or wideband modes. Filter insertion loss (IL) is < 7 dB in all three modes, whereas the noise figure exceeds IL by 1 dB at 6 GHz and 11 dB at 29 GHz in the active-wide mode. The filter provides a return loss of < 10 dB both in-band and OOB. In all three modes of the filter, the in-band input-referred third-order intercept point (IIP3) is<−2.2 dBm and the OOB IIP3 is > 11 dBm, whereas the maximum in-band input-referred P1 dB is −2 dBm. Clock circuitry consumes 75–320 mW from 6 to 31 GHz, whereas the active BBs consume 70 mW in the wideband mode and 90 mW in the narrowband mode.}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Hari, Sandeep and Ellington, Cody J. and Floyd, Brian A.}, year={2023}, month={Jan} }
 @article{ellington_hari_floyd_2023, title={Analysis and Design of Baseband Circuits for Higher-Order Reflection-Mode N-Path Filters}, volume={10}, ISSN={["1558-0806"]}, DOI={10.1109/TCSI.2023.3321872}, abstractNote={A design methodology for the synthesis of baseband circuits for higher-order reflection-mode N-path filters (RMNFs) is presented. Beginning with a linear time-invariant (LTI) model, equations are formulated that provide intuition for the designer with regard to signal and noise transfer through the RMNF. Building upon the mathematical foundation of the LTI model, an interdependence between signal and noise is explored and addressed. Furthermore, two baseband synthesis approaches are presented and connected with other state-of-the-art works. Finally, a 12-18GHz RMNF design with third-order selectivity (18dB/octave) is performed with analytical, simulated, and measured hardware results to validate the presented methodology.}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Ellington, Cody J. and Hari, Sandeep and Floyd, Brian A.}, year={2023}, month={Oct} }
 @article{dean_hari_floyd_2023, title={RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback}, volume={10}, ISSN={["1558-173X"]}, DOI={10.1109/JSSC.2023.3322136}, abstractNote={This article presents multi-band direct-conversion receivers (RXs) with frequency-translated negative feedback. The forward path includes a low-noise transconductance amplifier (LNTA) followed by four-phase passive mixers that drive baseband amplifiers. A feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable, frequency-selective input matching around a wide range of local oscillator (LO) frequencies. The passive mixers are driven by 25% duty-cycle, non-overlapping quadrature LO waveforms, and two different methods are presented for generating such waveforms. Two RX variants, differing in their LO generation schemes, are fabricated in 45-nm SOI CMOS. The first operates from 6 to 30 GHz, exhibiting greater than 25-dB gain and 4.1–10.5-dB noise figure (NF). A second operates from 10 to 50 GHz, achieving greater than 18-dB gain with 7.1–17-dB NF across the band. For either version, the instantaneous bandwidth is 960 MHz for the highest gain setting and 1375 MHz with reduced gain, measured at 10 GHz LO. The in-band third-order intercept point (IIP3) is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 5.4 dBm, the in-band IIP2 is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+$</tex-math> </inline-formula> 16.5 dBm, and the out-of-band 1-dB blocker compression is greater than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 15 dBm. The RX core consumes 71 mW, while LO circuitry in each variant consumes 48–182 and 72–262 mW from 10 to 50 and 6 to 30 GHz, respectively.}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Dean, Jacob and Hari, Sandeep and Floyd, Brian A.}, year={2023}, month={Oct} }
 @article{chang_floyd_2023, title={Reduction of Phase and Gain Control Dependencies Within a 20 GHz Beamforming Receiver IC}, volume={11}, ISSN={["2169-3536"]}, DOI={10.1109/ACCESS.2023.3280475}, abstractNote={This paper studies the phase and gain control dependencies of a variable gain amplifier (VGA) and a vector interpolator phase shifter (VIPS) within a 20 GHz beamforming receiver. First, the mechanisms of gain control and phase variation in a classic current-steering VGA are analyzed and design techniques are proposed such that the gain-dependent phase variations (GDPV) introduced by the amplifiers are well balanced. Second, similar analysis is performed to evaluate GDPV within a vector interpolator, where we show how the same techniques only partially apply due to the cross-coupling structure of the interpolator’s VGAs. We evaluate our techniques within a 20 GHz beamforming receiver IC realized in GlobalFoundries 45 nm RFSOI. Very low GDPV is observed within the VGA, with less than 0.3-deg. root-mean squared phase variation for a 9 dB gain control, whereas the VIPS achieves worst-case GDPV of 14 deg. The full beamformer channel achieves 29 dB gain, 2.2-2.4 dB noise figure, −26 dBm input 1 dB compression and consumes 111 mW. Based on these results, improvements to the interpolator are proposed and validated through simulation. The result is a near-ideal Cartesian interpolator that has less than 2-deg. GDPV and very low crosstalk between the VGAs.}, journal={IEEE ACCESS}, author={Chang, Yuan and Floyd, Brian A.}, year={2023}, pages={68066–68078} }
 @article{samal_dutta_guvenc_sichitiu_floyd_zajkowski_2022, title={Automating Operator Oversight in an Autonomous, Regulated, Safety-Critical Research Facility}, ISSN={["1095-2055"]}, DOI={10.1109/ICCCN54977.2022.9868858}, abstractNote={The deployment at scale of Unmanned Aerial Systems have become increasingly imminent in the last few years, even as concerns regarding the dependability and predictability of their command and control channels remain fully to be addressed. The intersection of ground-to-air wireless communications, aerial networking, and trajectory control has become a research area of sharp interest. The validation of such research, beyond the theoretical/simulation stage, requires a facility that is both realistic, and admits of potentially risky or unsafe operation, while in the end guaranteeing personnel and equipment safety. The AERPAW project is an ambitious project, funded by the PAWR program of the US NSF, to create a remote accessible research platform for a research facility to enable such validation. To enable remote usage of such a testbed, yet provide the researcher with complete experimental freedom, the AERPAW facility includes a combination of architectural mechanisms that balance freedom of experimentation with regulatory compliance and safety. In this paper, we articulate the challenges and considerations of designing such mechanisms, and present the architectural features of AERPAW that attempt to realize these lofty goals.}, journal={2022 31ST INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN 2022)}, author={Samal, Tripti and Dutta, Rudra and Guvenc, Ismail and Sichitiu, Mihail L. and Floyd, Brian and Zajkowski, Thomas}, year={2022} }
 @article{hong_floyd_2022, title={Beamformer Calibration Using Coded Correlations}, ISSN={["1554-8422"]}, DOI={10.1109/PAST49659.2022.9975099}, abstractNote={Code-modulated embedded test (CoMET) has been investigated for simultaneous testing and calibration of phased-array elements using phase-shifter modulation and a single scalar detector together with an off-line equation solver. To improve the speed and reduce the complexity of the calibration, this work presents a revised methodology relying only on correlations and eliminating equation solvers within the calibration loop. The new technique, “beamformer calibration using coded correlations” (BC3), operates by calibrating the phased-array's in-phase and quadrature-phase correlations between elements. Within BC3, a first method calibrates the array's response by using two two-dimensional (2-D) correlations. A second method further reduces the total calibration time and improves accuracy by using two one-dimensional (1-D) correlations together with an empirical model to predict gain-dependent phase variation. Also, we investigate ways to improve the speed of calibration by reducing the code length and the number of searching states per iteration. The phase and gain accuracy, calibration time, and antenna beam patterns are measured and compared using original and proposed calibration methods on an eight-element receiver at 10 GHz. The most accurate BC3 method achieves 1.4 deg. and 0.23 dB root-mean-squared (RMS) phase and gain error, 1.1 dB maximum gain error and -37.8 dB calculated residual sidelobe level (RSL) for the calibrated array, with 12X speedup compared to CoMET. The fastest BC3 method achieves 2.1 deg. and 0.27 dB root-mean-squared (RMS) phase and gain error, 1.2 dB maximum gain error and -35.3 dB RSL for the array with 33X speedup compared to CoMET.}, journal={2022 IEEE INTERNATIONAL SYMPOSIUM ON PHASED ARRAY SYSTEMS & TECHNOLOGY (PAST)}, author={Hong, Zhangjie and Floyd, Brian A.}, year={2022} }
 @article{wen_dean_floyd_franzon_2022, title={High Dimensional Optimization for Electronic Design}, DOI={10.1145/3551901.3556495}, abstractNote={Bayesian optimization (BO) samples points of interest to update a surrogate model for a blackbox function. This makes it a powerful technique to optimize electronic designs which have unknown objective functions and demand high computational cost of simulation. Unfortunately, Bayesian optimization suffers from scalability issues, e.g., it can perform well in problems up to 20 dimensions. This paper addresses the curse of dimensionality and proposes an algorithm entitled Inspection-based Combo Random Embedding Bayesian Optimization (IC-REMBO). IC-REMBO improves the effectiveness and efficiency of the Random EMbedding Bayesian Optimization (REMBO) approach, which is a state-of-the-art high dimensional optimization method. Generally, it inspects the space near local optima to explore more points near local optima, so that it mitigates the over-exploration on boundaries and embedding distortion in REMBO. Consequently, it helps escape from local optima and provides a family of feasible solutions when inspecting near global optimum within a limited number of iterations.The effectiveness and efficiency of the proposed algorithm are compared with the state-of-the-art REMBO when optimizing a mmWave receiver with 38 calibration parameters to meet 4 objectives. The optimization results are close to that of a human expert. To the best of our knowledge, this is the first time applying REMBO or inspection method to electronic design.}, journal={MLCAD '22: PROCEEDINGS OF THE 2022 ACM/IEEE 4TH WORKSHOP ON MACHINE LEARNING FOR CAD (MLCAD)}, author={Wen, Yuejiang and Dean, Jacob and Floyd, Brian A. and Franzon, Paul D.}, year={2022}, pages={153–157} }
 @article{maeng_guvenc_sichitiu_floyd_dutta_zajkowski_ozdemir_mushi_2022, title={National Radio Dynamic Zone Concept with Autonomous Aerial and Ground Spectrum Sensors}, ISSN={["2164-7038"]}, DOI={10.1109/ICCWORKSHOPS53468.2022.9814648}, abstractNote={National radio dynamic zone (NRDZs) are intended to be geographically bounded areas within which controlled experiments can be carried out while protecting the nearby licensed users of the spectrum. An NRDZ will facilitate research and development of new spectrum technologies, waveforms, and protocols, in typical outdoor operational environments of such technologies. In this paper, we introduce and describe an NRDZ concept that relies on a combination of autonomous aerial and ground sensor nodes for spectrum sensing and radio environment monitoring (REM). We elaborate on key characteristics and features of an NRDZ to enable advanced wireless experimentation while also coexisting with licensed users. Some preliminary results based on simulation and experimental evaluations are also provided on out-of-zone leakage monitoring and real-time REMs.}, journal={2022 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS WORKSHOPS (ICC WORKSHOPS)}, author={Maeng, S. J. and Guvenc, I and Sichitiu, M. L. and Floyd, B. and Dutta, R. and Zajkowski, T. and Ozdemir, O. and Mushi, M.}, year={2022}, pages={687–692} }
 @article{almahmoud_hong_floyd_2022, title={Simultaneous Phased-Array Element Testing Using Orthogonal Amplitude Modulation}, ISSN={["1554-8422"]}, DOI={10.1109/PAST49659.2022.9975103}, abstractNote={This work introduces an orthogonal amplitude modulation (AM) technique for simultaneous measurement of phased-array elements. The approach leverages a code-modulated embedded test (CoMET) technique in which a test signal is injected to the array, on-off keying is applied to each element using the existing variable-gain amplifiers and vector interpolators, signals are combined and then squared using a power detector, correlations are demodulated from the squared response, and then amplitude and phase are estimated using an equation solver. The amplitude modulation technique can be used in systems where phase modulation is either difficult or erroneous. This paper presents the theory for AM-CoMET and demonstrates its operation using an eight-element phased array transmitter operating at 8 GHz. The extracted gain and phase from the new technique are compared with a vector network analyzer (VNA), showing that AM-CoMET extracted gain and phase are accurate to within 0.25 dB gain error and 2° phase error.}, journal={2022 IEEE INTERNATIONAL SYMPOSIUM ON PHASED ARRAY SYSTEMS & TECHNOLOGY (PAST)}, author={Almahmoud, Saleh and Hong, Zhangjie and Floyd, Brian A.}, year={2022} }
 @article{mushi_joshi_dutta_guvenc_sichitiu_floyd_zajkowski_2022, title={The AERPAW Experiment Workflow - Considerations for Designing Usage Models for a Computing-supported Physical Research Platform}, ISSN={["2159-4228"]}, DOI={10.1109/INFOCOMWKSHPS54753.2022.9798061}, abstractNote={The AERPAW project is an ambitious project, funded by the PAWR program of the US NSF, to create a remote accessible research platform for a research facility with some distinct features that makes its usage model unique, and non-obvious to many researchers desirous of making use of this platform. AERPAW is primarily a physical resource (not a computing or cyber-resource) - the RF enviroment, and the airspace. Experimenters can explore them through radio transceivers and Unmanned Aerial Vehicles, both under the Experimenter’s programmatic control. Since the entire workflow of the user is through the mediation of virtual computing environments, users often tend to think of AERPAW as a computing resource, and find some of the experiment workflow counter-intuitive. In this paper, we articulate the challenges and considerations of designing an experiment workflow that balances the need for guaranteeing safe testbed operation, and providing flexible programmatic access to this unique resource.}, journal={IEEE INFOCOM 2022 - IEEE CONFERENCE ON COMPUTER COMMUNICATIONS WORKSHOPS (INFOCOM WKSHPS)}, author={Mushi, Magreth and Joshi, Harshvardhan P. and Dutta, Rudra and Guvenc, Ismail and Sichitiu, Mihail L. and Floyd, Brian and Zajkowski, Thomas}, year={2022} }
 @article{yeh_wang_floyd_2021, title={75-86-GHz Signal Generation Using a Phase-Controlled Quadrature-Push Quadrupler Driven by a QVCO or a Tunable Polyphase Filter}, volume={69}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85112660002&partnerID=MN8TOARS}, DOI={10.1109/TMTT.2021.3097711}, abstractNote={This article demonstrates a $W$ -band local-oscillator generation technique in 120-nm SiGe BiCMOS technology with high output power and high efficiency. The circuit employs a frequency quadrupler that is driven with differential quadrature inputs that are provided by either a quadrature voltage-controlled oscillator (QVCO) or a tunable active polyphase filter (PPF) circuit. The quadrupler employs a phase-controlled quadrature-push (PCQP) topology using stacked devices with a lower class-C common-emitter (CE) amplifier generating a current that is then modulated by an upper common-base (CB) amplifier driven out-of-phase with the lower devices. Such a structure generates a strong fourth-order harmonic. Four such stacks driven at their input using accurate differential quadrature signals increase the fourth-harmonic output power while suppressing other harmonics. The differential quadrature signals for the quadrupler are provided using either a PPF circuit or a capacitive injection-locking QVCO, which achieves wide tuning range and low phase noise. Both approaches are evaluated through the measurement of separate test circuits. The LO circuit using the QVCO provides 8–11.5-dBm output power over 75.2–83 GHz, power efficiency of 2.2–4.1%, including QVCO and buffer power, >20-dB harmonic rejection in the lower frequency range, and >14.4-dB harmonic rejection in the upper frequency range. The LO circuit using the active PPF provides 8.4–11.2-dBm output power over 75.6–82.8 GHz, power efficiency of 2.4–4.8%, including PPF and buffer power, and >23-dB harmonic rejection.}, number={10}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Yeh, Yi-Shin and Wang, Weihu and Floyd, Brian A.}, year={2021}, month={Oct}, pages={4521–4532} }
 @article{dean_hari_bhat_floyd_2021, title={A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback}, ISSN={["1930-8833"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85118428066&partnerID=MN8TOARS}, DOI={10.1109/ESSCIRC53450.2021.9567779}, abstractNote={This paper presents a multi-band direct-conversion receiver with frequency-translated feedback. The forward path includes a low-noise transconductance amplifier followed by four-phase passive mixers which drive baseband amplifiers, and the feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable frequency-selective input matching. The receiver operates from 4–31 GHz exhibiting greater than 25 dB gain through 22 GHz and greater than 17 dB gain through 31 GHz. Noise figure is 5.2 to 9.8 dB, rising with frequency; input-referred 1-dB compression point is -17 dBm; and in-band IIP3 is -6.6 dBm. Out-of-band 1-dB blocker compression is greater than -12 dBm. The receiver core consumes 91 mW, whereas an integrated 2:1 frequency divider and pass-gate buffer for generating non-overlapping four-phase clocks consumes an additional 87–227 mW from 4–31 GHz, respectively.}, journal={ESSCIRC 2021 - IEEE 47TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE (ESSCIRC)}, author={Dean, Jacob and Hari, Sandeep and Bhat, Avinash and Floyd, Brian A.}, year={2021}, pages={187–190} }
 @inproceedings{hari_ellington_floyd_2021, title={A 6-31 GHz tunable reflection-mode N-path filter}, volume={2021-June}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85111721713&partnerID=MN8TOARS}, DOI={10.1109/RFIC51843.2021.9490492}, abstractNote={A 6-31 GHz reflection-mode N-path filter is implemented in 45 nm SOI technology. The filter is comprised of an on-chip hybrid coupler with through and coupled ports terminated with four-phase passive mixers. Each mixer provides a high impedance in-band and a 50-ohm impedance out-of-band, enabling reflection-mode bandpass filtering of the signal, with the center frequency set by the local-oscillator frequency. To increase selectivity, an active baseband load with adjustable bandwidth can be enabled to increase the roll-off to 12 dB/octave. The baseband loads between the two N-path mixers are shared to reduce size and power with the added benefit of creating a non-reciprocal filter response. Measurements show the filter can be tuned across 6–31 GHz with insertion loss <7 dB, typical return loss >10 dB, noise figure exceeding insertion loss by 1 dB at 6 GHz and 10 dB at 31 GHz, and in-band IIP3 of 1.4-6.3 dBm.}, booktitle={Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium}, author={Hari, S. and Ellington, C.J. and Floyd, B.A.}, year={2021}, pages={143–146} }
 @article{chowdhury_anjinappa_guvenc_sichitiu_ozdemir_bhattacherjee_dutta_marojevic_floyd_2021, title={A Taxonomy and Survey on Experimentation Scenarios for Aerial Advanced Wireless Testbed Platforms}, volume={2021-March}, ISSN={["1095-323X"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85111405299&partnerID=MN8TOARS}, DOI={10.1109/AERO50100.2021.9438449}, abstractNote={There are various works in the recent literature on fundamental research and experimentation on unmanned aerial vehicle (UAV) communications. On the other hand, to our best knowledge, there is no taxonomy and survey on experimentation possibilities with a software-defined aerial wireless platform. The goal of this paper is first to have a brief overview of large-scale advanced wireless experimentation platforms broadly available to the wireless research community, including also the Aerial Experimentation and Research Platform for Advanced Wireless (AERPAW). We then provide a detailed taxonomy and a comprehensive survey of experimentation possibilities that can be carried out in a platform such as AERPAW. In particular, we conceptualize and present eleven different classes of advanced and aerial wireless experiments, provide several example experiments for each class, and discuss some of the existing related works in the literature. The paper will help to develop a better understanding of the equipment and software resources that can be available for experimentation in mid-scale wireless platforms, as well as the capabilities and limitations of such platforms.}, journal={2021 IEEE AEROSPACE CONFERENCE (AEROCONF 2021)}, author={Chowdhury, Md Moin Uddin and Anjinappa, Chethan K. and Guvenc, Ismail and Sichitiu, Mihail and Ozdemir, Ozgur and Bhattacherjee, Udita and Dutta, Rudra and Marojevic, Vuk and Floyd, Brian}, year={2021} }
 @article{panicker_ozdemir_sichitiu_guvenc_dutta_marojevic_floyd_2021, title={AERPAW emulation overview and preliminary performance evaluation}, volume={194}, ISSN={["1872-7069"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85105348139&partnerID=MN8TOARS}, DOI={10.1016/j.comnet.2021.108083}, abstractNote={The Aerial Experimentation and Research Platform for Advanced Wireless (AERPAW) has been recently funded by the National Science Foundation (NSF)'s Platforms for Advanced Wireless Research (PAWR) program. The AERPAW platform will enable experiments with programmable radios and programmable unmanned aerial vehicles (UAVs), conducted in a safe and repeatable manner. Several architectural components are crucial for enabling the envisioned capabilities of the testbed. In this paper, after providing a high level overview of AERPAW, we first present the emulation design of AERPAW vehicles. Subsequently, we describe various different options for wireless channel emulation in AERPAW. We start with a generalized model for wireless emulation, and expand that model to packet-level emulation, I-Q level emulation, and radio-frequency (RF)-level emulation. A discussion on the trade-offs among these various different emulation possibilities is also provided.}, journal={COMPUTER NETWORKS}, publisher={Elsevier BV}, author={Panicker, Ashwin and Ozdemir, Ozgur and Sichitiu, Mihail L. and Guvenc, Ismail and Dutta, Rudra and Marojevic, Vuk and Floyd, Brian}, year={2021}, month={Jul} }
 @article{chauhan_hong_schoenherr_floyd_2021, title={An X-Band Code-Modulated Interferometric Imager}, volume={69}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85118883233&partnerID=MN8TOARS}, DOI={10.1109/TMTT.2021.3101243}, abstractNote={Code-modulated interferometry (CMI) enables a lens-less approach to imaging in which incoming signals are code modulated, combined, and processed through a shared hardware path; visibility functions are demodulated from an aggregate power-detected response; and an image is obtained using an inverse Fourier transform of the visibility samples. CMI allows the imager to be constructed using low-cost conventional beamforming hardware. This article presents the theory of operation of a code-modulated interferometer array intended for active imaging. This includes the selection of codes, the use of phase shifters for modulation, the demodulation of visibility functions, the necessary calibration, and the image processing. The architecture and design of an active imaging prototype is then presented, where it is created using a commercially available 16-element 8–16 GHz beamforming receiver along with a sparse antenna array that generates 169 distinct visibility samples. The imaging capabilities are demonstrated through the detection of multiple point sources at 10 GHz. Finally, the feasibility of creating a larger 64-element imager with 961 visibility samples is demonstrated through construction and measurements of a single row within that array.}, number={11}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Chauhan, Vikas and Hong, Zhangjie and Schoenherr, Simon and Floyd, Brian A.}, year={2021}, month={Nov}, pages={4856–4868} }
 @article{hong_schönherr_chauhan_floyd_2021, title={Board-level code-modulated embedded test and calibration of an X-band phased-array transceiver}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85111040784&partnerID=MN8TOARS}, journal={arXiv}, author={Hong, Z. and Schönherr, S. and Chauhan, V. and Floyd, B.}, year={2021} }
 @article{hong_chauhan_schoenherr_floyd_2021, title={Code-Modulated Embedded Test and Calibration of Phased-Array Transceivers}, volume={69}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85097946951&partnerID=MN8TOARS}, DOI={10.1109/TMTT.2020.3041022}, abstractNote={We present improved methods for built-in test and calibration of phased arrays in free-space using a code-modulated embedded test (CoMET). Our approach employs the Cartesian modulation of test signals within each element using existing phase shifters, the combination of these signals into a code-multiplexed response, creation of code-modulated element-to-element “interference products” using a built-in power detector, demodulation of correlations from the digitized interference response, and parallel in situ extraction of amplitude and phase per element using an equation solver. In this article, we review CoMET’s methodology and then analyze the impact of noise within the system. To improve CoMET accuracy, a reference-element methodology is introduced, where all measurements are referred to as one element in the array whose phase is held constant. This is compared with another method in which the modulation axes are rotated to allow accurate extraction of phase near the original 0°/90°/180°/270° axes. Our techniques are demonstrated for both receive and transmit modes using an eight-element 8–16-GHz phased-array packaged and assembled together with patch antennas. Compared with network analyzer measurements, CoMET-extracted gain and phase using the reference-element method are accurate to within 0.4 dB and 2°–3° for free-space measurements, respectively. CoMET is then used within a calibration loop to equalize elemental gain and achieve a 7-bit phase resolution. In free space, the maximum gain and phase offsets between active antenna elements are reduced from 3.5 dB and 20°–90° to 1.1 dB and 0°, respectively. Calibrated beam patterns show significant improvement with peak-to-null ratios of >30 dB.}, number={3}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hong, Zhangjie and Chauhan, Vikas and Schoenherr, Simon and Floyd, Brian A.}, year={2021}, month={Mar}, pages={1846–1859} }
 @article{floyd_shana'a_lie_2021, title={The Hybrid 2021 RFIC Symposium}, volume={22}, ISSN={["1557-9581"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85103966294&partnerID=MN8TOARS}, DOI={10.1109/MMM.2021.3056988}, abstractNote={Describes the above-named upcoming conference event. May include topics to be covered or calls for papers.}, number={5}, journal={IEEE MICROWAVE MAGAZINE}, author={Floyd, Brian and Shana'a, Osama and Lie, Donald Y. C.}, year={2021}, month={May}, pages={72–75} }
 @article{khalil_floyd_shana'a_2020, title={2020 RFIC Symposium}, volume={21}, ISSN={["1557-9581"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85083048661&partnerID=MN8TOARS}, DOI={10.1109/MMM.2020.2971371}, abstractNote={Presents information on the RFIC 2020 Conference.}, number={5}, journal={IEEE MICROWAVE MAGAZINE}, author={Khalil, Waleed and Floyd, Brian and Shana'a, Osama}, year={2020}, month={May}, pages={30–32} }
 @article{ren_hari_floyd_2020, title={A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85104680228&partnerID=MN8TOARS}, DOI={10.1109/BCICTS48439.2020.9392967}, abstractNote={This paper presents a 20–33 GHz direct-conversion transmitter implemented in 45-nm RFSOI CMOS technology. The transmitter features a divider-based quadrature clock generation circuit, two current-combined double-balanced mixers, and a balanced power amplifier (PA) employing stacked FETs. The transmitter chip achieves 19.1 to 22.4 dB of conversion gain with saturated output power of 16.7 to 20.4 dBm over 20 to 33 GHz at the differential output. Image rejection and carrier suppression are more than 29 dB and 36 dB after calibration. At a carrier frequency of 28 GHz, the transmitter chip achieves an error vector magnitude (EVM) of 5.1 % with 12 Gbps using 64-QAM.}, journal={2020 IEEE BICMOS AND COMPOUND SEMICONDUCTOR INTEGRATED CIRCUITS AND TECHNOLOGY SYMPOSIUM (BCICTS)}, author={Ren, Tiantong and Hari, Sandeep and Floyd, Brian A.}, year={2020} }
 @inproceedings{chauhan_seo_greene_kam_floyd_2020, title={A 60 GHz Code-modulated interferometric imaging system using a phased array}, volume={11411}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85086991088&partnerID=MN8TOARS}, DOI={10.1117/12.2565589}, abstractNote={This paper presents a millimeter-wave code-modulated interferometric imaging system, which is a lens-less approach to realizing imagers using repurposed phased arrays. To use a phased array as an interferometer, incoming signals are code modulated using phase shifters, multiplexed using a power combiner, and processed through a shared receiver chain. An interference pattern is then obtained by a squaring operation, from which complex visibilities can be demodulated. Here, a four-element 60-GHz phased array chip is packaged with slot antennas, and a single 60-GHz output is measured using a power detector. This scalar measurement is then demodulated to obtain the interferometric visibilities. The four-element phased array is thinned to obtain a 13-pixel image and the system is demonstrated through a point-source detected at different locations.}, booktitle={Proceedings of SPIE - The International Society for Optical Engineering}, publisher={SPIE}, author={Chauhan, V. and Seo, H. and Greene, K. and Kam, D.G. and Floyd, B.}, editor={Robertson, Duncan A. and Wikner, David A.Editors}, year={2020} }
 @inproceedings{sichitiu_guvenc_dutta_marojevic_floyd_2020, title={AERPAW Emulation Overview}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85093361697&partnerID=MN8TOARS}, DOI={10.1145/3411276.3412188}, abstractNote={The Aerial Experimentation and Research Platform for Advanced Wireless (AERPAW) has been recently funded by the National Science Foundation (NSF)'s Platforms for Advanced Wireless Research (PAWR) program. The AERPAW platform will enable experiments with programmable radios and programmable unmanned aerial vehicles (UAVs), conducted in a safe and repeatable manner. Several architectural components are crucial for enabling the envisioned capabilities of the testbed. In this paper, after providing a high level overview of AERPAW, we first present the emulation design of AERPAW vehicles. Subsequently, we describe various different options for wireless channel emulation in AERPAW. We start with a generalized model for wireless emulation, and expand that model to packet-level emulation, I-Q level emulation, and radio-frequency (RF)-level emulation. A discussion on the trade-offs among these various different emulation possibilities is also provided.}, booktitle={WiNTECH 2020 - Proceedings of the 14th ACM Workshop on Wireless Network Testbeds, Experimental evaluation and CHaracterization, Part of ACM MobiCom 2020}, author={Sichitiu, M.L. and Guvenc, I. and Dutta, R. and Marojevic, V. and Floyd, B.}, year={2020}, pages={1–8} }
 @article{marojevic_guvenc_dutta_sichitiu_floyd_2020, title={Advanced Wireless for Unmanned Aerial Systems: 5G Standardization, Research Challenges, and AERPAW Architecture}, volume={15}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85083012374&partnerID=MN8TOARS}, DOI={10.1109/MVT.2020.2979494}, abstractNote={The 5G mobile communications systems merge traditionally separate communications and networking systems and services to effectively support a myriad of heterogeneous applications. Researchers and industry working groups are investigating the integration of aerial nodes, shared spectrum techniques, and new network architectures, which are gradually being introduced into standards. This article discusses relevant standardization efforts for the integration of unmanned aerial systems (UASs) into 5G and the requirements for an aerial wireless testbed. We introduce the aerial experimentation and research platform for advanced wireless (AERPAW) and, specifically, its architecture, which is designed for enabling experimental research in controlled yet production-like environments. Sample research projects and trials show the critical R&D needs, broad scope, and impact that such a platform can have on technology evolution, regulation, and standardization as well as future services.}, number={2}, journal={IEEE Vehicular Technology Magazine}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Marojevic, Vuk and Guvenc, Ismail and Dutta, Rudra and Sichitiu, Mihail L. and Floyd, Brian A.}, year={2020}, pages={22–30} }
 @article{wilson_dean_floyd_2020, title={Mixer-First MIMO Receiver with Reconfigurable Multi-Port Decoupling and Matching}, volume={55}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85083916933&partnerID=MN8TOARS}, DOI={10.1109/JSSC.2020.2967552}, abstractNote={This article presents architectures to realize mutual impedance tuning for N-path mixer-first multiple-input multiple-output (MIMO) receivers. A coupled response at baseband is upconverted to radio frequency to realize the tunable mutual impedance. This enables the dynamic decoupling of coupled-antenna systems. The impedance of a multi-port receiver is analyzed and shown to be able to provide a wideband tunable and broadband coupled response with an array of RC baseband networks. A two-port mixer-first MIMO receiver is realized in a 45-nm silicon on insulator (SOI) CMOS and includes polyphase baseband resistive-coupling networks. The two receivers consume 16 mW and operate over 0.1–3 GHz. Each receiver achieves 3–6-dB noise figure and 14–40-dB conversion gain. The MIMO system with $N$ -path decoupling was measured with two cases: two monopole antennas and a two-port single-aperture antenna. Signal-to-noise ratio was increased by 7 and 5.2 dB, respectively.}, number={5}, journal={IEEE Journal of Solid-State Circuits}, author={Wilson, C. and Dean, J. and Floyd, B.A.}, year={2020}, pages={1401–1410} }
 @article{yeh_floyd_2020, title={Multibeam Phased-Arrays Using Dual-Vector Distributed Beamforming: Architecture Overview and 28 GHz Transceiver Prototypes}, volume={67}, ISSN={["1558-0806"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85097341095&partnerID=MN8TOARS}, DOI={10.1109/TCSI.2020.3026624}, abstractNote={This article presents a dual-vector distributed beamformer architecture that employs a series-feed network and is capable of supporting up to four simultaneous beams. The multibeam array uses scalar functions within each front end to create Cartesian-weighted signals needed for phase shifting. A dual-vector series-feed network combines/distributes these signals for the receiver/transmitter whereas a global quadrature interpolator is used to create two conjugate beams. By using an interpolator on either end of the series feed, a total of four beams can be obtained. Among these four beams, a first beam can be controlled independently, a second beam is formed as an image of the first, a third beam is offset from the first based on the amount of phase shift within the series-feed structure, and a fourth beam is an image of the offset beam. In this work, the theory of operation of the series-feed DVDB is presented and then two different four-element 28 GHz DVDB transceiver array prototypes in 120 nm SiGe BiCMOS technology are described. One uses a hybrid coupler for global interpolation at radio frequency (RF) and the other uses quadrature mixers for global interpolation at baseband. Measurement results for the array employing passive interpolation at RF show excellent phase-shifting performance, including < 1 dB root-mean-squared (RMS) gain error, < 2 degree RMS phase error, 24% 3 dB bandwidth, with 16–18.6 dBm saturated output power in transmit mode and 4.9–7.3 dB noise figure in receive mode. Measurement results for the array employing mixer-based interpolation likewise show excellent phase-shifting performance with similar RMS gain and phase errors and slightly degraded overall RF performance. Comparing the two, we conclude that the DVDB with passive interpolation at RF is better suited for partitioned systems where beamformers and transceivers are realized on separate chips to support larger, scalable arrays. In contrast, the DVDB with mixer-based interpolation is better suited for integrated systems where beamformers and frequency translation functions must be integrated together.}, number={12}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Yeh, Yi-Shin and Floyd, Brian A.}, year={2020}, month={Dec}, pages={5496–5509} }
 @article{bonner-stewart_wilson_floyd_2020, title={Tunable 0.7-2.8-GHz Reflection-Mode N-Path Filters in 45-nm SOI CMOS}, volume={68}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85086269923&partnerID=MN8TOARS}, DOI={10.1109/TMTT.2020.2971489}, abstractNote={This article presents the principles of operation of a reflection-mode $N$ -path filter and then discusses both single-balanced and double-balanced implementations. The single-balanced approach can be used to realize tunable filters with extremely low insertion loss; however, the circuit also exhibits harmonic responses. The double-balanced reflector naturally rejects even-order harmonics and can be modified to cancel the third harmonics as well to provide a tunable $N$ -path filter with the second through fourth harmonics rejected. This comes at the expense of increased insertion loss to support the required balun circuitry used to balance the mixers. Prototypes for both types of filters have been realized in the 45-nm SOI CMOS technology. Measurements on the single-balanced reflection-mode filter indicate 0.8–2.4-dB insertion loss across a 700–3000-MHz tuning range. The input-referred 1-dB compression point is 0 dBm and the input-referred third-order intercept point (IIP3) is +10-dBm in-band and +22-dBm out-of-band (OOB), and the circuit consumes 2.5–7.2 mW of power. Measurements on the double-balanced reflection-mode filter indicate 1.9–4.4-dB insertion loss across a 700–2800-MHz tuning range. The input-referred 1-dB compression point is +0.75 dBm, and IIP3 is >+16.3-dBm in-band and >+19.5-dBm OOB, and the circuit consumes a total of 4.0–15.6 mW of power.}, number={6}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Bonner-Stewart, Jeffrey and Wilson, Charley, III and Floyd, Brian A.}, year={2020}, month={Jun}, pages={2343–2357} }
 @inproceedings{khalil_floyd_shana’a_2020, title={Welcome Message from Chairs}, volume={2020-August}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85093967309&partnerID=MN8TOARS}, DOI={10.1109/RFIC49505.2020.9218358}, abstractNote={We invite you to join us in the 2020 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, to be held as a virtual symposium beginning on 4 August 2020.The RFIC Symposium is the premier IC conference focused exclusively on the latest advances in RF, mm-wave and high-frequency analog/ mixed-signal IC technologies and designs.The Symposium, combined with the International Microwave Symposium (IMS), ARFTG, and the Industry Exhibition, form "Microwave Week", the largest worldwide RF/microwave technical meeting of the year.While we are regrettably unable to gather in person due to the COVID-19 pandemic, the RFIC and our IMS and ARFTG partners, with support from our organizers and sponsors, have worked tirelessly to build a world-class virtual platform through which we hope to provide a rewarding and engaging experience.A single registration will allow attendees to access all Microwave Week content, including RFIC, IMS, ARFTG, the 5G Summit, a virtual exhibition, panel sessions, and more.This registration is free to all members of the IEEE Microwave Theory and Technique Society (MTTS).All Microwave Week content will be available on-line beginning on 4 August 2020 and lasting through 30 September 2020.The 2020 RFIC Symposium will begin on Tuesday, 4 August 2020, with the RFIC Plenary Session.This session will be streamed live, beginning at 16:00 PDT, and will then be made available afterwards on demand.The Session will feature two visionary talks by our distinguished plenary speakers.}, booktitle={Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium}, author={Khalil, W. and Floyd, B. and Shana’a, O.}, year={2020}, pages={i-ii} }
 @article{pellerano_khalil_floyd_2019, title={2019 RFIC Symposium}, volume={20}, ISSN={["1557-9581"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85062714467&partnerID=MN8TOARS}, DOI={10.1109/MMM.2019.2891858}, abstractNote={April 2019 The 2019 IEEE RFIC Symposium will be held in Boston, Massachusetts, 2–4 June 2019. RFIC is the premier IC design conference focused exclusively on the latest advances in RF, microwave, and millimeter-wave (mm-wave) IC technologies and designs as well as innovations in highfrequency analog/mixed-signal ICs. In 2019, the conference will also expand its focus to emerging circuit technologies related to RFIC, such as RF circuits and systems that incorporate microelectromechanical system sensors and actuators, heterogeneous and 3D ICs, silicon photonics, quantum computing ICs, hardware security and machine-learning applications, wearable and implantable systems, biomedical applications, and autonomous systems, such as automotive and drones. We cordially invite you to participate in this international symposium. For 2019, RFIC is promoting a new educational experience for attendees: a technical lecture, a 1.5-h interactive short course delivered by a distinguished speaker during lunchtime on Sunday, between the morning and afternoon workshop sessions. For 2019, Prof. Ali Niknejad from the University of California, Berkeley, will present “Fundamentals of mm-Wave IC Design in CMOS.” Don’t forget to register in advance because we expect a very high attendance, and seats will be limited to the first 250 participants! To encourage student attendance, the IEEE Microwave Theory and Techniques Society 2019 International Microwave Symposium (IMS2019) is offering deep registration discounts and numerous benefits for student volunteers who are IEEE Me m b er s a nd w i l l i ng to he lp with conference activities. For more details, visit https://ims-ieee.org/ Digital Object Identifier 10.1109/MMM.2019.2891858 Date of publication: 7 March 2019 Stefano Pellerano (stefano.pellerano@intel .com), RFIC 2019 General Chair, is with Intel, Hillsboro, Oregon, United States. Waleed Khalil (khalil@ece.osu.edu), RFIC 2019 Technical Program Chair, is with The Ohio State University, Columbus, United States. Brian Floyd (bafloyd@ncsu.edu), RFIC 2019 Technical Program Cochair, is with North Carolina State University, Raleigh, United States. 2019 RFIC Symposium}, number={4}, journal={IEEE MICROWAVE MAGAZINE}, author={Pellerano, Stefano and Khalil, Waleed and Floyd, Brian}, year={2019}, month={Apr}, pages={68-+} }
 @inproceedings{chauhan_schonherr_hong_floyd_2019, title={A 10-GHz Code-Modulated Interferometric Imager Using Commercial-Off-The-Shelf Phased Arrays}, volume={2019-June}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85069962256&partnerID=MN8TOARS}, DOI={10.1109/mwsym.2019.8700850}, abstractNote={Code-modulated interferometric imaging is a lens-less approach to imaging in which existing analog phased-arrays are repurposed as an interferometer using code modulation. A 33-pixel, eight-element prototype is created using two commercially-available ADAR1000 phased-array receivers from Analog Devices Inc. The chips are connected at board level to a patch antenna array. The serial interface is used to apply codes whereas the on-chip power detector and data converter are used for direct read out of the composite code-multiplexed imaging data. These are then processed off-line in Matlab to reconstruct the image. The 33-pixel camera is demonstrated in hardware for point-source detection.}, booktitle={IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Chauhan, V. and Schonherr, S. and Hong, Z. and Floyd, B.}, year={2019}, pages={1015–1018} }
 @inproceedings{ren_floyd_2019, title={A 21 to 31 GHz Multi-Stage Stacked SOI Power Amplifier with 33% PAE and 18 dBm Output Power}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85091891435&partnerID=MN8TOARS}, DOI={10.1109/IMC-5G47857.2019.9160355}, abstractNote={This paper presents a compact two-stage K/Ka-band power amplifier (PA) implemented i n GlobalFoundries 4SRFSOI CMOS technology for fifth-generation (5G) millimeterwave phased arrays. The PA features a linear pre-driver stage with 1.6 V supply and a three-stack FET output stage with 3.6 V supply. Measurement results show that at 26 GHz, the PA achieves a peak gain of 16.6 dB and a saturated output power (Psat) of 18.3 dBm with maximum power-added efficiency (PAE) of 32.8%. The 1-dB compression point (P1dB) is 16.2 dBm with PAE of 29.7%. The PA operates across 21 to 31 GHz with Psat above 17.3 dBm and gain above 13.6 dB.}, booktitle={2019 IEEE MTT-S International Microwave Conference on Hardware and Systems for 5G and Beyond, IMC-5G 2019}, author={Ren, T. and Floyd, B.A.}, year={2019} }
 @inproceedings{chang_floyd_2019, title={A Broadband Reflection-Type Phase Shifter Achieving Uniform Phase and Amplitude Response across 27 to 31 GHz}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85079211684&partnerID=MN8TOARS}, DOI={10.1109/BCICTS45179.2019.8972730}, abstractNote={This paper demonstrates a broadband reflection-type phase shifter (RTPS) for millimeter-wave phased-array applications. Implemented in 45-nm SOI CMOS, the proposed bidirectional RTPS provides a full 360 deg. phase-shift with a five-bit phase resolution. It incorporates an additional series inductor/varactor resonator to a Pi-based varactor/inductor/varactor network to broaden both the phase-shift range and bandwidth and to allow a single set of voltages to control the RTPS response over the full 27 to 31 GHz bandwidth (13.8% fractional bandwidth). A method is proposed to select these control voltages under an intended insertion-loss constraint to minimize the average root-mean squared (RMS) phase error across the entire band. Across the full band, the RTPS achieves an RMS phase error less than 3.8 deg, insertion loss of 8.5 to 10 dB, and RMS gain error less than 0.5 dB across the band.}, booktitle={2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2019}, author={Chang, Y. and Floyd, B.A.}, year={2019} }
 @inproceedings{hari_bhat_wilson_floyd_2019, title={Approaches to Nonoverlapping Clock Generation for RF to Millimeter-Wave Mixer-First Receivers}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85091897686&partnerID=MN8TOARS}, DOI={10.1109/IMC-5G47857.2019.9160353}, abstractNote={N-phase mixer-first receivers are an ideal choice for broadband frequency-selective receivers. These receivers can now operate near millimeter-wave frequencies using fast-rising four-phase clock generation in advanced CMOS. This paper compares four-phase clock-generation approaches used in two high-frequency mixer-first receivers-a polyphase filter-based scheme as part of a 20–30 GHz receiver and a divider-based scheme as part of 5–31 GHz receiver. We discuss circuits for quadrature and 25% duty-cycle generation and compare clock performance in terms of area, power, quadrature accuracy, and receiver metrics. Both receivers demonstrate typical noise figure below 8 dB and conversion gains above 18 dB.}, booktitle={2019 IEEE MTT-S International Microwave Conference on Hardware and Systems for 5G and Beyond, IMC-5G 2019}, author={Hari, S. and Bhat, A. and Wilson, C. and Floyd, B.}, year={2019} }
 @inproceedings{wang_floyd_2019, title={Comparison of 10/20/40 GHz Quadrature VCOs for W-band FMCW Radar Systems in 90nm SiGe BiCMOS Technology}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85079221318&partnerID=MN8TOARS}, DOI={10.1109/BCICTS45179.2019.8972723}, abstractNote={This paper presents and compares quadrature voltage-controlled oscillators (QVCOs) operating at 10, 20, and 40 GHz for use within W-band frequency-modulated continuous wave (FMCW) radar systems. The same circuit topology and a 90nm SiGe BiCMOS 9HP technology are used for each band. The QVCO employs Colpitts oscillators which are capacitively coupled in a ring structure. This passive coupling results in improved phase noise compared to active injection techniques. Each differential Colpitts subcircuit uses an AC-shorted transformer-coupled varactor structure to allow for wide continuous tuning range with low phase noise. Estimated quality factors of the tanks are 16/11/6 for the 10/20/40 GHz VCOs, where the higher Q is achieved through careful optimization of the transformer (with Q of ~35 for each band) and varactor structures. Our results show that the 10/20/40-GHz QVCOs achieve phase noises at 1-MHz offset of -122/-114/-105 dBc/Hz, continuous tuning ranges of 14%/10%/4%, and figures-of-merit of -181/-179/-174 dBc/Hz, respectively. After multiplication to 80 GHz, phase noises would be -104/-102/-98 dBc/Hz, respectively, indicating that the lower frequency design is preferable for the FMCW radar system, provided that high-performance multipliers are available. Keywords—Voltage-controlled oscillators, quadrature VCO, SiGe, BiCMOS, technology benchmarking, FMCW radar.}, booktitle={2019 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, BCICTS 2019}, author={Wang, W. and Floyd, B.A.}, year={2019} }
 @inproceedings{hong_schonherr_chauhan_floyd_2019, title={Free-Space Phased-Array Characterization and Calibration Using Code-Modulated Embedded Test}, volume={2019-June}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85069962278&partnerID=MN8TOARS}, DOI={10.1109/mwsym.2019.8701098}, abstractNote={A phased-array self-test technique called code-modulated embedded test (CoMET) is used for free-space characterization and calibration of phased-array transceivers packaged with antennas. Orthogonal two-bit modulation is applied to all phase shifters to allow for parallel extraction of gain and phase of array elements using a simple power detector. Our array uses two commercially-available beamformers and a patch antenna array. At 10 GHz, CoMET-extracted gain, phase, and phase offset are accurate to within 0.4 dB and 4° compared to network analyzer measurements. CoMET is then used within a calibration-loop to equalize elemental gain and phase across the array for 7-bit phase resolution. After calibration, the maximum gain and phase offsets between elements are reduced from 3.5 dB and 70° to 1.1 dB and ~0°. Free-space beam patterns after calibration show significant improvement.}, booktitle={IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Hong, Zhangjie and Schonherr, Simon and Chauhan, Vikas and Floyd, Brian}, year={2019}, pages={1225–1228} }
 @article{wilson_floyd_2019, title={Harmonic Performance of Mixer-First Receivers With Circulant-Symmetric Basebands}, volume={66}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85051814188&partnerID=MN8TOARS}, DOI={10.1109/TCSI.2018.2856257}, abstractNote={In this paper, we analyze a mixer-first receiver, which includes passive polyphase mixers, low-noise baseband amplifiers, and baseband circulant-symmetric polyphase feedback. This analysis is performed for input frequencies located around any harmonic frequency of the local oscillator. From this, circuits and methods are introduced, which allow control of the receiver’s harmonic input impedance through the use of resistive–capacitive ( $RC$ ) baseband feedback networks. We show that the harmonic input admittance of the mixer-first receiver is related to the discrete Fourier transform of the baseband circulant. This Fourier relationship allows control of the harmonic impedance response across frequencies. The noise figure of the receiver with circulant-symmetric feedback can approach that of an equivalent mixer-first receiver having harmonic feedforward cancelation without the additional power consumption of a cancelation stage. Harmonic impedance shaping can improve the blocker tolerance by decreasing the harmonic conversion gain. A single design can be reconfigured to use these techniques for fundamental-frequency or subharmonic operation. Derivations for impedance, conversion gain, and noise figure are included and a linear time-invariant circuit model is introduced. These are validated through circuit simulation using a combination of 45-nm silicon-on-insulator CMOS technology and behavioral baseband models.}, number={1}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Wilson, Charley and Floyd, Brian}, year={2019}, pages={161–174} }
 @inproceedings{chauhan_floyd_2018, title={A 24–44 GHz UWB LNA for 5G Cellular Frequency Bands}, ISBN={9781538645840}, url={http://dx.doi.org/10.1109/gsmm.2018.8439672}, DOI={10.1109/gsmm.2018.8439672}, abstractNote={This paper presents a 24–44 GHz ultra-wideband (UWB) low-noise amplifier (LNA); simultaneously covering all major 5G cellular frequency bands. The LNA has been designed in 45nm CMOS SOI technology, has a maximum gain of 20 dB with more than 65% 3dB bandwidth (24-47.5 GHz), and a noise figure less than 5.5 dB (typical 4.7 dB) in the band. A narrowband 28 GHz LNA is presented for comparison and evaluation of merits of a wideband design.}, booktitle={2018 11th Global Symposium on Millimeter Waves (GSMM)}, publisher={IEEE}, author={Chauhan, Vikas and Floyd, Brian}, year={2018}, month={May} }
 @article{greene_chauhan_floyd_2018, title={Built-In Test of Phased Arrays Using Code-Modulated Interferometry}, volume={66}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85040060676&partnerID=MN8TOARS}, DOI={10.1109/tmtt.2017.2784373}, abstractNote={This paper presents a built-in self-test technique for phased arrays that applies code modulation to each element within the array to allow parallel in situ measurements and a built-in distribution network to allow injection or extraction of test signals. The aggregated test response is downconverted from radio-frequency or millimeter-wave frequencies using a direct (power) detector, resulting in a baseband interference signal composed of code-modulated complex cross correlations between all elemental signals. Using orthogonal code products, each cross correlation can be extracted from the interference signal, and then the full set of cross correlations can be used to obtain amplitude and phase data of each element. A four-element 60-GHz phased-array receiver front end that includes this code-modulated embedded test (CoMET) infrastructure has been fabricated in SiGe BiCMOS technology. The BIST overhead is less than 2% of the total die area. Comparisons between our built-in test technique and measurements using a vector network analyzer show that CoMET can be used to extract amplitude with 1 dB accuracy and phase with four degree accuracy. Furthermore, measurements confirm that CoMET can be used to extract the phase-step response of each element in parallel across all settings as well as phase offset introduced by the built-in test network.}, number={5}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Greene, Kevin and Chauhan, Vikas and Floyd, Brian}, year={2018}, month={May}, pages={2463–2479} }
 @inproceedings{floyd_2018, title={High-performance millimeter-wave beamformers with built-in self-test}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85048120217&partnerID=MN8TOARS}, DOI={10.1109/CICC.2018.8357113}, abstractNote={•Phased arrays are the enabling technology for 5G-mmW; however, research is needed to find new architectures having improved performance, reduced cost, and built-in test capabilities: — Power efficiency and/or size of array: •By using improved SiGePA techniques, including harmonic termination, we can improve the back-off efficiency by ∼5X. •Reconfigurablity of array: — By using Dual-Vector Doherty, we can reconfigure the TX between a Doherty mode with improved efficiency and class-AB with improved linearity. — Built-in Self-Test of arrays: •By using code-modulated interferometry, we can extract amplitude and phase responses of all elements in parallel using a simply power detector.}, booktitle={2018 IEEE Custom Integrated Circuits Conference, CICC 2018}, author={Floyd, B.}, year={2018}, pages={1–68} }
 @inproceedings{wilson_dean_floyd_2018, title={Mixer-First MIMO Receiver with Multi-Port Impedance Tuning for Decoupling of Compact Antenna Systems}, volume={2018-June}, ISBN={9781538645451}, url={http://dx.doi.org/10.1109/rfic.2018.8429048}, DOI={10.1109/rfic.2018.8429048}, abstractNote={This paper introduces mutual impedance tuning for N-path mixer-first MIMO receivers, useful for dynamic decoupling of coupled-antenna systems. A two-port mixer-first MIMO receiver is realized in 45-nm SOI CMOS and includes polyphase baseband resistive-coupling networks. This coupled response is upconverted to radio frequency to realize tunable mutual impedance. The two receivers consume 16 mW and operate over 0.1-3 GHz. Each receiver achieves 3–6 dB noise figure and 14–40 dB conversion gain. When connected to two antennas placed an eighth-wavelength apart, measurements show that N-path decoupling improves signal-to-noise ratio by 7 dB.}, booktitle={2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)}, publisher={IEEE}, author={Wilson, Charley and Dean, Jacob and Floyd, Brian A.}, year={2018}, month={Jun}, pages={112–115} }
 @article{sarkar_floyd_2017, title={A 28-GHz Harmonic-Tuned Power Amplifier in 130-nm SiGe BiCMOS}, volume={65}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85008465269&partnerID=MN8TOARS}, DOI={10.1109/tmtt.2016.2636842}, abstractNote={The design methodology and measurement results of a millimeter-wave harmonic-tuned power amplifier (PA) are presented. The PA uses optimum fundamental and second-harmonic terminations to achieve high peak power-added efficiency (PAE). We present a parasitic-aware design technique for the output network realized as a bandpass filter cascaded with or surrounded by a low-pass matching network. This technique demonstrates a method of manipulating the second-harmonic phase of a Chebyshev bandpass filter, while maintaining a suitable impedance match at the fundamental. The technique is applied to a 28-GHz PA in SiGe BiCMOS, which achieves 15.3-dB gain, 18.6-dBm saturated output power, 15.5-dBm output 1-dB compression point, and 35.3% peak PAE. When backed off 6- from 1-dB compression, the PA achieves 11.5% PAE with a third-order intermodulation product of −33.7 dBc.}, number={2}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Sarkar, Anirban and Floyd, Brian A.}, year={2017}, month={Feb}, pages={522–535} }
 @article{yeh_walker_balboni_floyd_2017, title={A 28-GHz Phased-Array Receiver Front End With Dual-Vector Distributed Beamforming}, volume={52}, ISSN={["1558-173X"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85016476641&partnerID=MN8TOARS}, DOI={10.1109/jssc.2016.2635664}, abstractNote={This paper presents a 28-GHz four-channel phased-array receiver in 130-nm SiGe BiCMOS technology for fifth-generation cellular application. The phased-array receiver employs scalar-only weighting functions within each receive path and then global quadrature power combining to realize beamforming. We discuss both the theory and nonidealities of this architecture and then circuit design details for our phased-array front-end prototype. Differential low-noise amplifiers and dual-vector variable-gain amplifiers are used to realize each front end in a compact area of 0.3 mm2. Across 4-b phase settings, each array element achieves 5.1–7 dB noise figure, −16.8 to −13.8 dBm input-referred 1-dB compression point, and −10.5 to −8.9 dBm input-referred third-order intercept point. The average gain per element is 10.5 dB at 29.7 GHz, whereas the 3-dB bandwidth is 24.5% (26.5–33.9 GHz). Root-mean-squared gain and phase errors are less than 0.6 dB and 5.4° across 28–32 GHz, respectively, and all four elements provide well-matched and well-isolated responses. Power consumption is 136 mW per element, equaling 546 mW for the four-element array.}, number={5}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Yeh, Yi-Shin and Walker, Benjamin and Balboni, Ed and Floyd, Brian}, year={2017}, month={May}, pages={1230–1244} }
 @article{sarkar_aryanfar_floyd_2017, title={A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power}, volume={52}, ISSN={["1558-173X"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85018626903&partnerID=MN8TOARS}, DOI={10.1109/jssc.2017.2686585}, abstractNote={In this paper, we present a two-stage, four-way combined power amplifier (PA) operating in the 27–31-GHz frequency range in 180-nm SiGe BiCMOS technology. The output network of the PA employs spiral transformers and a microstrip T-combiner to realize low-loss two-way series, two-way parallel power combining. With the help of a lumped-element transformer model, we present a co-optimization technique for the transformer and the adjoining matching components to minimize the power loss of the full output network. The design methodology is applicable for realizing an arbitrary impedance at the device plane with a K-way series, M-way parallel combiner. The efficacy of this technique is demonstrated by the realization of a PA, which has 27.6-dB gain, 23.2-dBm, 1-dB compressed output power, 32.7% power-added efficiency (PAE) at 1-dB compression, and 15% PAE at 6-dB back off. Linearity measurements show less than 4° amplitude-modulation to phase-modulation distortion below 3-dB back off and less than −32-dBc intermodulation product at 6-dB back off.}, number={6}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Sarkar, Anirban and Aryanfar, Farshid and Floyd, Brian A.}, year={2017}, month={Jun}, pages={1680–1686} }
 @inproceedings{yeh_balboni_floyd_2017, title={A 28-GHz phased-array transceiver with series-fed dual-vector distributed beamforming}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85026892597&partnerID=MN8TOARS}, DOI={10.1109/rfic.2017.7969018}, abstractNote={This paper presents a 28-GHz four-element phased-array transceiver in 130-nm SiGe BiCMOS technology for 5G cellular application. The array employs scalar-only weighting functions within each front-end and a global quadrature function, enabling small footprint for each element. A dual-vector series feed network also reduces size of the array. Measurements show that each receive front-end achieves 8.7 to 11.5 dB gain, 4.5 to 6.9 dB noise figure, −25.4 to −18.4 dBm input 1-dB compression point, and < 0.5dB/2.1° RMS gain/phase error at 24 to 28 GHz. Each transmit front-end achieves 9.4 to 14.3 dB gain, 5.5 to 10.6 dBm output 1-dB compression point, and < 0.4dB/4.2° RMS gain/phase error at 24 to 28 GHz. The four-element transceiver array occupies 2.9 mm2 area and consumes 1.08 W in transmit mode and 0.68 W in receive mode.}, booktitle={2017 ieee radio frequency integrated circuits symposium (rfic)}, author={Yeh, Y. S. and Balboni, E. and Floyd, Brian}, year={2017}, pages={65–68} }
 @article{greene_sarkar_floyd_2017, title={A 60-GHz Dual-Vector Doherty Beamformer}, volume={52}, ISSN={["1558-173X"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85013649014&partnerID=MN8TOARS}, DOI={10.1109/jssc.2017.2661980}, abstractNote={In this paper, we demonstrate a 60-GHz transmit beamformer implemented in 130-nm SiGe BiCMOS technology which includes a Doherty amplifier driven by a dual-vector phase rotator (DVR). In addition, a benchmarking circuit comprising another DVR followed by two class-AB amplifiers, each nearly identical to the carrier amplifier within the Doherty, is included which allows us to measure the Doherty improvement in terms of efficiency and output power over conventional approaches. The dual-vector Doherty element achieves 28-dB gain with an output 1-dB compression point of +16.7 dBm. A power-added efficiency (PAE) of 16.5% is realized at 1-dB compression, with 10.8% and 7% PAE at 3- and 6-dB back-off, respectively. A stand-alone Doherty amplifier achieves a 17.1-dBm output 1-dB compression point at 23.7% PAE and a 6-dB back-off PAE of 13%. The DVR performs the phase shifting for each phased-array element necessary for beamforming, as well as providing tunable amplitude balance and phase separation between input signals to the Doherty amplifier. This allows optimization of both linearity and efficiency profiles across frequency. The Doherty element is capable of generating full 360° phase shifts with 5-b accuracy having root-mean-squared errors less than 0.6 dB in amplitude and 6° in phase from 60 to 66 GHz.}, number={5}, journal={IEEE JOURNAL OF SOLID-STATE CIRCUITS}, author={Greene, Kevin and Sarkar, Anirban and Floyd, Brian}, year={2017}, month={May}, pages={1373–1387} }
 @article{fujibayashi_takeda_wang_yeh_stapelbroek_takeuchi_floyd_2017, title={A 76- to 81-GHz Multi-Channel Radar Transceiver}, volume={52}, ISSN={0018-9200 1558-173X}, url={http://dx.doi.org/10.1109/jssc.2017.2700359}, DOI={10.1109/jssc.2017.2700359}, abstractNote={This paper presents a packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS for both long-range and short-range automotive radars. The chip contains a two-channel transmitter (TX), a six-channel receiver (RX), a local-oscillator (LO) chain, and built-in self-test (BIST) circuitry. Each transmit channel includes multiple variable-gain amplifiers and a two-stage power amplifier. Measured on-die output power per channel is +18 dBm at 25 °C, decreasing to +16 dBm at 125 °C. Each receive channel includes a current-mode mixer, followed by intermediate-frequency buffers. At 25 °C, measured on-die noise figure is 10–11 dB, conversion gain is 14–15 dB, and input 1-dB compression point exceeds +1 dBm. An integrated LO chain drives the transmit and receive chains and includes an 18.5- to 20.6-GHz voltage-controlled oscillator connected to cascaded frequency doublers and a divide-by-four prescaler. At 25 °C, measured phase noise is −100 dBc/Hz at 1-MHz offset from a 77-GHz carrier. Integrated BIST circuits enable the measurement of signal power, RX gain, channel-to-channel phase, and internal temperature. The chip is flip-chip packaged into a ball-grid array and extracted interconnect loss for the package is 1.5 to 2 dB. Total power consumption for the chip is 1.8 W from 3.3 V for a single-TX, six-RX mode.}, number={9}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Fujibayashi, Takeji and Takeda, Yohsuke and Wang, Weihu and Yeh, Yi-Shin and Stapelbroek, Willem and Takeuchi, Seiji and Floyd, Brian}, year={2017}, month={Sep}, pages={2226–2241} }
 @inproceedings{bonner-stewart_wilson_floyd_2017, title={A Tunable reflection-mode N-path filter Using 45-nm SOI CMOS}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85032500755&partnerID=MN8TOARS}, DOI={10.1109/mwsym.2017.8058961}, abstractNote={A tunable 700-to 3000-MHz reflection-mode N-path filter in 45-nm SOI CMOS is presented. The filter employs a reflective architecture in which two eight-phase passive mixers are combined with an external 90-degree hybrid coupler to realize a circuit that passes in-band signals and absorbs out-of-band signals. The filter achieves insertion loss 0.8 to 2.1 dB and noise figure of 0.9 to 3.9 dB over the entire tuning range, while consuming 4 to 8 mW from a 0.9-V supply. Input-referred 1-dB compression point is +0 dBm, and input-referred third-order intercept point (HP3) is +10 dBm in-band and +22 dBm out-of-band.}, booktitle={2017 ieee mtt-s international microwave symposium (ims)}, author={Bonner-Stewart, J. and Wilson, C. and Floyd, Brian}, year={2017}, pages={1671–1674} }
 @inproceedings{floyd_sarkar_greene_yeh_2017, title={Toward efficient, reconfigurable, and compact beamforming for 5g millimeter-wave systems}, volume={2017-October}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85040239609&partnerID=MN8TOARS}, DOI={10.1109/bctm.2017.8112913}, abstractNote={In this paper, we discuss architectures and integrated circuits for efficient, reconfigurable and compact millimeter-wave beamforming in silicon. First, we present techniques to improve peak and back-off power-added efficiency (PAE) of SiGe power amplifiers, demonstrated with a 28-GHz harmonic-tuned amplifier (+15.5 dBm output 1-dB compression point, 35% peak PAE, 11.5% PAE at 6-dB back-off) and a 60GHz Doherty amplifier (+17.1 dBm output 1-dB compression point, 23.7% peak PAE, 13% PAE at 6-dB back-off). Second, we present a dual-vector Doherty beamformer architecture which allows reconfiguration between an efficient Doherty mode (+16.7 dBm output 1-dB compression point and 7% PAE at 6-dB backoff) and a linear class-AB mode (+13 dBm output 1-dB compression point and 4.5% PAE at 6-dB back-off), demonstrated in SiGe at 60 GHz. Finally, we present a compact architecture for beamformers which employs dual-vector scaling functions within each element and then global combining and interpolation. This is demonstrated with a 28-GHz dual-vector receiver array in SiGe which requires only 0.3 mm2 for each receiver front-end.}, booktitle={2017 ieee bipolar/bicmos circuits and technology meeting (bctm)}, author={Floyd, Brian and Sarkar, A. and Greene, K. and Yeh, Y. S.}, year={2017}, pages={66–73} }
 @inproceedings{wilson_floyd_2016, title={20-30 GHz mixer-first receiver in 45-nm SOI CMOS}, volume={2016-July}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84980371004&partnerID=MN8TOARS}, DOI={10.1109/rfic.2016.7508323}, abstractNote={A 20-30 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The receiver employs four-phase passive mixing with input inductor to realize tunable impedance matching up to 30 GHz. The receiver achieves an 8-dB noise figure with reconfigurable 8.9 to 20.6-dB conversion gain and 2:1 impedance tuning range. Input 1-dB compression point ranges from -13 to -9.3 dBm and power consumption is 41 mW.}, booktitle={2016 ieee radio frequency integrated circuits symposium (rfic)}, author={Wilson, C. and Floyd, Brian}, year={2016}, pages={344–347} }
 @inproceedings{yeh_walker_balboni_floyd_2016, title={A 28-GHz 4-channel dual-vector receiver phased array in SiGe BiCMOS technology}, volume={2016-July}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84980416213&partnerID=MN8TOARS}, DOI={10.1109/rfic.2016.7508325}, abstractNote={This paper presents a 28-GHz four-channel phased-array receiver in 120-nm SiGe BiCMOS technology for 5G cellular application. The phased-array receiver employs scalar-only weighting functions within each front-end and then global quadrature power combining to realize beamforming. Differential LNAs and dual-vector variable-gain amplifiers are used to realize each front-end with compact area. Each front-end achieves 5.1 to 7 dB noise figure, -16.8 to -13.8 dBm input compression point, -10.5 to -8.9 dBm input third-order intercept point across 4-bit phase settings and a 3-dB bandwidth of 26.5 to 33.9GHz, while consuming 136 mW per element. RMS gain and phase errors are <; 0.6 dB and <; 5.4° at 28-32 GHz respectively, and all four elements reveal well-matched responses.}, booktitle={2016 ieee radio frequency integrated circuits symposium (rfic)}, author={Yeh, Y. S. and Walker, B. and Balboni, E. and Floyd, Brian}, year={2016}, pages={352–355} }
 @inproceedings{fujibayashi_takeda_wang_yeh_stapelbroek_takeuchi_floyd_2016, title={A 76-to 81-GHz packaged single-chip transceiver for automotive radar}, volume={2016-November}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85002194596&partnerID=MN8TOARS}, DOI={10.1109/bctm.2016.7738943}, abstractNote={This paper presents a flip-chip packaged 76- to 81-GHz transceiver chip implemented in SiGe BiCMOS technology for both long-range and short-range automotive radar applications. The single chip contains a two-channel transmitter with +18-dBm saturated output power per channel; an LO chain with ×4 multiplier, wide-band 20-GHz VCO with -100-dBc/Hz phase noise at 1-MHz offset referenced to a 77-GHz carrier, and divide-by-four prescaler; and a six-channel receiver with 10- to 11-dB noise figure, 14- to 15-dB conversion gain and +1-dBm input P1dB in unpackaged condition. The interconnect loss through the BGA package at 80 GHz is 1.5 to 2 dB. Built-in self-test (BIST) circuits are integrated to enable RF output power, receiver gain, relative channel-to-channel phase and internal temperature measurement.}, booktitle={2016 ieee bipolar/bicmos circuits and technology meeting (bctm)}, author={Fujibayashi, T. and Takeda, Y. and Wang, W. H. and Yeh, Y. S. and Stapelbroek, W. and Takeuchi, S. and Floyd, Brian}, year={2016}, pages={166–169} }
 @inproceedings{greene_chauhan_floyd_2016, title={Code-modulated embedded test for phased arrays}, volume={2016-May}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84973922847&partnerID=MN8TOARS}, DOI={10.1109/vts.2016.7477274}, abstractNote={Millimeter wave (mm-wave) design has become the forefront for enabling multi-Gb/s wireless communications due to the abundance of available bandwidth at frequencies above 24 GHz. At these frequencies, phased arrays are used to meet link budgets by combining phase-adjusted responses of multiple antennas to form a high-gain, directive beam which is electrically steerable. Current requirements point to array sizes ranging from 8-32 elements, each of which must be measured and calibrated in terms of RF output power and phase to obtain the desired array performance. This paper will first review phased-array topologies and calibration requirements. We will then present a code modulated technique for manufacturing test of the array which uses only digital code modulators per element and a single global mm-wave squaring circuit in the form of a power detector. This approach allows measurement of full array performance with a single detector using minimum additional built-in-test hardware. Behavioral models indicate that this method can estimate the phase response within 1 degree and an output power within 0.2 dB for each individual element using global array measurements.}, booktitle={2016 ieee 34th vlsi test symposium (vts)}, author={Greene, K. and Chauhan, V. and Floyd, Brian}, year={2016} }
 @inproceedings{chauhan_greene_floyd_2016, title={Code-modulated interferometric imaging system using phased arrays}, volume={9830}, ISSN={["1996-756X"]}, url={http://dx.doi.org/10.1117/12.2234758}, DOI={10.1117/12.2234758}, abstractNote={Millimeter-wave (mm-wave) imaging provides compelling capabilities for security screening, navigation, and bio- medical applications. Traditional scanned or focal-plane mm-wave imagers are bulky and costly. In contrast, phased-array hardware developed for mass-market wireless communications and automotive radar promise to be extremely low cost. In this work, we present techniques which can allow low-cost phased-array receivers to be reconfigured or re-purposed as interferometric imagers, removing the need for custom hardware and thereby reducing cost. Since traditional phased arrays power combine incoming signals prior to digitization, orthogonal code-modulation is applied to each incoming signal using phase shifters within each front-end and two-bit codes. These code-modulated signals can then be combined and processed coherently through a shared hardware path. Once digitized, visibility functions can be recovered through squaring and code-demultiplexing operations. Pro- vided that codes are selected such that the product of two orthogonal codes is a third unique and orthogonal code, it is possible to demultiplex complex visibility functions directly. As such, the proposed system modulates incoming signals but demodulates desired correlations. In this work, we present the operation of the system, a validation of its operation using behavioral models of a traditional phased array, and a benchmarking of the code-modulated interferometer against traditional interferometer and focal-plane arrays.}, booktitle={Passive and Active Millimeter-Wave Imaging XIX}, publisher={SPIE}, author={Chauhan, Vikas and Greene, Kevin and Floyd, Brian}, editor={Wikner, David A. and Luukanen, Arttu R.Editors}, year={2016}, month={May} }
 @inbook{floyd_natarajan_2016, title={System-on-a-chip mm-wave silicon transmitters}, ISBN={9781107295520}, url={http://dx.doi.org/10.1017/cbo9781107295520.011}, DOI={10.1017/cbo9781107295520.011}, abstractNote={Millimeter-wave (mm-wave) links feature large bandwidths which enable highthroughput, multi-gigabit-per-second (multi-Gb/s) wireless links. High-volume, lowcost applications for wireless communications require the transmitter to achieve a high integration level, avoiding both lossy off-chip interconnects at mm-wave frequencies and expensive packaging technologies. State-of-the-art CMOS [1] and SiGe BiCMOS [2–4] technologies achieve ft and fmax in excess of 200 GHz, making integrated mm-wave circuits feasible (see Fig. 10.1); however, the relatively high operation frequency compared with fmax makes it challenging to achieve both high transmit output power and high efficiency. Earlier chapters have discussed high-efficiency power amplifiers and efficient spatial combining and modulation schemes. This chapter will discuss systemon- a-chip (SOC) approaches to achieve highly integrated mm-wave single-element and phased-array transmitters. It is important to note that mm-wave refers to frequencies from 30 GHz to 300 GHz and the feasibility of several complex transmitter architectures must be evaluated carefully in the context of operating frequency relative to the capabilities of the process technology. The broad range of frequencies also impacts integrated circuit topologies since these frequencies represent a natural yet ill-defined transition point between the use of on-chip lumped inductor/capacitor (LC) passives and on-chip distributed transmission-line (t-line)-based components.}, booktitle={mm-Wave Silicon Power Amplifiers and Transmitters}, publisher={Cambridge University Press}, author={Floyd, Brian and Natarajan, Arun}, editor={Hashemi, Hossein and Raman, SanjayEditors}, year={2016}, month={Apr}, pages={376–418} }
 @inproceedings{yeh_floyd_2015, title={A 55-GHz power-efficient frequency quadrupler with high harmonic rejection in 0.1-mu m SiGe BiCMOS technology}, volume={2015-November}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84975774977&partnerID=MN8TOARS}, DOI={10.1109/rfic.2015.7337756}, abstractNote={This paper presents a V-band frequency quadrupler in 0.1-μm SiGe BiCMOS technology with 3-dB bandwidth from 44.8 to 57.2 GHz. The circuit employs cascode stacks comprising in-phase class-C common-emitter and anti-phase class-AB cascode devices to obtain current pulses at ×4 frequency. Four such cascodes driven with differential and tunable quadrature increase the 4th harmonic output power while suppressing all other harmonics 22 dB or more. Measurements show >7.4-dBm 4th harmonic output power, and >5.2% power efficiency for the core of the multiplier.}, booktitle={Proceedings of the 2015 ieee radio frequency integrated circuits symposium (rfic 2015)}, author={Yeh, Y. S. and Floyd, Brian}, year={2015}, pages={267–270} }
 @inproceedings{greene_floyd_2015, title={Dual-vector phase rotator for Doherty beamformers}, volume={2015-November}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84975761262&partnerID=MN8TOARS}, DOI={10.1109/rfic.2015.7337772}, abstractNote={A 28-GHz dual-vector phase rotator is introduced, having the capability of generating two quadrature output signals that track one another in phase. The 4-bit dual-vector rotator was implemented in IBM 0.12-μm SiGe BiCMOS technology and achieves full 360o phase shifting, RMS phase and amplitude errors of <; 5 degrees and <; 0.8 dB, respectively for both output vectors, and 10-12 dB of gain. Output 1-dB compression points for both quadrature outputs is -6.5 to -4.4 dBm, suitable for directly driving a Doherty amplifier in a 28-GHz beamformer.}, booktitle={Proceedings of the 2015 ieee radio frequency integrated circuits symposium (rfic 2015)}, author={Greene, K. and Floyd, Brian}, year={2015}, pages={331–334} }
 @inproceedings{wang_takeda_yeh_floyd_2014, title={A 20GHz VCO and frequency doubler for W-band FMCW radar applications}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84903826560&partnerID=MN8TOARS}, DOI={10.1109/sirf.2014.6828522}, abstractNote={This paper presents a low-noise Colpitts VCO with transformer-based resonator and a 20-to-40GHz frequency doubler for use in 76~77GHz long-range radar and 77~81GHz short-range radar transceivers. To reduce supply pushing and AM-to-PM noise conversion in the high-gain VCO, a differentially tuned, transformer-coupled varactor is used. Implemented in 0.12-μm SiGe BiCMOS technology, the VCO and doubler achieve an 11% continuous tuning range from 37.5-42GHz, and a phase noise between -103 and -106dBc/Hz at 1MHz offset from the 40GHz carrier.}, booktitle={2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF)}, author={Wang, W. H. and Takeda, Y. and Yeh, Y. S. and Floyd, Brian}, year={2014}, pages={104–106} }
 @inproceedings{sarkar_floyd_2014, title={A 28-GHz class-J power amplifier with 18-dBm output power and 35% peak PAE in 120-nm SiGe BiCMOS}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84903832374&partnerID=MN8TOARS}, DOI={10.1109/sirf.2014.6828532}, abstractNote={A 28-GHz Power Amplifier (PA) designed in 120-nm SiGe BiCMOS for potential use in mobile millimeter-wave phased arrays is presented in this paper. The core of the PA is a cascode amplifier operated in class-J mode. A multi-harmonic load-pull analysis was used to determine the optimum harmonic output impedances (up to third harmonic) resulting in improved efficiency. The PA has a measured 15.3-dB small signal gain, 18.6-dBm saturated output power and 35.3% peak power added efficiency (PAE) at 28GHz. At 1-dB compression the PA has a 15.5-dBm output power and 31.5% PAE.}, booktitle={2014 IEEE 14th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SIRF)}, author={Sarkar, A. and Floyd, Brian}, year={2014}, pages={71–73} }
 @inproceedings{takeda_fujibayashi_yeh_wang_floyd_2014, title={A 76-to 81-GHz transceiver chipset for long-range and short-range automotive radar}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84905054469&partnerID=MN8TOARS}, DOI={10.1109/mwsym.2014.6848490}, abstractNote={This paper presents a 76- to 81-GHz transceiver chipset implemented in SiGe BiCMOS technology for both long-range and short-range radar applications. A four-channel receiver achieves 11-12 dB noise figure, 16-dB conversion gain, and -2 dBm input compression point. A single-channel transmitter with integrated subharmonic VCO achieves +17 dBm output power and -97 dBc/Hz phase noise at 1-MHz offset referenced to the 77-GHz carrier. The chipset includes built-in-self-test features allowing measurement of RF power, gain, and phase. Total power consumption is 0.79 W for the four-channel receiver and 1.16 W for the transmitter.}, booktitle={2014 ieee mtt-s international microwave symposium (ims)}, author={Takeda, Y. and Fujibayashi, T. and Yeh, Y. S. and Wang, W. H. and Floyd, Brian}, year={2014} }
 @inproceedings{sarkar_greene_floyd_2014, title={A power-efficient 4-element beamformer in 120-nm SiGe BiCMOS for 28-GHz cellular communications}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84919631866&partnerID=MN8TOARS}, DOI={10.1109/bctm.2014.6981287}, abstractNote={A 4-element beamformer designed in 120-nm SiGe BiCMOS technology for 28-GHz mobile millimeter-wave broadband system is presented in this paper. Each element of the beamformer consists of a 4-bit active phase shifter and a two-stage Power Amplifier (PA). A two-stage PA design with a Class-C pre-driver and a 2nd-harmonic-tuned Class-AB driver stage is adopted for high gain and high efficiency at both peak and backed-off power levels. The active phase shifter employs in-phase/ quadrature phase current steering and digital control of transconductance (Gm). Measurement results show a 33-dB gain, 16.5-dBm saturated output power, 15.7-dBm oP1dB, 27.5% peak PAE and 8.2% 7-dB back-off PAE at 27 GHz for a single element. The minimum (maximum) RMS gain and phase errors across the 27-29 GHz band were 0.5 dB (3 dB) and 1.5°(12°). The beamformer also includes a 1:4 power splitter and a serial interface for digital control and occupies a die area of 5.32mm2.}, booktitle={2014 ieee bipolar/bicmos circuits and technology meeting (bctm)}, author={Sarkar, A. and Greene, K. and Floyd, Brian}, year={2014}, pages={68–71} }
 @inproceedings{floyd_2014, title={Market opportunities and testing challenges for millimeter-wave radios and radars}, ISBN={9781479947225}, url={http://dx.doi.org/10.1109/test.2014.7035302}, DOI={10.1109/test.2014.7035302}, abstractNote={The millimeter-wave spectrum from 30 to 300 GHz features large available bandwidth and small wavelengths which can be leveraged for high-throughput wireless communications and high-resolution radar sensors. Key mass-market millimeter-wave applications include local-area networks at 60 GHz which can support multiple gigabit-per-second transfer rates, vehicular radars at 76–81 GHz for collision avoidance or adaptive cruise-control, and fifth-generation cellular networks at 28 GHz which can support higher data rates. Silicon technology has advanced to the point that it is now possible to realize high-performance and low-cost solutions for each of these applications. This talk will review application requirements and opportunities for these markets and then highlight the challenges associated with both antenna and package integration and manufacturing test for multi-antenna transceivers operating at millimeter-wave frequencies. Finally, a recently-developed 76–81-GHz radar transceiver chipset with built-in-test will be highlighted to illustrate an approach to simplify the manufacturing test of a millimeter-wave radar system.}, booktitle={2014 International Test Conference}, publisher={IEEE}, author={Floyd, Brian}, year={2014}, month={Oct} }
 @inproceedings{sarkar_floyd_2013, title={A 60 GHz Doherty power amplifier with 14% PAE at 6-dB back off}, booktitle={Proceedings SRC Techcon Conference}, author={Sarkar, A. and Floyd, B.}, year={2013}, month={Sep} }
 @inproceedings{sarkar_floyd_2012, title={Power efficient power amplifiers for 60GHz phased array transmitters}, booktitle={Proceedings SRC Techcon Conference}, author={Sarkar, A. and Floyd, B.}, year={2012}, month={Sep} }
 @article{qiu_ivanov_nueslein_john_augustine_floyd_wang_2011, title={2011 IMS/RFIC/ARFTG workshops}, volume={12}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-79953886292&partnerID=MN8TOARS}, DOI={10.1109/MMM.2011.940308}, number={3}, journal={IEEE Microwave Magazine}, author={Qiu, J.X. and Ivanov, T. and Nueslein, M. and John, M.S. and Augustine, G. and Floyd, B. and Wang, A.}, year={2011}, pages={52–57} }
 @article{natarajan_reynolds_tsai_nicolson_zhan_kam_liu_huang_valdes-garcia_floyd_et al._2011, title={A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications}, volume={46}, ISSN={0018-9200 1558-173X}, url={http://dx.doi.org/10.1109/jssc.2011.2118110}, DOI={10.1109/jssc.2011.2118110}, abstractNote={A fully-integrated 16-element 60-GHz phased-array receiver is implemented in IBM 0.12-μm SiGe BiCMOS technology. The receiver employs RF-path phase-shifting and is designed for multi-Gb/s non-line of sight links in the 60-GHz ISM band (IEEE 802.15.3c and 802.11ad). Each RF front-end includes variable-gain LNAs and phase shifters with each front-end capable of 360° variable phase shift (11.25° phase resolution) from 57 GHz to 66 GHz with coarse/fine gain steps. A detailed analysis of the noise trade-offs in the receiver array design is presented to motivate architectural choices. The hybrid active and passive signal-combining network in the receiver uses a differential cross-coupled Gysel power combiner that reduces combiner loss and area. Each array front-end has 6.8-dB noise figure (at 22°C ) and the array has -10 dB to 58 dB programmable gain from single-input to output. Sixteen 60-GHz aperture-coupled patch-antennas and the RX IC are packaged together in multi-layer organic and LTCC packages. The packaged RX IC is capable of operating in all four IEEE 802.15.3c channels (58.32 to 64.8 GHz). Beam-forming and beam-steering measurements show good performance with 50-ns beam switching time. 5.3-Gb/s OFDM 16-QAM and 4.5 Gb/s SC 16-QAM links are demonstrated using the packaged RX ICs. Both line-of-sight links (~7.8 m spacing) and non-line-of-sight links using reflections (~9 m total path length) have been demonstrated with better than -18 dB EVM. The 16-element receiver consumes 1.8 W and occupies 37.7 mm2 of die area.}, number={5}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Natarajan, Arun and Reynolds, Scott K. and Tsai, Ming-Da and Nicolson, Sean T. and Zhan, Jing-Hong Conan and Kam, Dong Gun and Liu, Duixian and Huang, Yen-Lin Oscar and Valdes-Garcia, Alberto and Floyd, Brian A. and et al.}, year={2011}, month={May}, pages={1059–1075} }
 @article{kam_liu_natarajan_reynolds_chen_floyd_2011, title={LTCC Packages With Embedded Phased-Array Antennas for 60 GHz Communications}, volume={21}, ISSN={1531-1309 1558-1764}, url={http://dx.doi.org/10.1109/lmwc.2010.2103932}, DOI={10.1109/lmwc.2010.2103932}, abstractNote={A low-cost, fully-integrated antenna-in-package solution for 60 GHz phased-array systems is demonstrated. Sixteen patch antennas are integrated into a 28 mm × 28 mm ball grid array together with a flip-chip attached transmitter or receiver IC. The packages have been implemented using low temperature co-fired ceramic technology. 60 GHz interconnects, including flip-chip transitions and via structures, are optimized using full-wave simulation. Anechoic chamber measurement has shown ~ 5 dBi unit antenna gain across all four IEEE 802.15.3c channels, achieving excellent model-to-hardware correlation. The packaged transmitter and receiver ICs, mounted on evaluation boards, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s.}, number={3}, journal={IEEE Microwave and Wireless Components Letters}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kam, Dong Gun and Liu, Duixian and Natarajan, Arun and Reynolds, Scott and Chen, Ho-Chung and Floyd, Brian A.}, year={2011}, month={Mar}, pages={142–144} }
 @article{kam_liu_natarajan_reynolds_floyd_2011, title={Organic Packages With Embedded Phased-Array Antennas for 60-GHz Wireless Chipsets}, volume={1}, ISSN={2156-3950}, url={http://dx.doi.org/10.1109/tcpmt.2011.2169064}, DOI={10.1109/tcpmt.2011.2169064}, abstractNote={A multilayer organic package with embedded 60-GHz antennas and fully integrated with a 60-GHz phased-array transmitter or receiver chip is demonstrated. The package includes sixteen phased-array antennas, an open cavity for housing the flip-chip attached RF chip, and interconnects operating at DC-66 GHz. The 28 mm 28 mm ball grid array package is manufactured using printed circuit board processes and uses a combination of liquid-crystal polymer and glass-reinforced laminates, allowing excellent 60-GHz interconnect and antenna performance. The measured return loss and gain of each antenna from 56 to 66 GHz are and , respectively. Finally, the packaged transmitter and receiver chipsets, each working with a heat sink, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s using 16-quadrature amplitude modulation single-carrier and orthogonal frequency division multiplexing schemes.}, number={11}, journal={IEEE Transactions on Components, Packaging and Manufacturing Technology}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kam, Dong Gun and Liu, Duixian and Natarajan, Arun and Reynolds, Scott K. and Floyd, Brian A.}, year={2011}, month={Nov}, pages={1806–1814} }
 @article{liu_akkermans_chen_floyd_2011, title={Packages With Integrated 60-GHz Aperture-Coupled Patch Antennas}, volume={59}, ISSN={0018-926X 1558-2221}, url={http://dx.doi.org/10.1109/tap.2011.2163760}, DOI={10.1109/tap.2011.2163760}, abstractNote={This paper presents balanced-fed and fork-fed aperture-coupled patch antennas and 16-element arrays suitable for broadband millimeter-wave communications. The antennas are realized in a multi-layer organic package structure, to which RF integrated circuits can be integrated. To improve antenna bandwidth and radiation efficiency, an air cavity is used, resulting in a superstrate planar patch-antenna structure. Additionally, resonating apertures are used to further increase the antenna bandwidth. Measured results at 60 GHz for the antennas show good performance in terms of peak gain (about 8 dBi for a single element and 17 dBi for a 16-element array), bandwidth ( >; 10 GHz for 10-dB return loss bandwidths are achievable), and radiation efficiency (80% for single-element from simulation).}, number={10}, journal={IEEE Transactions on Antennas and Propagation}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Liu, Duixian and Akkermans, Johannes A. G. and Chen, Ho-Chung and Floyd, Brian}, year={2011}, month={Oct}, pages={3607–3616} }
 @article{valdes-garcia_reynolds_natarajan_kam_liu_lai_huang_chen_tsai_zhan_et al._2011, title={Single-Element and Phased-Array Transceiver Chipsets for 60-GHz Gb/s Communications}, volume={49}, ISSN={["1558-1896"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-79953788802&partnerID=MN8TOARS}, DOI={10.1109/mcom.2011.5741156}, abstractNote={This article summarizes the development of mature and highly integrated SiGe BiCMOS ICs for gigabit-per-second communications according to the requirements of the IEEE 802.15.3c and 802.11.ad-draft standards. A single-element transceiver chipset for point-to-point communications is described with emphasis on a feature-rich yet compact 60-GHz receiver. Next, a 16-element phased-array transceiver chipset for non-line-of-sight communications is described, with emphasis on a new power-efficient phased-array transmitter. Examples of gigabit-per-second line-of-sight and non-line-of-sight link experiments are provided, and system-level implementation trade-offs are discussed.}, number={4}, journal={IEEE COMMUNICATIONS MAGAZINE}, author={Valdes-Garcia, Alberto and Reynolds, Scott and Natarajan, Arun and Kam, Dong and Liu, Duixian and Lai, Jie-Wei and Huang, Yen-Lin Oscar and Chen, Ping-Yu and Tsai, Ming-Da and Zhan, Jing-Hong Conan and et al.}, year={2011}, month={Apr}, pages={120–131} }
 @inproceedings{reynolds_natarajan_tsai_nicolson_zhan_liu_kam_huang_valdes-garcia_floyd_et al._2010, title={A 16-element phased-array receiver IC for 60-GHz communications in SiGe BiCMOS}, ISBN={9781424462407}, url={http://dx.doi.org/10.1109/rfic.2010.5477306}, DOI={10.1109/rfic.2010.5477306}, abstractNote={A 0.12-µm SiGe phased-array Rx IC for beam-steered wireless communication in the 60-GHz band is described. It has 16 RF phase-shifting front-ends with 11° digital phase resolution and hybrid passive-active RF signal combining. It achieves 7.4–7.9 dB NF (not including 12-dB array gain) over the 4 IEEE channels. The IC has a double-conversion superheterodyne Rx core with a maximum of 72 dB of power gain in 1-dB steps, and the on-chip synthesizer achieves ≪ −90 dBc/Hz Rx phase noise at 1MHz offset. The IC draws 1.8 W at 2.7 V with a die area of 38 mm2. It has been packaged with 16 antennas in a 288-pin organic BGA and phased-array beamsteering has been demonstrated, along with 5+ Gb/s wireless links using 16-QAM OFDM.}, booktitle={2010 IEEE Radio Frequency Integrated Circuits Symposium}, publisher={IEEE}, author={Reynolds, Scott K. and Natarajan, Arun S. and Tsai, Ming-Da and Nicolson, Sean and Zhan, Jing-Hong Conan and Liu, Duixian and Kam, Dong G. and Huang, Oscar and Valdes-Garcia, Alberto and Floyd, Brian A. and et al.}, year={2010}, pages={461–464} }
 @article{valdes-garcia_nicolson_lai_natarajan_chen_reynolds_zhan_kam_liu_floyd_et al._2010, title={A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications}, volume={45}, ISSN={0018-9200 1558-173X}, url={http://dx.doi.org/10.1109/jssc.2010.2074951}, DOI={10.1109/jssc.2010.2074951}, abstractNote={A phased-array transmitter (TX) for multi-Gb/s non-line-of-sight links in the four frequency channels of the IEEE 802.15.3c standard (58.32 to 64.8 GHz) is fully integrated in a 0.12-μm SiGe BiCMOS process. It consists of an up-conversion core followed by a 1:16 power distribution tree, 16 phase-shifting front-ends, and a digital control unit. The TX core is a two-step sliding-IF up-conversion chain with frequency synthesizer that features 40 dB of gain programmability, I/Q balance and LO leakage correction, and a modulator for 802.15.3c common-mode signaling. The tradeoffs involved in the implementation of a 1:16 power distribution network are analyzed and a hybrid passive/active distribution tree architecture is introduced. Each of the 16 front-ends consists of a balanced passive phase shifter and a variable-gain, 3-stage PA that features oP1dB programmability through the bias control of the its final stage. All of the chip features are digitally controllable and individual memory arrays are integrated at each front-end to enable fast beam steering through a high-speed parallel interface. The IC occupies 44 mm and is fully characterized on wafer. The TX delivers 9 to 13.5 dBm oPidB per element at 60.48 GHz with a total power consumption of 3.8 to 6.2 W. Each element attains a phase-shift range >360° with an amplitude variation <;±1 dB across phase settings and adjacent elements. Measurement results from a packaged IC in an antenna chamber are also presented including the demonstration of spatial power combining up to +40 dBm EIRP and 16-element radiation patterns.}, number={12}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Valdes-Garcia, Alberto and Nicolson, Sean T. and Lai, Jie-Wei and Natarajan, Arun and Chen, Ping-Yu and Reynolds, Scott K. and Zhan, Jing-Hong Conan and Kam, Dong G. and Liu, Duixian and Floyd, Brian and et al.}, year={2010}, month={Dec}, pages={2757–2773} }
 @inproceedings{valdes-garcia_nicolson_lai_natarajan_chen_reynolds_zhan_floyd_2010, title={A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications}, volume={53}, ISBN={9781424460335}, url={http://dx.doi.org/10.1109/isscc.2010.5433956}, DOI={10.1109/isscc.2010.5433956}, abstractNote={The demonstration of multi-Gb/s links in the 60GHz band has created new opportunities for wireless communications [1,2]. Due to the directional nature of millimeter-wave (mm-Wave) propagation, beam steering enables longer-range non-line-of-sight (NLOS) links at these frequencies. A phased-array architecture is attractive for an integrated 60GHz transmitter (Tx) since it can attain both beam steering and higher EIRP through spatial combining. An all-RF 16-element 40-to-45GHz Tx for satellite applications [3], a 6-element 60GHz Tx with IF-path phase-shift [4], and a bi-directional 4-element 60GHz Tx/Rx with RF phase shifters [5] have been recently demonstrated in silicon. This work presents a fully-integrated phased-array Tx which supports multi-Gb/s NLOS IEEE 802.15.3c links. In addition to beamsteering, the IC has the following major features: an on-chip power sensor at each element, 3 temperature sensors, LO leakage and I/Q phase and amplitude adjustment, front-end OP1dB programmability, and an integrated modulator for pi/2-BPSK/MSK signaling (common mode in 802.15.3c). The IC integrates 2240 NPNs, 323,000 FETs and hundreds of transmission lines and is fabricated in the IBM 8HP 0.12µm SiGe BiCMOS process (fT = 200GHz).}, booktitle={2010 IEEE International Solid-State Circuits Conference - (ISSCC)}, publisher={IEEE}, author={Valdes-Garcia, Alberto and Nicolson, Sean and Lai, Jie-Wei and Natarajan, Arun and Chen, Ping-Yu and Reynolds, Scott and Zhan, Jing-Hong Conan and Floyd, Brian}, year={2010}, month={Feb}, pages={218–219} }
 @inproceedings{liu_chen_floyd_2010, title={An LTCC superstrate patch antenna for 60-GHz package applications}, ISBN={9781424449675 9781424449682}, url={http://dx.doi.org/10.1109/aps.2010.5561139}, DOI={10.1109/aps.2010.5561139}, abstractNote={The increasing capabilities of high speed silicon germanium (SiGe) and complementary metal–oxide–semiconductor (CMOS) technologies have made millimeter wave (mmWave) frequencies attractive for low-cost applications. An overview of the capabilities can be found in [1]. Promising applications could be high data rate wireless personal-area networks (WPAN) at 60 GHz [2], automotive radars at 76–77 GHz or 78–81 GHz [3], and imaging at 94 GHz [4]. These applications require small, low-profile, but high-performance packages at moderate to low cost. Such mmWave systems require not only highly-integrated radio frequency integrated circuits (RFICs), but also high-performance antennas. However, integrating an antenna into a package is not an easy task. The realization of a robust, efficient and broadband mmWave antenna within a plastic or multilayer organic (MLO) package is challenging due to assembly difficulties, limited material selection and manufacturing tolerances. In [5] we indicated that our cavity-backed folded dipole superstrate antenna has potential for integration with our 60-GHz SiGe chipset [1] in a plastic land-grid array (LGA) package [6]. This package concept includes a fused-silica substrate with antenna structures, a metal frame forming the cavity and providing the support for the fused- silica substrate, a package carrier to carry the radio frequency (RF) chip and the antenna assembly, and glob-top to protect the chip and the antenna. Although this package shows excellent performance, the assembly is still complicated and expensive. In [7], we proposed an aperture-coupled superstrate patch antenna with an embedded air cavity and an open cavity for antenna evaluation (possibly also for holding an RFIC chip). The antenna, based on printed circuit board (PCB) or MLO technology, provides high efficiency and wide bandwidth.}, booktitle={2010 IEEE Antennas and Propagation Society International Symposium}, publisher={IEEE}, author={Liu, Duixian and Chen, HoChung and Floyd, B}, year={2010}, month={Jul} }
 @inproceedings{kam_liu_natarajan_reynolds_floyd_2010, title={Low-cost antenna-in-package solutions for 60-GHz phased-array systems}, ISBN={9781424468652}, url={http://dx.doi.org/10.1109/epeps.2010.5642554}, DOI={10.1109/epeps.2010.5642554}, abstractNote={A low-cost, fully-integrated antenna-in-package solution for 60-GHz phased-array system is demonstrated. Sixteen patch antennas are integrated into a 28 mm × 28 mm ball grid array together with a flip-chip attached phased-array transmitter or receiver chip. The packages have first been fabricated using low temperature co-fired ceramic technology, and then built using conventional printed circuit board processes for lower manufacturing cost. Antenna chamber measurement has shown ∼5 dBi unit antenna gain across the 60-GHz frequency band covering all four IEEE 802.15.3c channels. The packaged transmitter and receiver chipsets, each mounted on an evaluation board, have demonstrated beam-steered, non-line-of-sight links with data rates up to 5.3 Gb/s.}, booktitle={19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems}, publisher={IEEE}, author={Kam, Dong Gun and Liu, Duixian and Natarajan, Arun and Reynolds, Scott and Floyd, Brian A.}, year={2010}, month={Oct}, pages={93–96} }
 @inproceedings{liu_floyd_2010, title={Microstrip to CPW transitions for package applications}, ISBN={9781424449675 9781424449682}, url={http://dx.doi.org/10.1109/aps.2010.5561028}, DOI={10.1109/aps.2010.5561028}, abstractNote={Microstrip (MS) transmission lines are widely used at RF, microwave and millimeter-wave (mmWave) frequencies in monolithic integrated-circuits (ICs), printed circuit boards, and planar antennas. At mmWave frequencies, RF transceivers typically use coplanar waveguide (CPW) pad structures. As a result, MS-to-CPW transitions are necessary to connect the antennas to the RF transceivers. Furthermore, to accurately evaluate these antennas at mmWave frequencies, MS-to-CPW transitions are required since CPW (i.e., ground-signal-ground (GSG)) probe-based measurement systems are used. Probe-based measurement systems avoid the use of connectors on antennas; therefore, de-embedding is not required. In fact, connectors are not used in many mmWave antenna designs.}, booktitle={2010 IEEE Antennas and Propagation Society International Symposium}, publisher={IEEE}, author={Liu, Duixian and Floyd, B}, year={2010}, month={Jul} }
 @inproceedings{floyd_valdes garcia_reynolds_natarajan_liu_gaucher_nakano_katayama_2010, title={Silicon millimeter-wave radios for 60 GHz and beyond}, ISBN={9781424450633}, url={http://dx.doi.org/10.1109/vtsa.2010.5488970}, DOI={10.1109/vtsa.2010.5488970}, abstractNote={This paper provides an overview of a 60 GHz transceiver chipset implemented in 0.12 μm SiGe BiCMOS technology, prototype 60 GHz antennas and packages developed for that chipset, and a 60 GHz phased-array receiver front-end. The transceiver chipset achieves 6 dB noise figure in the receiver and 10 dBm output compression point in the transmitter. Folded-dipole and patch antenna arrays developed for the 60 GHz chipset show >90% efficiencies and broad bandwidths. These antennas were attached to the SiGe RF chips, and the packaged chipset has been used to transmit an uncompressed high-definition video stream at 2 Gb/s, with even higher data rates possible. Finally, a 60 GHz RF-combined phased-array receiver front-end is discussed which uses a hybrid parallel/series phase-shifting architecture and which achieves full spatial coverage with reduced phase-shifter requirements.}, booktitle={Proceedings of 2010 International Symposium on VLSI Technology, System and Application}, publisher={IEEE}, author={Floyd, B. and Valdes Garcia, A. and Reynolds, S. and Natarajan, A. and Liu, D. and Gaucher, B. and Nakano, D. and Katayama, Y.}, year={2010}, month={Apr}, pages={12–13} }
 @inproceedings{natarajan_tsai_floyd_2009, title={60GHz RF-path phase-shifting two-element phased-array front-end in silicon}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-70449427639&partnerID=MN8TOARS}, booktitle={Symposium on VLSI Technology Digital Technology Papers}, author={Natarajan, A. and Tsai, M.D. and Floyd, B.}, year={2009}, month={Jun}, pages={250–251} }
 @inproceedings{liu_akkermans_floyd_2009, title={A superstrate patch antenna for 60-GHz applications}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-70349854864&partnerID=MN8TOARS}, booktitle={European Conference on Antennas and Propagation, EuCAP 2009, Proceedings}, author={Liu, D. and Akkermans, I. and Floyd, B.}, year={2009}, month={Mar}, pages={2592–2594} }
 @inbook{reynolds_valdes-garcia_floyd_katayama_natarajan_2009, title={Millimeter-Wave System Overview}, ISBN={9780470742969 9780470996171}, url={http://dx.doi.org/10.1002/9780470742969.ch16}, DOI={10.1002/9780470742969.ch16}, abstractNote={This chapter contains sections titled: Outlook for Low-cost, High-volume mmWave Systems Example:60 GHz SiGe Transceiver Demonstration Board for 60GHz SiGe Transceiver Transceiver ICs as Part of Larger Digital System Future Evolution References}, booktitle={Advanced Millimeter-Wave Technologies}, publisher={John Wiley & Sons, Ltd}, author={Reynolds, Scott K. and Valdes-Garcia, Alberto and Floyd, Brian A. and Katayama, Yasunao and Natarajan, Arun}, year={2009}, month={Feb}, pages={709–727} }
 @article{floyd_2008, title={A 16–18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers}, volume={43}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2008.920351}, DOI={10.1109/jssc.2008.920351}, abstractNote={An 18-GHz range frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz superheterodyne transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 16.0 to 18.8 GHz, while the enabled RF frequency range is 3.5 times this, or 55.8 to 65.8 GHz. The measured RMS phase noise of the synthesizer is 0.8deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are 69 dBc; sub-integer spurs are -65 dBc; and combined power consumption from 1.2 and 2.7 V is 144 mW.}, number={5}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, Brian A.}, year={2008}, month={May}, pages={1076–1086} }
 @inproceedings{natarajan_nicolson_tsai_floyd_2008, title={A 60GHz variable-gain LNA in 65nm CMOS}, ISBN={9781424426041}, url={http://dx.doi.org/10.1109/asscc.2008.4708743}, DOI={10.1109/asscc.2008.4708743}, abstractNote={A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.}, booktitle={2008 IEEE Asian Solid-State Circuits Conference}, publisher={IEEE}, author={Natarajan, Arun and Nicolson, Sean and Tsai, Ming-Da and Floyd, Brian}, year={2008}, month={Nov}, pages={117–120} }
 @inbook{niknejad_emami_heydari_adabi_afshar_floyd_2008, title={Amplifiers and Mixers}, ISBN={9780387765587 9780387765617}, ISSN={1558-9412}, url={http://dx.doi.org/10.1007/978-0-387-76561-7_4}, DOI={10.1007/978-0-387-76561-7_4}, abstractNote={The key performance requirements of the 60 GHz low-noise amplifier (LNA) are power gain, noise figure, linearity, stability, impedance matching, power dissipation, bandwidth, and design robustness to process/voltage/temperature variation. These basic requirements are universal for LNAs, and as will be shown, the basic design methodologies at 60 GHz are not all that different than those at much lower frequencies. The circuit topologies, however, will be different to account for the three fundamental differences of 60 GHz design compared to lower frequency design, which are (1) designing using transistors operating much closer to their cutoff frequencies, (2) operating with signals with small wavelengths resulting in distributed effects within actual components of the circuit, and (3) designing with parasitic elements which represent a much larger portion of the total impedance or admittance on a given node. The implications of these three differences are now briefly discussed, and then illustrated through circuit examples later on in the chapter.}, booktitle={Series on Integrated Circuits and Systems}, publisher={Springer US}, author={Niknejad, Ali M. and Emami, Sohrab and Heydari, Babak and Adabi, Ehsan and Afshar, Bagher and Floyd, Brian A.}, year={2008}, pages={109–157} }
 @article{floyd_2008, title={Sub-Integer Frequency Synthesis Using Phase-Rotating Frequency Dividers}, volume={55}, ISSN={1549-8328 1558-0806}, url={http://dx.doi.org/10.1109/tcsi.2008.918077}, DOI={10.1109/tcsi.2008.918077}, abstractNote={A generalized architecture and theory for realizing multimodulus, sub-integer frequency division is developed by extending the phase-switched divider technique. The sub-integer divider consists of a pre-scaler, a phase rotator, a post-sealer, and a modulus controller. Phase rotation is proposed as an effective technique to realize fine phase resolution and thereby low sub-integer division ratios, as well as to eliminate the glitch which has plagued phase-switched dividers. Program-swallowed counters are used as the modulus controller to realize a broad-range multimodulus divider. Expressions are derived for the range and resolution of such a program-swallowed, phase-rotating divider. Furthermore, the fractional spurs from this divider topology are derived and related to the linearity of the phase rotator. It is shown that very low (-60 to -75 dBc) fractional spurs at the output of the divider can be attained with reasonably accurate phase rotators. The benefit of this technique is in the ability to realize sub-integer frequency synthesizers which have the architectural simplicity of standard integer-N PLLs, but the finer frequency resolution capabilities due to sub-integer division.}, number={7}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, B.A.}, year={2008}, month={Aug}, pages={1823–1833} }
 @inproceedings{katayama_haymes_nakano_beukema_floyd_reynolds_pfeiffer_gaucher_schleupen_2007, title={2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link}, ISBN={1424406676}, url={http://dx.doi.org/10.1109/ccnc.2007.10}, DOI={10.1109/ccnc.2007.10}, abstractNote={We report a proof-of-concept demonstration of 2- Gbps uncompressed HDTV transmission using a 60-GHz SiGe radio chipset. We took a single-carrier approach with a usual DQPSK modulation scheme, assuming an LOS environment, and implemented the system with FPGAs. At the same time, in order to take care of more frequent sync/burst errors in high-data-rate single-carrier approaches, we equipped the baseband with effi- cient random/packet error recovery and symbol-timing recovery with an effective interpolation method. As a result, a clear and crisp image was obtained in the end-to-end transmission. I. INTRODUCTION}, booktitle={2007 4th IEEE Consumer Communications and Networking Conference}, publisher={IEEE}, author={Katayama, Y. and Haymes, C. and Nakano, D. and Beukema, T. and Floyd, B. and Reynolds, S. and Pfeiffer, U. and Gaucher, B. and Schleupen, K.}, year={2007}, month={Jan}, pages={12–16} }
 @inproceedings{floyd_2007, title={A 15 to 18-GHz Programmable Sub-Integer Frequency Synthesizer for a 60-GHz Transceiver}, ISBN={1424405300}, url={http://dx.doi.org/10.1109/rfic.2007.380939}, DOI={10.1109/rfic.2007.380939}, abstractNote={A 15 to 18-GHz frequency synthesizer is implemented in 0.13-mum SiGe BiCMOS technology as part of a 60-GHz transceiver chipset. It provides for RF channels of 56.5-64 GHz in 500-MHz steps, and features a phase-rotating multi-modulus divider capable of sub-integer division. Output frequency range from the synthesizer is 15.3 to 18 GHz. The measured RMS phase noise of the synthesizer is 0.9deg (1 MHz to 1 GHz integration), while phase noise at 100-kHz and 10-MHz offsets are -90 and -124 dBc/Hz, respectively. Reference spurs are -69 dBc; sub-integer spurs are -65 dBc; and power consumption is 145 mW.}, booktitle={2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium}, publisher={IEEE}, author={Floyd, Brian A.}, year={2007}, month={Jun}, pages={529–532} }
 @inproceedings{natarajan_floyd_hajimiri_2007, title={A Bidirectional RF-Combining 60GHz Phased-Array Front-End}, ISBN={1424408520 1424408539}, ISSN={0193-6530}, url={http://dx.doi.org/10.1109/isscc.2007.373364}, DOI={10.1109/isscc.2007.373364}, abstractNote={A 60GHz RF-combining phased-array front-end is implemented in silicon using a hybrid parallel/series phase-shift approach that reduces the requirements of the on-chip phase shifters. The 4-element array provides for simultaneous illumination of 2 angles of incidence and includes amplitude control and continuous phase adjustment. The front-end NF <6.9dB at 60GHz and the array achieves full spatial coverage with peak-to-null ratio >25dB. It consumes 265mW and occupies 4.6mm2.}, booktitle={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers}, publisher={IEEE}, author={Natarajan, Arun and Floyd, Brian and Hajimiri, Ali}, year={2007}, month={Feb}, pages={202–204} }
 @inproceedings{reynolds_valdes-garcia_floyd_beukema_gaucher_liu_hoivik_orner_2007, title={Second Generation 60-GHz Transceiver Chipset Supporting Multiple Modulations at Gb/s data rates (Invited)}, ISBN={9781424410187 9781424410194}, ISSN={1088-9299}, url={http://dx.doi.org/10.1109/bipol.2007.4351867}, DOI={10.1109/bipol.2007.4351867}, abstractNote={A feature-rich second-generation 60-GHz transceiver chipset is introduced. It integrates dual-conversion superheterodyne receiver and transmitter chains, a sub-integer frequency synthesizer, full programmability from a digital interface, modulator and demodulator circuits to support analog modulations (e.g. MSK, BPSK), as well as a universal I&Q interface for digital modulation formats (e.g. OFDM). Achieved performance includes 6-dB receiver noise figure and 12 dBm transmitter output ldB compression point. Wireless link experiments with different modulation formats for 2-Gb/s real-time uncompressed HDTV transmission are discussed. Additionally, recent millimeter-wave package and antenna developments are summarized and a 60GHz silicon micromachined antenna is presented.}, booktitle={2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting}, publisher={IEEE}, author={Reynolds, Scott and Valdes-Garcia, Alberto and Floyd, Brian and Beukema, Troy and Gaucher, Brian and Liu, Duixian and Hoivik, Nils and Orner, Bradley}, year={2007}, month={Sep}, pages={192–197} }
 @inproceedings{floyd_gaucher_reynolds_valdes-garcia_pfeiffer_liu_grzyb_hoivik_jagannathan_2007, title={SiGe vs. CMOS for 60-100 GHz: technology, circuits, packages, and systems}, booktitle={Government Microcircuit Applications Conference Digital Papers}, author={Floyd, B. and Gaucher, B. and Reynolds, S. and Valdes-Garcia, A. and Pfeiffer, U. and Liu, D. and Grzyb, J. and Hoivik, N. and Jagannathan, B.}, year={2007}, month={Mar}, pages={31–34} }
 @inproceedings{floyd_pfeiffer_reynolds_valdes-garcia_haymes_katayama_nakano_beukema_gaucher_soyuer_et al._2007, title={Silicon Millimeter-Wave Radio Circuits at 60-100 GHz}, ISBN={0780397649 0780397657}, url={http://dx.doi.org/10.1109/smic.2007.322823}, DOI={10.1109/smic.2007.322823}, abstractNote={This paper reviews silicon millimeter-wave radio circuits operating between 60 and 100GHz. Transmitter and receiver chips operating in the 60-GHz ISM band are highlighted, where the packaged chipset has shown data rates as high as 2 Gb/s over 5m for a wireless high-definition video link. In addition, a 60GHz PA with 23dBm output power and a class-E 60GHz PA with >20% peak PAE are reviewed. Finally, 77 and 94GHz downconverters are presented as a basis for an outlook to the performance achievable at these higher frequency bands}, booktitle={2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems}, publisher={IEEE}, author={Floyd, B. and Pfeiffer, U. and Reynolds, S. and Valdes-Garcia, A. and Haymes, C. and Katayama, Y. and Nakano, D. and Beukema, T. and Gaucher, B. and Soyuer, M. and et al.}, year={2007}, month={Jan}, pages={213–218} }
 @inproceedings{pfeiffer_grzyb_liu_gaucher_beukema_floyd_reynolds_2006, title={A 60GHz Radio Chipset Fully-Integrated in a Low-Cost Packaging Technology}, volume={2006}, ISBN={1424401526}, url={http://dx.doi.org/10.1109/ectc.2006.1645830}, DOI={10.1109/ectc.2006.1645830}, abstractNote={We present a cost-effective plastic packaging technology for a fully-integrated 60GHz radio, used for communication in the 60GHz ISM band. The chipset supports 1-3 Gbps directional links using a ASK or PSK modulation, or it can be used in 500Mbps-1Gbps omni-directional links using an OFDM modulation. The antenna is integrated inside of the package and does not require any high-frequency external connection. The fabrication process of a direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. Both packages are robust against variations of the electrical properties of standard plastic mold materials}, booktitle={56th Electronic Components and Technology Conference 2006}, publisher={IEEE}, author={Pfeiffer, U. and Grzyb, J. and Liu, D. and Gaucher, B. and Beukema, T. and Floyd, B. and Reynolds, S.}, year={2006}, month={Jul}, pages={1343–1346} }
 @article{reynolds_floyd_pfeiffer_beukema_grzyb_haymes_gaucher_soyuer_2006, title={A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications}, volume={41}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2006.884820}, DOI={10.1109/jssc.2006.884820}, abstractNote={A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated}, number={12}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Reynolds, Scott K. and Floyd, Brian A. and Pfeiffer, Ullrich R. and Beukema, Troy and Grzyb, Janusz and Haymes, Chuck and Gaucher, Brian and Soyuer, Mehmet}, year={2006}, month={Dec}, pages={2820–2831} }
 @article{pfeiffer_grzyb_liu_gaucher_beukema_floyd_reynolds_2006, title={A chip-scale packaging technology for 60-GHz wireless chipsets}, volume={54}, ISSN={0018-9480}, url={http://dx.doi.org/10.1109/tmtt.2006.877832}, DOI={10.1109/tmtt.2006.877832}, abstractNote={In this paper, we present a cost-effective chip-scale packaging solution for a 60-GHz industrial-scientific-medical band receiver (Rx) and transmitter (Tx) chipset capable of gigabit-per-second wireless communications. Envisioned applications of the packaged chipset include 1-3-Gb/s directional links using amplitude shift-keying or phase shift-keying modulation and 500-Mb/s-1-Gb/s omni-directional links using orthogonal frequency-division multiplexing modulation. This paper demonstrates the first fully package-integrated 60-GHz chipset including receive and transmit antennas in a cost-effective plastic package. A direct-chip-attach (DCA) and surface mountable land-grid-array (LGA) package technology is presented. The size of the DCA package is 7times11 mm2 and the LGA package size is 6times13 mm2. Optionally, the Tx and Rx chip can be packaged together with Tx and Rx antennas in a combined 13times13 mm2 LGA transceiver package}, number={8}, journal={IEEE Transactions on Microwave Theory and Techniques}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Pfeiffer, U.R. and Grzyb, J. and Liu, Duixian and Gaucher, B. and Beukema, T. and Floyd, B.A. and Reynolds, S.K.}, year={2006}, month={Aug}, pages={3387–3397} }
 @inproceedings{floyd_reynolds_pfeiffer_beukema_grzyb_haymes_2006, title={A silicon 60GHz receiver and transmitter chipset for broadband communications}, ISBN={1424400791}, url={http://dx.doi.org/10.1109/isscc.2006.1696103}, DOI={10.1109/isscc.2006.1696103}, abstractNote={An integrated SiGe superheterodyne RX/TX pair capable of Gb/s data rates in the 60GHz band is described. The 6dB NF RX includes an image-reject LNA, a multistage down-converter with on-chip IF filters, a frequency tripler, a PLL, and baseband outputs. The 10 to 12dBm P1dBTX achieves 10% PAE in the final stage. It includes a PA, image-reject driver, multistage up-converter with on-chip filters, tripler, and PLL}, booktitle={2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers}, publisher={IEEE}, author={Floyd, B. and Reynolds, S. and Pfeiffer, U. and Beukema, T. and Grzyb, J. and Haymes, C.}, year={2006} }
 @inproceedings{bhatia_kim_chuang_rosenbaum_plouchart_floyd_2006, title={Double-Gate FET Technology for RF Applications: Device Characteristics and Low Noise Amplifier Design}, ISBN={1424402891 1424402905}, ISSN={1078-621X}, url={http://dx.doi.org/10.1109/soi.2006.284440}, DOI={10.1109/soi.2006.284440}, abstractNote={Previous works have established that double-gate FET (DGFET) technology provides improved digital circuit performance relative to bulk CMOS (Nowak et al., 2004) and (Kim et al., 2005). However, the benefits of DGFET technology for analog/RF circuits have not been thoroughly analyzed. In this work, we use two-dimensional, mixed-mode simulations to compare the performance of low noise amplifier (LNA) circuits built using DGFET and bulk CMOS devices}, booktitle={2006 IEEE international SOI Conferencee Proceedings}, publisher={IEEE}, author={Bhatia, Karan and Kim, Keunwoo and Chuang, Ching-te and Rosenbaum, Elyse and Plouchart, Jean-olivier and Floyd, Brian}, year={2006}, month={Oct}, pages={75–76} }
 @inproceedings{chirala_floyd_2006, title={Millimeter-Wave Lange and Ring-Hybrid Couplers in a Silicon Technology for E-Band Applications}, ISBN={0780395417}, url={http://dx.doi.org/10.1109/mwsym.2006.249609}, DOI={10.1109/mwsym.2006.249609}, abstractNote={Five compact millimeter-wave 90deg and 180deg distributed couplers are realized in the back-end-of-the-line of a 0.13mum SiGe BiCMOS technology. Lange couplers smaller than 160 mum on a side have been implemented showing -4 dB through, -5 dB coupling, 14 dB return loss, and 15 dB isolation for 60- and 77-GHz versions. Ring hybrids with phase-inverters have been implemented showing -4 dB through, -5.6 dB coupling, 18 dB return loss, and 21 dB isolation for 60- and 77-GHz versions. The rings are smaller than 330 mum on a side}, booktitle={2006 IEEE MTT-S International Microwave Symposium Digest}, publisher={IEEE}, author={Chirala, Mohan K. and Floyd, Brian A.}, year={2006}, month={Jun}, pages={1547–1550} }
 @inproceedings{gaucher_reynolds_floyd_pfeiffer_beukema_joseph_mina_orner_wachnik_walter_et al._2006, title={Progress in SiGe Technology Toward Fully Integrated mmWave ICs}, volume={2006}, ISBN={1424404614}, url={http://dx.doi.org/10.1109/istdm.2006.246556}, DOI={10.1109/istdm.2006.246556}, abstractNote={We described newly developed, enhanced technology and enablement features that lead to state of the art mmwave ICs capable of meeting Gbps speeds required of emerging applications. Die photographs of the Rx and Tx are shown in (Floyd, 2006). The die sizes are 3.4times1.7mm2 and 4.0times1.6mm2, respectively}, booktitle={2006 International SiGe Technology and Device Meeting}, publisher={IEEE}, author={Gaucher, B. and Reynolds, S. and Floyd, B. and Pfeiffer, U. and Beukema, T. and Joseph, A. and Mina, E. and Orner, B. and Wachnik, R. and Walter, K. and et al.}, year={2006} }
 @inproceedings{reynolds_floyd_pfeiffer_beukema_zwick_grzyb_liu_gaucher_2006, title={Progress toward a low-cost millimeter-wave silicon radio}, volume={2005}, ISBN={0780390237}, url={http://dx.doi.org/10.1109/cicc.2005.1568731}, DOI={10.1109/cicc.2005.1568731}, abstractNote={This paper discusses the circuits, packaging, and antennas needed to realize a low-cost millimeter-wave transceiver with integrated antenna in silicon technology. The principal application envisioned is in high-speed 60-GHz wireless networks, but the concepts may be applicable to other products as well, such as 77-GHz radar sensors. Circuit results are presented for both 60 and 77 GHz, including an LNA, a highly-integrated direct downconverter, a mixer for a superheterodyne receiver, and a power amplifier. Packaging issues which arise at millimeter-wave frequencies are discussed, and a packaging approach involving a Si IC and a planar antenna in the same package is described. Measurement results for a planar Vivaldi antenna are presented as an example.}, booktitle={Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005.}, publisher={IEEE}, author={Reynolds, S.K. and Floyd, B.A. and Pfeiffer, U.R. and Beukema, T.J. and Zwick, T. and Grzyb, J. and Liu, D. and Gaucher, B.P.}, year={2006}, month={Jan}, pages={563–570} }
 @inproceedings{jagannathan_groves_goren_floyd_greenberg_wagner_csutak_lee_coolbaugh_pekarik_et al._2006, title={RF CMOS for microwave and MM-wave applications}, volume={2006}, ISBN={0780394720}, url={http://dx.doi.org/10.1109/smic.2005.1587964}, DOI={10.1109/smic.2005.1587964}, abstractNote={RF CMOS is gaining significant momentum as the technology of choice for implementing product designs in the 1-10GHz band. With scaling pushing fT and fMAX of FET's beyond 300GHz and integration of back-end-of-line (BEOL) conducive to low-loss passives, CMOS is poised to address application needs in the X, K and V bands}, booktitle={Digest of Papers. 2005 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2005.}, publisher={IEEE}, author={Jagannathan, B. and Groves, R. and Goren, D. and Floyd, B. and Greenberg, D. and Wagner, L. and Csutak, S. and Lee, Sungjae and Coolbaugh, D. and Pekarik, J. and et al.}, year={2006}, month={Feb}, pages={259–264} }
 @inproceedings{floyd_gaucher_2006, title={SiGe ICs for gigabit wireless transmission}, author={Floyd, B. and Gaucher, B.}, year={2006}, month={Aug} }
 @inproceedings{o_kim_floyd_mehta_yoon_hung_bravo_dickson_guo_li_et al._2006, title={Silicon Integrated Circuits Incorporating Antennas}, ISBN={1424400767 1424400759}, url={http://dx.doi.org/10.1109/cicc.2006.320824}, DOI={10.1109/cicc.2006.320824}, abstractNote={The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. This technology can potentially be used for intra and inter-chip interconnection, and implementation of true single chip radios, beacons, radars, RFID tags and others, as well as contact-less high frequency testing}, booktitle={IEEE Custom Integrated Circuits Conference 2006}, publisher={IEEE}, author={O, K. and Kim, K. and Floyd, B. and Mehta, J. and Yoon, H. and Hung, C.-m. and Bravo, D. and Dickson, T. and Guo, X. and Li, R. and et al.}, year={2006}, month={Sep}, pages={473–480} }
 @inproceedings{gaucher_floyd_reynolds_pfeiffer_joseph_mina_orner_wachnik_walters_2006, title={Silicon germanium based millimeter wave IC’s for Gbps wireless communication and radar systems}, booktitle={Government Microcircuit Applications Conference Digital Papers}, author={Gaucher, B. and Floyd, B. and Reynolds, S. and Pfeiffer, U. and Joseph, A. and Mina, E. and Orner, B. and Wachnik, R. and Walters, K.}, year={2006}, month={Mar} }
 @article{gaucher_floyd_reynolds_pfeiffer_grzyb_joseph_mina_orner_ding_wachnik_et al._2006, title={Silicon germanium based millimetre-wave ICs for Gbps wireless communications and radar systems}, volume={22}, ISSN={0268-1242 1361-6641}, url={http://dx.doi.org/10.1088/0268-1242/22/1/s55}, DOI={10.1088/0268-1242/22/1/S55}, abstractNote={This paper establishes the viability and suitability of silicon germanium (SiGe8HP) technology, enablement tools and circuits to millimetre-wave applications today and a roadmap to the future. Key elements discussed include SiGe technology and design enablement advancements leading to the world's most highly integrated, lowest power 60 GHz transmitter/receiver ICs.}, number={1}, journal={Semiconductor Science and Technology}, publisher={IOP Publishing}, author={Gaucher, B and Floyd, B and Reynolds, S and Pfeiffer, U and Grzyb, J and Joseph, A and Mina, E and Orner, B and Ding, H and Wachnik, R and et al.}, year={2006}, month={Dec}, pages={S236–S243} }
 @article{rylov_reynolds_storaska_floyd_kapur_zwick_gowda_sorna_2005, title={10+ gb/s 90-nm CMOS serial link demo in CBGA package}, volume={40}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2005.848177}, DOI={10.1109/jssc.2005.848177}, abstractNote={We report a 10+ Gb/s serial link demo chip with NRZ signaling in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. All coefficients of the 8-tap FIR filter have programmable polarity and magnitude. The chip is housed in CBGA package and has ESD protection devices on all pins. All clock signals are supplied externally. The measured maximum speeds of stand-alone transmitter and receiver are 11.7 Gb/s and 13.3 Gb/s, respectively, and maximum back-to-back operation speed (transmitter + receiver) is 11.4 Gb/s. The chip operates at 10 Gb/s over 20 ft of lossy cable with 20 dB attenuation at 5 GHz. All circuits in the chip use a single 1.0 V power supply, except TX output driver and RX input termination network, which use 1.4 V supply. Total power consumption of TX and RX from the two supplies is 280 mW.}, number={9}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Rylov, S. and Reynolds, S. and Storaska, D. and Floyd, B. and Kapur, M. and Zwick, T. and Gowda, S. and Sorna, M.}, year={2005}, month={Sep}, pages={1987–1991} }
 @article{reynolds_floyd_beukema_zwick_pfeiffer_2005, title={Design and Compliance Testing of a SiGe WCDMA Receiver IC With Integrated Analog Baseband}, volume={93}, ISSN={0018-9219}, url={http://dx.doi.org/10.1109/jproc.2005.852229}, DOI={10.1109/jproc.2005.852229}, abstractNote={A 2.7-3.3 V 32-mA SiGe direct-conversion wide-band code division multiple access (WCDMA) receiver IC integrating the RF front-end and analog baseband on a single chip has been completed and measured. Analog performance specifications for the design were driven by the 3GPP specifications. To close the loop from 3GPP specifications to IC design specifications to hardware performance results, a subset of compliance tests for both the analog as well as the digital 3GPP specifications was performed. The IC design includes a bypassable low-noise amplifier (LNA), a quadrature direct-downconverter, an automatically tuned channel-select filter, wide dynamic-range baseband amplifiers, and a serial digital interface. Power-saving modes allow the LNA to be powered down when the input signal is sufficiently large, reducing current consumption to 23 mA. In addition, the entire Q-channel signal path can be optionally powered down during control-channel monitoring, further reducing current draw to 17 mA nominal. The IC showed full compliance with the static channel 3GPP specification tests performed, including all analog/RF compliance tests and a set of DPCH/spl I.bar/Ec/Ior sensitivity tests from 12.2 through 384 kb/s as measured with a software baseband processor.}, number={9}, journal={Proceedings of the IEEE}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Reynolds, S.K. and Floyd, B.A. and Beukema, T.J. and Zwick, T. and Pfeiffer, U.R.}, year={2005}, month={Sep}, pages={1624–1636} }
 @inproceedings{gaucher_beukema_reynolds_floyd_zwick_pfeiffer_liu_cressler_2005, title={MM-wave transceivers using SiGe HBT technology}, ISBN={0780387031}, url={http://dx.doi.org/10.1109/smic.2004.1398172}, DOI={10.1109/smic.2004.1398172}, abstractNote={High-speed wireless technology has been evolving with roughly 2/spl times/ speed improvements every 18 months. Currently the wireless local-area network (WLAN) and wireless personal-area network (WPAN) spaces are developing new standards to increase wireless speeds beyond the 10-54 Mbit/s achieved in the first and second generation IEEE wireless network standards. Challenging issues which must be addressed in these new high-rate standards include FCC restrictions on maximum radiated power and power spectral density, bandwidth limitations in the available 2.4 and 5 GHz ISM bands, and cost and power required to support the high date rates in portable devices. This paper discusses the realization of a mm-wave transceiver in advanced SiGe HBT technology for application in high-speed mm-wave wireless systems. A low-power, integrated 60 GHz transceiver opens up the potential for economical high-speed wireless systems which can take advantage of >5 GHz of unlicensed spectrum available in the 60 GHz ISM band.}, booktitle={Digest of Papers. 2004 Topical Meeting onSilicon Monolithic Integrated Circuits in RF Systems, 2004.}, publisher={IEEE}, author={Gaucher, B. and Beukema, T. and Reynolds, S. and Floyd, B. and Zwick, T. and Pfeiffer, U. and Liu, D. and Cressler, J.}, year={2005}, month={Mar} }
 @article{o_kim_floyd_mehta_yoon_hung_bravo_dickson_guo_li_et al._2005, title={On-Chip Antennas in Silicon ICs and Their Application}, volume={52}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/ted.2005.850668}, DOI={10.1109/ted.2005.850668}, abstractNote={The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals, and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single-chip radio for general purpose communication, on-chip and inter-chip data communication systems, RFID tags, RF sensors/radars, and others.}, number={7}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={O, K.K. and Kim, K. and Floyd, B.A. and Mehta, J.L. and Yoon, H. and Hung, C.-M. and Bravo, D. and Dickson, T.O. and Guo, X. and Li, R. and et al.}, year={2005}, month={Jul}, pages={1312–1323} }
 @article{floyd_reynolds_pfeiffer_zwick_beukema_gaucher_2005, title={SiGe bipolar transceiver circuits operating at 60 GHz}, volume={40}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2004.837250}, DOI={10.1109/jssc.2004.837250}, abstractNote={A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.}, number={1}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, B.A. and Reynolds, S.K. and Pfeiffer, U.R. and Zwick, T. and Beukema, T. and Gaucher, B.}, year={2005}, month={Jan}, pages={156–167} }
 @inproceedings{pfeiffer_goren_floyd_reynolds_2005, title={SiGe transformer matched power amplifier for operation at millimeter-wave frequencies}, ISBN={0780392051}, url={http://dx.doi.org/10.1109/esscir.2005.1541579}, DOI={10.1109/esscir.2005.1541579}, abstractNote={In this paper, a transformer matched power amplifier for operation at millimeter-wave frequencies is presented. The SiGe single-stage push-pull amplifier uses a stacked transformer above a ground shield for output matching. The millimeter-wave transformer has a high coupling factor k = 0.8 and provides a very compact circuit layout. At 61.5 GHz the class-AB biased amplifier achieves a power gain of 12 dB with 8.5 dBm output power at a 1 dB compression. The saturated output power was measured up to P/sub sat/ = 14 dBm with a maximum PAE of 4.2%.}, booktitle={Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.}, publisher={IEEE}, author={Pfeiffer, U.R. and Goren, D. and Floyd, B.A. and Reynolds, S.K.}, year={2005}, month={Dec}, pages={141–144} }
 @inproceedings{o_kim_floyd_mehta_yoon_hung_bravo_dickson_guo_li_et al._2005, title={The feasibility of on-chip interconnection using antennas}, volume={2005}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-33751428417&partnerID=MN8TOARS}, DOI={10.1109/ICCAD.2005.1560204}, abstractNote={The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction of transmitted and received signals with nearby circuits appear to be manageable. Besides, on-chip interconnection, this technology can potentially be applied for implementation of true single chip radio and radar, interchip communication systems, RFID tags and others.}, booktitle={IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD}, author={O, K.K. and Kim, K. and Floyd, B. and Mehta, J. and Yoon, H. and Hung, C.-M. and Bravo, D. and Dickson, T. and Guo, X. and Li, R. and et al.}, year={2005}, pages={976–981} }
 @inproceedings{o_kim_floyd_2005, title={The feasibility of on-chip interconnection using antennas}, author={O, K.K. and Kim, K. and Floyd, B.}, year={2005}, month={Nov}, pages={979–984} }
 @article{floyd_reynolds_zwick_khuon_beukema_pfeiffer_2005, title={WCDMA direct-conversion receiver front-end comparison in RF-CMOS and SiGe BiCMOS}, volume={53}, ISSN={0018-9480}, url={http://dx.doi.org/10.1109/tmtt.2005.845742}, DOI={10.1109/tmtt.2005.845742}, abstractNote={Wide-band code-division multiple-access direct-conversion receiver front-ends have been implemented in both 0.25-/spl mu/m RF-CMOS and SiGe BiCMOS technologies. These circuits have been designed for the same application, radio architecture, and system specifications, allowing relevant comparisons to be made. The front-ends include a bypassable low-noise amplifier, a quadrature downconverter, baseband variable-gain amplifiers, and a local-oscillator frequency divider with output buffers. At 24.5 mA of total current consumption from a 2.7-3.3-V supply, the CMOS front-end has a noise figure of 5.3 dB, in-band third-order intercept point (IIP3) and second-order intercept point (IIP2) of -14 and +20.7 dBm, respectively, and out-of-band IIP3 and IIP2 of >+1.2 and +69 dBm, respectively. Compared to an SiGe front-end consuming 22 mA, the CMOS circuit has a 2-dB higher noise figure, comparable out-of-band linearity, 3-dB higher in-band IIP3, 12-dB lower in-band IIP2, and 7-dB higher LO-to-RF leakage.}, number={4}, journal={IEEE Transactions on Microwave Theory and Techniques}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, B.A. and Reynolds, S.K. and Zwick, T. and Khuon, L. and Beukema, T. and Pfeiffer, U.R.}, year={2005}, month={Apr}, pages={1181–1188} }
 @inproceedings{rylov_reynolds_storaska_floyd_kapur_zwick_gowda_sorna_2004, title={10+ Gb/s 90nm CMOS serial link demo in CBGA package}, ISBN={0780384954}, url={http://dx.doi.org/10.1109/cicc.2004.1358725}, DOI={10.1109/cicc.2004.1358725}, abstractNote={We report a 10+ Gb/s serial link demo chip in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. The chip is housed in CBGA package and uses ESD devices on all pins. The measured maximum speed of stand-alone transmitter and receiver was 11.7 Gb/s and 13.3 Gb/s respectively, and maximum back-to-back operation speed (transmitter+receiver) was 11.4 Gb/s.}, booktitle={Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571)}, publisher={IEEE}, author={Rylov, S. and Reynolds, S. and Storaska, D. and Floyd, B. and Kapur, M. and Zwick, T. and Gowda, S. and Sorna, M.}, year={2004}, month={Nov}, pages={27–30} }
 @inproceedings{reynolds_floyd_pfeiffer_zwick_2004, title={60GHz transceiver circuits in SiGe bipolar technology}, volume={47}, ISBN={0780382676}, url={http://dx.doi.org/10.1109/isscc.2004.1332784}, DOI={10.1109/isscc.2004.1332784}, abstractNote={A 60GHz LNA, direct-downconverter, PA, and 20GHz VCO are built in a 200GHz f/sub t/,/f/sub max/, 0.12/spl mu/m SiGe technology. The 10.8mW LNA has 15dB gain, 3.4-4.4dB noise figure and -8.5dBm IIP3. The down converter has 16dB gain, >50dB LO-RF isolation, and 13.4-14.8dB noise figure. The PA delivers 10dBm at 9dB gain.}, booktitle={2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)}, publisher={IEEE}, author={Reynolds, S. and Floyd, B. and Pfeiffer, U. and Zwick, T.}, year={2004}, month={Sep} }
 @inproceedings{pfeiffer_reynolds_floyd_2004, title={A 77 GHz SiGe power amplifier for potential applications in automotive radar systems}, ISBN={0780383338}, url={http://dx.doi.org/10.1109/rfic.2004.1320535}, DOI={10.1109/rfic.2004.1320535}, abstractNote={We present the performance of a 77 GHz power amplifier for potential applications directed towards automotive radar systems. The circuit was fabricated in a SiGe bipolar preproduction technology. A balanced two-stage common emitter circuit topology was used to achieve 6.1 dB of power gain at 77 GHz and 11.6 dBm output power at 1dB compression. The power amplifier uses a single 2.5 V supply and was fully integrated (including matching elements) to demonstrate its low-cost potential. First experimental results show its broadband characteristic from 40 GHz to 80 GHz and its temperature dependence up to 130/spl deg/C.}, booktitle={2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers}, publisher={IEEE}, author={Pfeiffer, U.R. and Reynolds, S.K. and Floyd, B.A.}, year={2004}, month={Sep}, pages={91–94} }
 @inproceedings{floyd_ozis_2004, title={Low-noise amplifier comparison at 2 GHz in 0.25-μm and 0.18-μm RF-CMOS and SiGe BiCMOS}, ISBN={0780383338}, url={http://dx.doi.org/10.1109/rfic.2004.1320566}, DOI={10.1109/rfic.2004.1320566}, abstractNote={Low-noise amplifiers (LNA) have been designed and implemented in 0.25-/spl mu/m and 0.18-/spl mu/m SiGe BiCMOS and RF-CMOS technologies. The LNA have been designed for the same WCDMA application and system specifications, allowing meaningful comparisons to be made. This paper presents the design methodology for these bipolar and CMOS switched-gain LNA and compares the simulated and measured results. A bypass switch topology is also presented. The results show that each technology can meet WCDMA LNA specifications. Measurements show noise figures of 1.4, 1.7, and 1.1 dB for LNA implemented in 0.25-/spl mu/m SiGe BiCMOS, 0.25-/spl mu/m CMOS, and 0.18-/spl mu/m SiGe BiCMOS, respectively. These LNA show 14 to 16 dB of gain and +3 to +4-dBm out-of-band IIP3 at 5 to 6 mA current from 3 V. Of these three measured LNA, the 0.18-/spl mu/m bipolar shows the best performance; however, simulations of a 0.18-/spl mu/m RF-CMOS LNA show further improved IIP3.}, booktitle={2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers}, publisher={IEEE}, author={Floyd, B.A. and Ozis, D.}, year={2004}, month={Sep}, pages={185–188} }
 @inproceedings{gaucher_beukema_reynolds_floyd_zwick_pfeiffer_liu_cressler_2004, title={MM-wave transceivers using SiGe HBT technology}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-20344405688&partnerID=MN8TOARS}, booktitle={2004 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems: Digest of Papers}, author={Gaucher, B. and Beukema, T. and Reynolds, S. and Floyd, B. and Zwick, T. and Pfeiffer, U. and Liu, D. and Cressler, J.}, year={2004}, pages={81–84} }
 @article{kuo_lu_floyd_haugerud_sutton_krithivasan_cressler_gaucher_marshall_reed_et al._2004, title={Proton radiation response of monolithic Millimeter-wave transceiver building blocks implemented in 200 GHz SiGe technology}, volume={51}, ISSN={0018-9499}, url={http://dx.doi.org/10.1109/tns.2004.839215}, DOI={10.1109/tns.2004.839215}, abstractNote={This work presents the first experimental results on the effects of 63.3 MeV proton irradiation on 60 GHz monolithic point-to-point broadband space data link transceiver building blocks implemented in a 200 GHz SiGe heterojunction bipolar transistor (HBT) technology. A SiGe low-noise amplifier and a SiGe voltage-controlled oscillator were each irradiated to proton fluences of 5.0/spl times/10/sup 13/ p/cm/sup 2/. The device and circuit level performance degradation associated with these extreme proton fluences is found to be minimal, suggesting that such SiGe HBT transceivers should be robust from a proton tolerance perspective for space applications, without intentional hardening at either the device or circuit level.}, number={6}, journal={IEEE Transactions on Nuclear Science}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Kuo, Wei-Min Lance and Lu, Yuan and Floyd, B.A. and Haugerud, B.M. and Sutton, A.K. and Krithivasan, R. and Cressler, J.D. and Gaucher, B.P. and Marshall, P.W. and Reed, R.A. and et al.}, year={2004}, month={Dec}, pages={3781–3787} }
 @inproceedings{floyd_2004, title={V-band and W-band SiGe bipolar low-noise amplifiers and voltage-controlled oscillators}, ISBN={0780383338}, url={http://dx.doi.org/10.1109/rfic.2004.1320601}, DOI={10.1109/rfic.2004.1320601}, abstractNote={LNAs and VCOs operating between 50 and 86 GHz have been implemented using a 0.12-/spl mu/m, 200-GHz SiGe bipolar technology. Unbalanced LNAs at 50, 60, and 77 GHz show /spl sim/15 dB of gain, drawing 2, 6, and 8 mA from 1.8 V, respectively. The iCP/sub 1dB/ for the LNAs are from -17 to -20 dBm. The noise figure of the 60-GHz LNA is 4.5 dB. Balanced amplifiers composed of two parallel LNAs with branch-line couplers at the input, and output have also been demonstrated at 60 and 77 GHz, showing 14 and 12-dB gain, respectively. Differential Colpitts VCOs have been implemented at 53, 67, and 85 GHz. Phase noises at a 1-MHz offset are -100, -98, and -94 dBc/Hz, respectively, while tuning ranges are 3.7%, 3.1%, and 2.7%. Each VCO consumes roughly 25 mW, and provides -8 dBm output power to 100 /spl Omega/ differential.}, booktitle={2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers}, publisher={IEEE}, author={Floyd, B.A.}, year={2004}, month={Sep}, pages={295–298} }
 @inbook{reynolds_floyd_beukema_zwick_pfeiffer_ainspan_2004, place={Piscataway, NJ : Hoboken, NJ}, edition={2}, title={Wireless Design: A Direct Conversion Receiver IC for WCDMA Mobile Systems}, volume={4}, ISBN={978-0-471-44653-8}, booktitle={Silicon germanium: technology, modeling, and design}, publisher={IEEE Press ; Wiley-Interscience}, author={Reynolds, S. and Floyd, B. and Beukema, T. and Zwick, T. and Pfeiffer, U. and Ainspan, H.}, year={2004}, pages={271–295} }
 @inproceedings{o_kim_floyd_mehta_yoon_hung_bravo_dickson_guo_li_et al._2004, title={Wireless communications using integrated antennas}, ISBN={0780377974}, url={http://dx.doi.org/10.1109/iitc.2003.1219727}, DOI={10.1109/iitc.2003.1219727}, abstractNote={The feasibility of integrating antennas and required circuits to form wireless interconnects in foundry digital CMOS technologies has been demonstrated. The key challenges including the effects of metal structures associated with integrated circuits, heat removal, packaging, and interaction between transmitted and received signals and nearby circuits appear to be manageable. This technology can potentially be applied for implementation of a true single chip radio, on-chip and inter-chip communication systems, RFID tags, and others.}, booktitle={Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695)}, publisher={IEEE}, author={O, K.K. and Kim, K. and Floyd, B. and Mehta, J. and Yoon, H. and Hung, C.-M. and Bravo, D. and Dickson, T. and Guo, X. and Li, R. and et al.}, year={2004}, month={Mar}, pages={111–113} }
 @inproceedings{reynolds_floyd_pfeiffer_zwick_2003, title={60GHz transceiver circuits in SiGe bipolar technology}, volume={47}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-2442715211&partnerID=MN8TOARS}, booktitle={Digest of Technical Papers - IEEE International Solid-State Circuits Conference}, author={Reynolds, S. and Floyd, B. and Pfeiffer, U. and Zwick, T.}, year={2003} }
 @inproceedings{floyd_mehta_gamero_kenneth_2003, title={A 900-MHz, 0.8-μm CMOS low noise amplifier with 1.2-dB noise figure}, ISBN={0780354435}, url={http://dx.doi.org/10.1109/cicc.1999.777367}, DOI={10.1109/cicc.1999.777367}, abstractNote={A 900-MHz single-stage low noise amplifier (LNA), requiring one external inductor and matched to 50-/spl Omega/ at both the input and output, has been implemented in a standard digital 0.8-/spl mu/m CMOS technology. Measured noise figures for the LNA in package are 2 dB at 6.2 mW, 1.78 dB at 8.1 mW, 1.5 dB at 13.2 mW, and 1.2 dB at 30 mW. At 30 mW and V/sub DD/=3.0 V, the LNA has a power gain of 14.5 dB, and an IIP3 of -1 dBm. At 6.2 mW and V/sub DD/=2.7 V, the LNA has a power gain of 9.4 dB, and an IIP3 of -3.8 dBm.}, booktitle={Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)}, publisher={IEEE}, author={Floyd, B.A. and Mehta, J. and Gamero, C. and Kenneth, K.O.}, year={2003}, month={Jan} }
 @article{reynolds_floyd_beukema_zwick_pfeiffer_ainspan_2003, title={A direct-conversion receiver IC for WCDMA mobile systems}, volume={38}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/jssc.2003.815914}, DOI={10.1109/jssc.2003.815914}, abstractNote={A prototype design of a 2.7-3.3-V 14.5-mA SiGe direct-conversion receiver IC for use in third-generation wide-band code-division multiple-access (3G WCDMA) mobile cellular systems has been completed and measured. The design includes a bypassable low-noise amplifier (LNA), a quadrature downconverter, a local-oscillator frequency divider and quadrature generator, and variable-gain baseband amplifiers integrated on chip. The design achieves a cascaded, LNA-referred noise figure (including an interstage surface acoustic wave filter) of 4.0 dB, an in-band IIP3 of -18.6 dBm, and local-oscillator leakage at the LNA input of -112 dBm. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.}, number={9}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Reynolds, S.K. and Floyd, B.A. and Beukema, T. and Zwick, T. and Pfeiffer, U. and Ainspan, H.}, year={2003}, month={Sep}, pages={1555–1560} }
 @inproceedings{reynolds_floyd_beukema_zwick_pfeiffer_ainspan_2003, title={A direct-conversion receiver IC for WCDMA mobile systems}, ISBN={0780375610}, url={http://dx.doi.org/10.1109/bipol.2002.1042887}, DOI={10.1109/bipol.2002.1042887}, abstractNote={A prototype design of a 2.7 V, 14.5 mA SiGe direct-conversion receiver IC for use in 3G WCDMA mobile cellular systems has been completed and measured. The design includes a bypassable LNA, a quadrature downconverter, and variable gain baseband amplifiers integrated on chip. The static sensitivity performance of the receiver IC is characterized using a software baseband processor to compute link bit-error rate.}, booktitle={Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting}, publisher={IEEE}, author={Reynolds, S. and Floyd, B. and Beukema, T. and Zwick, T. and Pfeiffer, U. and Ainspan, H.}, year={2003}, month={Jun} }
 @article{reynolds_floyd_beukema_zwick_pfeiffer_ainspan_2003, title={A direct-conversion receiver integrated circuit for WCDMA mobile systems}, volume={47}, ISSN={0018-8646 0018-8646}, url={http://dx.doi.org/10.1147/rd.472.0337}, DOI={10.1147/rd.472.0337}, abstractNote={A prototype of a 3-V SiGe direct-conversion receiver integrated circuit for use in third-generation (3G) WCDMA mobile cellular systems has been completed. The goal of its design was to minimize current draw while meeting WCDMA receiver rf specifications with margin. The design includes a bypassable low-noise amplifier, quadrature downconverter, and first-stage variable-gain baseband amplifiers integrated on chip. The design is optimized for use with a single-ended off-chip bandpass surface-acoustic-wave filter with no external matching components. The prototype design represents a first step toward a fully integrated monolithic WCDMA/UMTS receiver system-on-a-chip. A rigorous set of performance tests are used to characterize the noise and linearity performance of the packaged IC across its full frequency band of operation. A receiver test-bed system with a software baseband demodulator is used to determine the bit-error-rate performance of the receiver integrated circuit (IC) at sensitivity. Measured results are compared with estimated system performance requirements to determine compliance with key WCDMA rf specifications.}, number={2.3}, journal={IBM Journal of Research and Development}, publisher={IBM}, author={Reynolds, S. K. and Floyd, B. A. and Beukema, T. J. and Zwick, T. and Pfeiffer, U. R. and Ainspan, H. A.}, year={2003}, month={Mar}, pages={337–353} }
 @inproceedings{dickson_floyd_o_2003, title={Jitter in a wireless clock distribution system}, ISBN={0780372166}, url={http://dx.doi.org/10.1109/iitc.2002.1014917}, DOI={10.1109/iitc.2002.1014917}, abstractNote={The jitter of a transmitted wireless clock signal has been measured and found to behave much like jitter of conventionally distributed clock signals. Noise from nearby digital circuits can degrade receiver sensitivity by reducing LNA gain and shifting the divider self-oscillation frequency. This increases clock jitter and, in extreme conditions, can cause failure in the clock receiver circuits to lock on to the transmitted clock signal. The clock can be re-locked by increasing the transmitted power.}, booktitle={Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519)}, publisher={IEEE}, author={Dickson, T. and Floyd, B. and O, K.}, year={2003}, month={Jun}, pages={154–156} }
 @inproceedings{guo_caserta_li_floyd_o_2003, title={Propagation layers for intra-chip wireless interconnection compatible with packaging and heat removal}, ISBN={078037312X}, url={http://dx.doi.org/10.1109/vlsit.2002.1015378}, DOI={10.1109/vlsit.2002.1015378}, abstractNote={Inserting an aluminum nitride (AlN) layer which acts as a dielectric propagating medium between a silicon wafer containing integrated antennas and a metal chuck emulating the role of a heat sink improves the antenna power transmission gain by /spl sim/8 dB at 15 GHz. AlN, with its high thermal conductivity, also alleviates the heat removal problem. With a 760-/spl mu/m AlN layer, an on-chip wireless connection is demonstrated over a 2.2-cm distance, which is 3/spl times/ the previously reported separation.}, booktitle={2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)}, publisher={IEEE}, author={Guo, Xiaoling and Caserta, J. and Li, R. and Floyd, B. and O, K.O.}, year={2003}, month={Jun} }
 @inproceedings{gaucher_beukema_reynolds_floyd_zwick_pfeiffer_liu_2003, title={Silicon monolithic broadband millimeter wave radio technology}, booktitle={International Conference on Space Mission Challenges for Information Technology}, author={Gaucher, B. and Beukema, T. and Reynolds, S. and Floyd, B. and Zwick, T. and Pfeiffer, U. and Liu, D.}, year={2003}, month={Jun}, pages={113–121} }
 @inproceedings{floyd_o_2003, title={The projected power consumption of a wireless clock distribution system and comparison to conventional distribution systems}, ISBN={0780351746}, url={http://dx.doi.org/10.1109/iitc.1999.787135}, DOI={10.1109/iitc.1999.787135}, abstractNote={A wireless interconnect system has been proposed for global clock signal distribution. The system transmits and receives signals at 20 GHz or higher. The received signal is then amplified, frequency divided to 4 GHz or lower, and buffered to provide a clock signal to the local clock distribution system. An analysis comparing the projected power dissipation of a wireless clock distribution system to conventional grid-based and H-tree based distribution systems for 0.1 /spl mu/m generation microprocessors is performed, based on the total capacitive loading of the global distribution system. The results show that in terms of power dissipation, the wireless clock distribution system should be comparable to conventional systems.}, booktitle={Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247)}, publisher={IEEE}, author={Floyd, B.A. and O, K.K.}, year={2003}, month={Jan}, pages={248–250} }
 @inproceedings{kim_ho_floyd_wann_taur_lagnado_2002, title={4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 μm CMOS technology on SOI and SOS substrates}, ISBN={0780343441}, url={http://dx.doi.org/10.1109/isscc.1998.672405}, DOI={10.1109/isscc.1998.672405}, abstractNote={CMOS is a viable contender for front-end receiver circuits in the frequency range between 0.9 and 2 GHz. As gate lengths decrease to 0.1 /spl mu/m and below, this frequency range will increase, potentially opening up applications such as wireless LANs in the 5-20 GHz range. These 4 GHz and 13 GHz CMOS tuned amplifiers are implemented with partially-depleted silicon on insulator (SOI) and silicon on sapphire (SOS) nMOS transistors with floating bodies. Measured forward gains (S21) for the 4 GHz SOS and SOI amplifiers are 12 and 11 dB, respectively, and 15 and 5.3 dB for the 13 GHz SOS and SOI amplifiers. The 13 GHz amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. The CMOS process uses 0.35 /spl mu/m design rules for all dimensions except for the 0.1 /spl mu/m gate length and 2.9 nm gate oxide thickness. The nMOS transistors have -100 GHz measured peak f/sub T/. Threshold voltages are 0.2 and 0.4 V for the SOS and SOI transistors, respectively.}, booktitle={1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156)}, publisher={IEEE}, author={Kim, K.-H. and Ho, Y.-C. and Floyd, B. and Wann, C. and Taur, Y. and Lagnado, I.}, year={2002}, month={Nov} }
 @inproceedings{floyd_hung_kenneth_2002, title={A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas}, ISBN={4891140143}, url={http://dx.doi.org/10.1109/vlsic.2001.934225}, DOI={10.1109/vlsic.2001.934225}, abstractNote={Using a 6-metal, copper 0.18-/spl mu/m CMOS technology, a 15-GHz on-chip wireless interconnect system has been demonstrated. The transmission frequency and distance (5.6 mm) of on-chip wireless interconnection have been almost doubled compared to the previously reported system. In addition, an integrated transmitter for on-chip wireless interconnection has been demonstrated. Lastly, the RF potential of CMOS technology for >10 GHz is assessed.}, booktitle={2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)}, publisher={Japan Soc. Appl. Phys}, author={Floyd, B.A. and Hung, Chih-Ming and Kenneth, K.O.}, year={2002}, month={Nov} }
 @article{floyd_shi_taur_lagnado_o_2002, title={A 23.8-GHz SOI CMOS tuned amplifier}, volume={50}, ISSN={0018-9480}, url={http://dx.doi.org/10.1109/tmtt.2002.802334}, DOI={10.1109/tmtt.2002.802334}, abstractNote={A 23.8-GHz tuned amplifier is demonstrated in a partially scaled 0.1-/spl mu/m silicon-on-insulator CMOS technology. The fully integrated three-stage amplifier employs a common-gate, source-follower, and cascode with on-chip spiral inductors and MOS capacitors. The gain is 7.3 dB, while input and output reflection coefficients are -45 and -9.4 dB, respectively. Positive gain is exhibited beyond 26 GHz. The amplifier draws 53 mA from a 1.5-V supply. The measured on-wafer noise figure is 10 dB, while the input-referred third-order intercept point is -7.8 dBm. The results demonstrate that 0.1-/spl mu/m CMOS technology may be used for 20-GHz RF applications and suggest even higher operating frequencies and better performance for further scaled technologies.}, number={9}, journal={IEEE Transactions on Microwave Theory and Techniques}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, B.A. and Shi, L. and Taur, Yuan and Lagnado, I. and O, K.K.}, year={2002}, month={Sep}, pages={2193–2196} }
 @inproceedings{reynolds_floyd_beukema_zwick_pfeiffer_ainspan_2002, title={A direct-conversion receiver IC for WCDMA mobile systems}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0036437922&partnerID=MN8TOARS}, booktitle={Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting}, author={Reynolds, S. and Floyd, B. and Beukema, T. and Zwick, T. and Pfeiffer, U. and Ainspan, H.}, year={2002}, pages={61–64} }
 @inproceedings{hung_floyd_o_2002, title={A fully integrated 5.35-GHz CMOS VCO and a prescaler}, ISBN={0780362802}, url={http://dx.doi.org/10.1109/rfic.2000.854419}, DOI={10.1109/rfic.2000.854419}, abstractNote={A 5.35-GHz monolithic VCO and a prescaler have been fabricated in a 0.25-/spl mu/m CMOS process. The VCO has a tuning range of 336 MHz and phase noise of -117 dBc/Hz at a 1-MHz offset and 7-mW power consumption. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescaler utilizes a variation of the source coupled logic and consumes only 4.1 mW at VDD=1.5 V and 5.4 GHz. A second prescaler operating at 9.96 GHz and 2.5-V VDD is also demonstrated.}, booktitle={2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)}, publisher={IEEE}, author={Hung, Chih-Ming and Floyd, B.A. and O, K.K.}, year={2002}, month={Nov} }
 @inproceedings{bravo_yoon_kim_floyd_o_2002, title={Estimation of the signal-to-noise ratio for on-chip wireless clock signal distribution (year 2000)}, ISBN={0780363272}, url={http://dx.doi.org/10.1109/iitc.2000.854082}, DOI={10.1109/iitc.2000.854082}, abstractNote={The achievable signal-to-noise ratio for an 18-GHz wireless clock distribution system has been estimated by extrapolating from the current status of the clock receiver, the integrated antenna performance, and the understanding of noise sources and coupling mechanisms. It is estimated that a SNR of /spl sim/23 dB is achievable at the input of the frequency divider within the clock receiver block.}, booktitle={Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)}, publisher={IEEE}, author={Bravo, D. and Yoon, Hyun and Kim, Kihong and Floyd, B. and O, K.K.}, year={2002}, month={Nov}, pages={9–11} }
 @article{floyd_hung_o_2002, title={Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters}, volume={37}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/4.997846}, DOI={10.1109/4.997846}, abstractNote={A wireless interconnect system which transmits and receives RF signals across a chip using integrated antennas, receivers, and transmitters is proposed and demonstrated. The transmitter consists of a voltage-controlled oscillator, an output amplifier, and an antenna, while the receiver consists of an antenna, a low-noise amplifier, a frequency divider, and buffers. Using a 0.18-/spl mu/m CMOS technology, each of these individual circuits is demonstrated at 15 GHz. Wireless interconnection for clock distribution is then demonstrated in two stages. First, a wireless transmitter with integrated antenna generates and broadcasts a 15-GHz global clock signal across a 5.6-mm test chip, and this signal is detected using receiving antennas. Second, a wireless clock receiver with an integrated antenna detects a 15-GHz global clock signal supplied to an on-chip transmitting antenna located 5.6 mm away from the receiver, and generates a 1.875-GHz local clock signal. This is the first known demonstration of an on-chip clock transmitter with an integrated antenna and the second demonstration of a clock receiver with an integrated antenna, where the receiver's frequency and interconnection distance have approximately been doubled over previous results.}, number={5}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Floyd, B.A. and Hung, Chih-Ming and O, K.K.}, year={2002}, month={May}, pages={543–552} }
 @inproceedings{guo_caserta_li_floyd_o_2002, title={Propagation layers for intra-chip wireless interconnection compatible with packaging and heat removal}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0036057339&partnerID=MN8TOARS}, booktitle={IEEE Symposium on VLSI Circuits, Digest of Technical Papers}, author={Guo, X. and Caserta, J. and Li, R. and Floyd, B. and O, K.K.}, year={2002}, pages={36–37} }
 @inproceedings{floyd_hung_o_2002, title={The effects of substrate resistivity on RF component and circuit performance}, ISBN={0780363272}, url={http://dx.doi.org/10.1109/iitc.2000.854313}, DOI={10.1109/iitc.2000.854313}, abstractNote={The benefits of using high-resistivity substrates for RF CMOS applications are experimentally quantified. The quality factors of spiral inductors with a patterned ground shield, varactors, and transistors have been measured on both p/sup +/ (with epi) and p/sup -/ substrates, and in each case, Q is higher on p/sup $/substrates. A 5.35-GHz VCO on a p-substrate has an 8 dB lower phase noise than that on a p/sup +/ substrate, while a 7-GHz LNA on a p/sup -/ substrate has a 6 dB higher gain and /spl sim/2.5 dB lower noise figure than that on a p/sup +/ substrate.}, booktitle={Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407)}, publisher={IEEE}, author={Floyd, B.A. and Hung, Chih-Ming and O, K.K.}, year={2002}, month={Nov}, pages={164–166} }
 @inproceedings{floyd_guo_caserta_dickson_hung_kim_o_2002, title={Wireless Interconnects for Clock Distribution}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0141989608&partnerID=MN8TOARS}, DOI={10.1145/589411.589433}, abstractNote={A wireless interconnect system for clock distribution which transmits and receives microwave signals across a chip using integrated antennas, receivers, and transmitters is presented. All of the com-ponents of the system are demonstrated at 15 GHz in a 0.18-m CMOS technology. Wireless interconnection is achieved over a distance of 5.6 mm.}, booktitle={ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems}, author={Floyd, B.A. and Guo, X. and Caserta, J. and Dickson, T. and Hung, C.-M. and Kim, K. and O, K.K.}, year={2002}, pages={105–108} }
 @inproceedings{floyd_kim_kenneth_2002, title={Wireless interconnection in a CMOS IC with integrated antennas}, ISBN={0780358538}, url={http://dx.doi.org/10.1109/isscc.2000.839802}, DOI={10.1109/isscc.2000.839802}, abstractNote={Improved RF capability and projected increase in die size for CMOS circuits lead to the concept of wireless communications within and between chips. A potential application is wireless clock distribution, proposed as an alternative interconnect system capable of distributing high frequency clock signals at the speed of light using microwaves. The wireless clock distribution system consists of a clock transmitter, located on or off chip, broadcasting a microwave global clock signal at frequencies greater than 15 GHz, and a grid of integrated clock receivers. The global clock signal is received using an integrated dipole antenna. The signal is then amplified using a low-noise amplifier (LNA), frequency divided down to the local clock frequency, buffered, and distributed to provide local clock signals. This IC operating at 7.4 GHz, which integrates antennas and necessary receiver circuits in 0.25 /spl mu/m CMOS with five metal layers on p-substrates, is a first step towards realizing such a system.}, booktitle={2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)}, publisher={IEEE}, author={Floyd, B. and Kim, K. and Kenneth, O.}, year={2002}, month={Nov} }
 @inproceedings{floyd_hung_kenneth_2001, title={A 15-GHz wireless interconnect implemented in a 0.18-μm CMOS technology using integrated transmitters, receivers, and antennas}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0034796094&partnerID=MN8TOARS}, number={CIRCUITS SYMP.}, booktitle={IEEE Symposium on VLSI Circuits, Digest of Technical Papers}, author={Floyd, B.A. and Hung, C.-M. and Kenneth, K.O.}, year={2001}, pages={155–158} }
 @article{hung_floyd_park_kenneth_2001, title={Fully integrated 5.35-GHz CMOS VCOs and prescalers}, volume={49}, ISSN={0018-9480}, url={http://dx.doi.org/10.1109/22.899957}, DOI={10.1109/22.899957}, abstractNote={Two 5.35-GHz monolithic voltage-controlled oscillators (VCOs) and two prescalers have been fabricated in a digital 0.25-/spl mu/m CMOS process. One VCO uses p/sup +//n-well diodes, while the other uses MOS varactors, Q of 57 at 5.5 GHz and 0 V bias (low-Q condition) for a p/sup +//n-well varactor has been achieved. For an MOS varactor, it is possible to achieve a quality factor of 140 at 5.5 GHz. The tuning ranges of the VCOs are >310 MHz, and their phase noise is <-116.5 dBc/Hz at a 1-MHz offset while consuming /spl sim/7 mW power at V/sub DD/=1.5 V. The low phase noise is achieved by using only PMOS transistors in the VCO core and by optimizing the resonator layout. The prescalers utilize a variation of the source-coupled logic. The power consumption is 4.1 mW at 1.5-V V/sub DD/ and 5.4 GHz. By widening the transistors in the first three divide-by-two stages, the maximum operating frequency is increased to 9.96 GHz at V/sub DD/=2.5 V.}, number={1}, journal={IEEE Transactions on Microwave Theory and Techniques}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hung, C.-M. and Floyd, B.A. and Park, N. and Kenneth, K.O.}, year={2001}, pages={17–22} }
 @article{floyd_shi_taur_lagnado_o_2001, title={SOI and bulk CMOS frequency dividers operating above 15 GHz}, volume={37}, ISSN={0013-5194}, url={http://dx.doi.org/10.1049/el:20010446}, DOI={10.1049/el:20010446}, abstractNote={Dual-phase dynamic pseudo-NMOS ([DP]/sup 2/) frequency dividers have been implemented in a partially scaled 0.1 /spl mu/m CMOS technology. For 4:1 dividers on silicon-on-insulator (SOI) and bulk substrates, the maximum speed, power consumption, and extracted [DP]/sup 2/ latch delays are 18.75 and 15.4 GHz, 13.5 and 9.8 mW and 13.3 and 16.2 ps, respectively, at 1.5 V.}, number={10}, journal={Electronics Letters}, publisher={Institution of Engineering and Technology (IET)}, author={Floyd, B.A. and Shi, L. and Taur, Y. and Lagnado, I. and O, K.K.}, year={2001}, pages={617} }
 @inproceedings{hung_floyd_o_2000, title={Fully integrated 5.35-GHz CMOS VCO and a prescaler}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0033715978&partnerID=MN8TOARS}, booktitle={Digest of papers - IEEE Radio Frequency Integrated Circuits Symposium}, author={Hung, Chih-Ming and Floyd, Brian A. and O, Kenneth K.}, year={2000}, pages={69–72} }
 @inproceedings{floyd_kim_o_2000, title={Wireless interconnection in a CMOS IC with integrated antennas}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0034429612&partnerID=MN8TOARS}, booktitle={Digest of Technical Papers - IEEE International Solid-State Circuits Conference}, author={Floyd, B. and Kim, K. and O, K.}, year={2000}, pages={328–329} }
 @inproceedings{floyd_mehta_gamero_o_1999, title={900-MHz, 0.8-μm CMOS low noise amplifier with 1.2-dB noise figure}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0032597705&partnerID=MN8TOARS}, booktitle={Proceedings of the Custom Integrated Circuits Conference}, author={Floyd, Brian A. and Mehta, Jesal and Gamero, Carlos and O, Kenneth K.}, year={1999}, pages={661–664} }
 @inproceedings{o_kim_floyd_mehta_yoon_1999, title={Inter and intra-chip wireless clock signal distribution using microwaves: a status of a feasibility study}, booktitle={Government Microcircuit Applications Conference Digital Papers}, author={O, K.K. and Kim, K. and Floyd, B.A. and Mehta, J. and Yoon, H.}, year={1999}, month={Mar}, pages={306–309} }
 @inproceedings{kim_ho_floyd_wann_taur_lagnado_o_1998, title={4 GHz and 13 GHz tuned amplifiers implemented in a 0.1 μm CMOS technology on SOI and SOS substrates}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-0031704599&partnerID=MN8TOARS}, booktitle={Digest of Technical Papers - IEEE International Solid-State Circuits Conference}, author={Kim, K.-H. and Ho, Y.-C. and Floyd, B. and Wann, C. and Taur, Y. and Lagnado, I. and O, K.}, year={1998}, pages={134–135, 425} }
 @article{ho_kim_floyd_wann_taur_lagnado_o_1998, title={4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates}, volume={33}, ISSN={0018-9200}, url={http://dx.doi.org/10.1109/4.735548}, DOI={10.1109/4.735548}, abstractNote={Four- and 13-GHz tuned amplifiers have been implemented in a partially scaled 0.1-1 /spl mu/m CMOS technology on bulk, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS) substrates. The 4-GHz bulk, SOI, and SOS amplifiers exhibit forward gains of 14, 11, and 12.5 dB and F/sub min/'s of 4.5 (bulk) and 3.5 db (SOS). The 13-GHz SOS and SOI amplifiers exhibit gains of 15 and 5.3 dB and F/sub unn/'s of 4.9 and 7.8 dB. The 4-GHz bulk amplifier has the highest resonant frequency among reported bulk CMOS amplifiers, while the 13-GHz SOS and SOI amplifiers are the first in a CMOS technology to have tuned frequencies greater than 10 GHz. These and other measurement results suggest that it may be possible to implement 20-GHz tuned amplifiers in a fully scaled 0.1-1 /spl mu/m CMOS process.}, number={12}, journal={IEEE Journal of Solid-State Circuits}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ho, Yo-Chuol and Kim, Ki-Hong and Floyd, B.A. and Wann, C. and Taur, Yuan and Lagnado, I. and O, K.K.}, year={1998}, pages={2066–2073} }
 @inproceedings{o_kim_floyd_ho_hung_wann_taur_lagnado_1998, title={Tuned amplifiers fabricated in a 0.1-um CMOS technology on bulk, SOI, and SOS substrates}, booktitle={Government Microcircuit Applications Conference Digital Papers}, author={O, K.K. and Kim, K. and Floyd, B. and Ho, Y.-C. and Hung, C.-M. and Wann, C. and Taur, Y. and Lagnado, I.}, year={1998}, month={Mar}, pages={175–178} }