@article{parashar_kolli_kokkonda_kanale_bhattacharya_baliga_2024, title={Mitigating Voltage Imbalance Across Series-Connected 10 kV SiC JBS Diodes in a Medium-Voltage High-Power 3L-NPC Converter}, volume={39}, ISSN={["1941-0107"]}, url={https://doi.org/10.1109/TPEL.2023.3339809}, DOI={10.1109/TPEL.2023.3339809}, abstractNote={This article presents a design methodology for RC snubbers to address dynamic voltage imbalance in series-connected 10 kV SiC junction barrier Schottky (JBS) diodes, utilized in a 3-level (3L) neutral point clamped (NPC) converter. The proposed method considers the effect of bus bar inductance, unequal diode junction capacitance, baseplate capacitance, and common mode (CM) choke tied between the heat sink and midpoint of the dc link capacitor on snubber losses and turn-off voltage mismatch across series-connected diodes. In addition, the effect of hard-switched turn-on across complementary SiC mosfets has been considered on snubber loss and dynamic voltage balancing across SiC JBS diodes. The following steps have been used to simplify the RC snubber design: modeling the switching transition across series-connected 10 kV SiC JBS diodes and 10 kV SiC mosfets on two-level clamped inductive switching test setup, modification of snubber capacitor and switching transition model for 3L-NPC topology, using the experimental data, and modification of snubber resistor using experimental data from 3L-NPC setup with CM choke. Key design parameters obtained from the proposed model have been compared with the experimentally obtained data, which validates the accuracy of the model. Experimental results at the 7 kV dc bus show that the designed RC snubber constrains the turn-off voltage mismatch, snubber loss, and turn-on transition time within the specified limit.}, number={3}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Parashar, Sanket and Kolli, Nithin and Kokkonda, Raj Kumar and Kanale, Ajit and Bhattacharya, Subhashish and Baliga, Jay}, year={2024}, month={Mar}, pages={2896–2911} }
 @inproceedings{narwal_rawat_kanale_cheng_agarwal_bhattacharya_baliga_hopkins_2023, title={Analysis and Characterization of Four-quadrant Switches based Commutation Cell}, volume={2023-March}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec43580.2023.10131312}, DOI={10.1109/APEC43580.2023.10131312}, abstractNote={A four-quadrant switch (FQS) blocks either polarity voltage and controls current flow in both directions. Unlike voltage-source converters, in which two-quadrant switches operate over a narrow voltage range, four-quadrant switches are required to operate over a wide range of both voltage and current in applications such as matrix converters and current-source converters. Furthermore, matrix converters require multi-step commutation schemes compared to two-step schemes for current-bidirectional switch based voltage-source converters and voltage-bidirectional switch based current-source converters. This paper provides a generalized overview of commutation schemes used for two and four quadrant switches based two-level commutation cells, identifies comparison indices for FQS commutation schemes, and discusses the need for adaptive commutation-step times for wide voltage and current variation applications. Also, the static and dynamic characteristics of 1.2 kV rated FQS implementations utilizing commercial SiC MOSFETs from four different manufacturers and novel monolithic SiC BiDirectional Field Effect Transistor (BiDFET) have been reported.}, booktitle={2023 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Narwal, Ramandeep and Rawat, Shubham and Kanale, Ajit and Cheng, Tzu-Hsuan and Agarwal, Aditi and Bhattacharya, Subhashish and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2023}, month={Mar}, pages={209–216} }
 @article{narwal_bhattacharya_baliga_hopkins_2023, title={Bidirectional Three-phase Current Source Converter based Buck-boost AC/DC System using Bidirectional Switches}, ISSN={["2473-7631"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85168253560&partnerID=MN8TOARS}, DOI={10.1109/ITEC55900.2023.10186945}, abstractNote={The 1.2 kV 4H-SiC BiDirectional Field Effect Transistor (BiDFET) is the first monolithic SiC bidirectional switch, which offers a lower voltage drop and semiconductor devices count alternative to the reverse-voltage-blocking (RB) switch used in the current-source converters (CSC). The bidirectional switch based CSC also allows DC-link current reversal for bidirectional power flow and provides multiple system-level benefits in a buck-boost AC/DC system consisting of buck-type DC/DC converter and CSC. This paper discusses the selection of buck converter duty cycle and CSC modulation index for the system's buck-boost operation with a wide variation in DC voltage. CSC modulation schemes categorized based on the number of hard-turn-on transitions per switching cycle are also analyzed along with the three-step and four-step commutation schemes that are essential for the CSC commutation cells. Finally, the different schemes are evaluated and compared through the experimental results of a 10 kW, 480 $\mathbf{V}_{\mathbf{RMS},\mathbf{LL}}/$ (400 - 800) V AC/DC system.}, journal={2023 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE & EXPO, ITEC}, author={Narwal, Ramandeep and Bhattacharya, Subhashish and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2023} }
 @article{narasimhan_kanale_bhattacharya_baliga_2023, title={Performance Evaluation of 3.3 kV SiC MOSFET and Schottky Diode Based Reverse Voltage Blocking Switch for Medium Voltage Current Source Inverter Application}, volume={11}, ISSN={["2169-3536"]}, url={https://doi.org/10.1109/ACCESS.2023.3302916}, DOI={10.1109/ACCESS.2023.3302916}, abstractNote={SiC power devices are used for medium-voltage (MV) motor drive and traction applications due to their higher temperature operation, switching frequencies, and higher efficiencies than Si-based devices. This article investigates three 3.3 kV reverse blocking or current switch configurations for their suitability in MV current-source inverter (CSI) applications. The three configurations are 1) Type I - SiC MOSFET and series Schottky diode; 2) Type II - SiC MOSFETs connected in common-source (CS); and 3) Type III - SiC MOSFETs connected in common-drain (CD) configuration. The switch configurations are characterized by comparing their on-state and switching performance at different junction temperatures varying from 25°C to 125°C. The results are used to evaluate three-phase CSI losses with three different switch configurations and choose the preferred switch configuration for MV-based CSI applications based on inverter efficiency while considering a wide range of operating points. The permissible limits of a 3.3 kV Type I switch-based CSI are presented, thus providing a safe operating area (SOA) of the switch configuration for a CSI application. Finally, the CSI is built using Type I switch configuration and is experimentally validated with an R-L load.}, journal={IEEE ACCESS}, author={Narasimhan, Sneha and Kanale, Ajit and Bhattacharya, Subhashish and Baliga, Jayant B.}, year={2023}, pages={89277–89289} }
 @article{bhattacharya_narwal_shah_baliga_agarwal_kanale_han_hopkins_cheng_2023, title={Power Conversion Systems Enabled by SiC BiDFET Device}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237060}, DOI={10.1109/MPEL.2023.3237060}, abstractNote={The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Bhattacharya, Subhashish and Narwal, Ramandeep and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Agarwal, Aditi and Kanale, Ajit and Han, Kijeong and Hopkins, Douglas C. and Cheng, Tzu-Hsuan}, year={2023}, month={Mar}, pages={39–43} }
 @article{baliga_2023, title={Silicon Carbide Power Devices: Progress and Future Outlook}, volume={11}, ISSN={["2168-6785"]}, DOI={10.1109/JESTPE.2023.3258344}, abstractNote={Silicon carbide (SiC) power devices have become commercialized and are being adopted for many applications after 40 years of effort to produce large diameter wafers and high-performance device structures. This article provides a historical perspective of the key breakthroughs that were needed to make progress toward this goal. The junction-barrier-Schottky (JBS) rectifier concept was a critical innovation required to make SiC power Schottky rectifiers viable. The Baliga-Pair or cascode concept was an intermediate step to realize a practical SiC power switch in the 1990 s. An essential unique innovation created in the 1990 s was the shielded planar SiC power MOSFET structure that is now commonly used for commercial products. Shielded trench-gate SiC power MOSFETs were also proposed in the 1990 s, which led to commercial products in the last five years. Although achieving a low specific ON-resistance in SiC power MOSFETs was essential at the inception of the technology, its penetration into power electronics applications is now driven by performance metrics for high-frequency circuits. Device structural enhancements to improve the high-frequency figures of merit are described that have led to major strides in performance. This includes the JBSFET concept where a JBS diode is integrated into the MOSFET structure to suppress current flow through the body diode; the split-gate (SG) and buffered-gate (BG) MOSFET structures that reduce the gate–drain charge; and the OCTFET structure where the gate–drain overlap area is reduced. Future developments in SiC power devices include increasing the blocking voltage rating to expand the applications spectrum. In addition, a SiC monolithic bidirectional switch has been demonstrated to allow implementation of matrix converters, and a SiC monolithic reverse blocking switch has been demonstrated to allow deployment of current source inverters (CSIs).}, number={3}, journal={IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS}, author={Baliga, B. Jayant}, year={2023}, month={Jun}, pages={2400–2411} }
 @article{baliga_hopkins_bhattacharya_agarwal_cheng_narwal_kanale_shah_han_2023, title={The BiDFET Device and Its Impact on Converters}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237059}, DOI={10.1109/MPEL.2023.3237059}, abstractNote={The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable d.c. link capacitors used in the popular voltage-source inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish and Agarwal, Aditi and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Kanale, Ajit and Shah, Suyash Sushilkumar and Han, Kijeong}, year={2023}, month={Mar}, pages={20–27} }
 @book{baliga_2023, place={Amsterdam}, edition={2nd}, title={The IGBT Device: Physics, Design and Applications of the Insulated Gate Bipolar Transistor}, publisher={Elsevier}, author={Baliga, B.Jayant}, year={2023} }
 @misc{kanale_cheng_narwal_agarwal_baliga_bhattacharya_hopkins_2022, title={Design Considerations for Developing 1.2 kV 4H-SiC BiDFET-enabled Power Conversion Systems}, ISSN={["2329-3721"]}, url={http://dx.doi.org/10.1109/ECCE50734.2022.9947715}, DOI={10.1109/ECCE50734.2022.9947715}, abstractNote={Bidirectional switches are essential for cycloconverter and matrix converter applications to facilitate single-stage AC-AC conversion without intermediate energy storage elements. The 1.2 kV 4H-SiC BiDFET was developed as the first monolithic bidirectional SiC power transistor. This paper describes the design considerations taken into account while creating the BiDFET device and developing custom packages for housing the switch in discrete form for low power applications and in module form for high-power applications. The realized switches are characterized for their on-state and switching performance. The versatility of the BiDFET device is demonstrated by operating a single BiDFET H-bridge in voltage-source-inverter and current-source-inverter topologies only by varying the gate bias on the individual BiDFETs and reversing the input-output connections.}, journal={2022 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Agarwal, Aditi and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2022}, month={Oct} }
 @article{agarwal_baliga_2022, title={Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters}, volume={10}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2022.3152489}, abstractNote={Significant impact of the ion-implant straggle of the P<sup>+</sup> shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modeling. The P<sup>+</sup> region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of <inline-formula> <tex-math notation="LaTeX">$0.7 \mu \text{m}$ </tex-math></inline-formula>. The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and <inline-formula> <tex-math notation="LaTeX">$0.5 \mu \text{m}$ </tex-math></inline-formula> using both accumulation and inversion mode channels. The presence of the P<sup>+</sup> shielding region ion-implant straggle is shown to: (a) increase specific on-resistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P<sup>+</sup> shielding region lateral straggle on device cell optimization is an important contribution of this paper.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Baliga, B. J.}, year={2022}, pages={245–255} }
 @article{kumar_bhattacharya_baliga_2022, title={Influence of the Inverter Dead-time on the Reverse Recovery Characteristics of 3.3-kV SiC MOSFETs and JBSFETs}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE50734.2022.9947390}, abstractNote={The switching behavior of the high voltage (HV) SiC MOSFETs is superior to that of HV silicon IGBTs. In medium voltage high switching frequency power conversion applications, the reverse recovery effect of the body diode results in large switching losses. In this work, the reverse recovery behavior of the body diode of the recently developed 3.3 kV SiC MOSFETs is investigated at varying junction temperature and current levels. Two solutions are proposed to reduce the reverse recovery losses - by using the optimized dead-time and by integrating Schottky diode in the MOSFETs. The experimental results validate the proposed solutions. A device physics-based numerical model is used to explain the improvement in the body diode reverse recovery characteristics at the smaller dead-time.}, journal={2022 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Kumar, Ashish and Bhattacharya, Subhashish and Baliga, Jayant}, year={2022} }
 @article{kanale_agarwal_baliga_bhattacharya_2022, title={Monolithic Reverse Blocking 1.2 kV 4H-SiC Power Transistor: A Novel, Single-Chip, Three-Terminal Device for Current Source Inverter Applications}, volume={37}, ISSN={["1941-0107"]}, url={https://doi.org/10.1109/TPEL.2022.3166933}, DOI={10.1109/TPEL.2022.3166933}, abstractNote={Current sourceinverters (CSIs) require power switches with first quadrant current conduction and gate-controlled output characteristics as well as reverse blocking capability. Experimental demonstration of a SiC monolithic reverse blocking transistor (MRBT) suitable for CSI applications is described in this letter. The proposed device is based on the integration of a SiC JBS diode with a SiC power mosfet on the same chip. The cathode of the SiC JBS diode is connected to the drain of the SiC power mosfet by their common N+ substrate. The proposed device structure creates a novel SiC-based unipolar single-chip three-terminal transistor with reverse blocking capability. The measured characteristics of a 1.2 kV 4H-SiC MRBT, fabricated in a commercial six-inch wafer foundry, are reported in this letter. The devices show a diode-like on-state characteristic with a low knee voltage of 1.3 V and an on-state voltage drop of 2.8 V at 5 A. The measured reverse transfer capacitance and output capacitance for the MRBT at a drain bias of 2 and 1000 V are a factor of ∼3x and ∼1.6x smaller than the measured values for the internal mosfet device. Switching measurements show a 12% reduction in the gate-drain charge for the MRBT compared with the internal mosfet which is favorable for reducing switching losses.}, number={9}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Kanale, Ajit and Agarwal, Aditi and Baliga, B. Jayant and Bhattacharya, Subhashish}, year={2022}, month={Sep}, pages={10112–10116} }
 @article{agarwal_baliga_2022, title={Temperature Dependence of 55 nm Gate Oxide, 2.3 kV SiC Power JBSFETs With Linear, Hexagonal, and Octagonal Cell Layouts}, volume={69}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2022.3148058}, abstractNote={The electrical characteristics of 2.3-kV 4H-SiC power Junction Barrier Schottky Field-Effect Transistors (JBSFETs) fabricated with 55-nm gate oxide thickness are reported as a function of temperature for the first time. The behavior of three cell topologies (linear, hexagonal, and octagonal) is compared. Excellent JBSFET characteristics are demonstrated up to 150 °C. The ON-resistance was found to increase by 45% from 25 °C to 150 °C for the linear and hexagonal cell layouts, which is much less than the 100% increase previously reported for silicon carbide (SiC) power MOSFETs. The threshold voltage decreases with temperature but remains above 1.2 V even at 150 °C for all cases. The third-quadrant current flow via the integrated JBS diode is confirmed to suppress body diode conduction at all temperatures. The leakage current remains below <inline-formula> <tex-math notation="LaTeX">$1~\mu \text{A}$ </tex-math></inline-formula> even at 150 °C despite the presence of the Schottky contact in the JBSFET structure due to optimum JBS diode design. The octagonal cell topology is shown to exhibit the best figures of merit (FOMs) FOM[<inline-formula> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{C}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula>] and FOM[<inline-formula> <tex-math notation="LaTeX">$ \mathrm{R}_{ \mathrm{\scriptscriptstyle ON}}{}^{\ast } \mathrm{ Q}_{ \mathrm{\scriptscriptstyle GD}}$ </tex-math></inline-formula>] even at elevated temperatures. The observed device behavior is explained using device analytical modeling. The analytical modeling reveals that the reduced rate of increase in ON-resistance with temperature for the 2.3-kV SiC JBSFETs is due to the relatively large source contact resistance produced by the lower (900 °C) contact anneal temperature. The lower anneal temperature is required to simultaneously make the Schottky contact for the JBS diode.}, number={3}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Baliga, B. Jayant}, year={2022}, month={Mar}, pages={1233–1241} }
 @article{agarwal_baliga_2021, title={2.3 kV 4H-SiC Planar-Gate Accumulation Channel Power JBSFETs: Analysis of Experimental Data}, volume={9}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2021.3058662}, abstractNote={Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and gate oxide thickness of 55 nm. The Schottky contact width was chosen to achieve an on-state voltage drop of below 2.8 V in the 3<sup>rd</sup> quadrant for the integrated JBS diodes. Lower specific on-resistance of the Hexagonal and higher values for the Octagonal cell topologies compared with the conventional Linear cell design were experimentally observed. New analytical models developed for the various cell topologies reveal that these differences arise from changes in the relative contributions from the N<sup>+</sup> source contact, channel, and accumulation region resistances. The analysis reported in this article provides new insight on the importance of the accumulation layer resistance to the Octagonal cell topology. Numerical simulation reveal that the measured leakage current behavior correlates with the electric field observed at the Schottky contact within the 2.3 kV JBSFET cell structures. The leakage current begins to rise rapidly when the electric field exceeds 1.5 MV/cm due to Schottky barrier lowering and enhanced tunneling. The reverse transfer capacitance and gate charge were found to correlate with the JFET region density within the different cell topologies. The measured on-state voltage drop in the third quadrant was found to correlate with the JBS diode density in the cell topologies. A new high-frequency figure-of-merit [<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ f3Q}}*Q_{\mathrm{ gd,sp}}$ </tex-math></inline-formula>] is proposed for SiC JBSFETs. The Octagonal cell designs are found to be the most suitable for high frequency applications of 2.3 kV JBSFETs based on the HF-FOMs [<inline-formula> <tex-math notation="LaTeX">$\text{R}_{\mathrm{ on}}*Q_{\mathrm{ gd}}$ </tex-math></inline-formula>] and [<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ f3Q}}$ </tex-math></inline-formula><bold>*Q</bold><inline-formula> <tex-math notation="LaTeX">$_{\mathrm{ gd,sp}}$ </tex-math></inline-formula>].}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Baliga, B. J.}, year={2021}, pages={324–333} }
 @article{agarwal_baliga_francois_maxwell_berliner_papageorge_2021, title={3.3 kV 4H-SiC Planar-Gate MOSFETs Manufactured using Gen-5 PRESiCE (TM) Technology in a 4-inch Wafer Commercial Foundry}, ISSN={["1558-058X"]}, DOI={10.1109/SOUTHEASTCON45413.2021.9401931}, abstractNote={The successful fabrication of 3.3 kV 4H-SiC Planar-Gate MOSFETs in a 4" commercial foundry using the Gen-5 PRESiCE™ technology is reported in this paper. Both Accumulation-channel MOSFETs (ACCUFETs) and Inversion-channel MOSFETs (INVFETs) were successfully manufactured. The electrical characteristics of the two types of fabricated devices are compared in this paper. The wafer yield data indicates that gate-source shorts were the yield-limiting criteria. This effort establishes a second source foundry for manufacturing SiC power devices in the United States.}, journal={SOUTHEASTCON 2021}, author={Agarwal, Aditi and Baliga, Jayant and Francois, Michel M. A. and Maxwell, Ed and Berliner, Nathaniel and Papageorge, Marc}, year={2021}, pages={555–558} }
 @article{agarwal_han_baliga_2021, title={650-V 4H-SiC Planar Inversion-Channel Power JBSFETs With 55-nm Gate Oxide: Relative Performance of Three Cell Types}, volume={68}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2021.3067921}, abstractNote={Planar 650-V 4H-silicon carbide (SiC), inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors (JBSFETs) with three types of cells are compared in this article for the first time. Devices with linear, hexagonal, and octagonal layouts were fabricated in a commercial foundry. The JBS diode was integrated within each cell type. The Schottky contact width for the JBS diode was adjusted to optimize third-quadrant ON-state voltage drop to below 2.5 V for each cell type to ensure by-passing the body diode while maintaining good blocking characteristics in the first quadrant. The hexagonal cell case was the only one whose breakdown voltage (560 V) fell below the 650-V rating. The highest breakdown voltage (710 V) was observed with the octagonal cell layout with a low leakage current of 10 nA at 600 V. The lowest specific ON-resistance was observed for the hexagonal cell design. However, its gate–drain charge was twice that of the conventional linear cell design and four times that of the octagonal cell design. The data from this work demonstrate that the best overall performance for the 650-V SiC, inversion-channel, 55-nm gate oxide junction barrier Schottky field effect transistors is achieved by using the octagonal cell design.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, month={May}, pages={2395–2400} }
 @article{kanale_baliga_2021, title={A New User-Configurable Method to Improve Short-Circuit Ruggedness of 1.2-kV SiC Power MOSFETs}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2020.3010154}, abstractNote={Silicon carbide (SiC) power MOSFETs have been commercialized to replace silicon insulated gate bipolar transistors (IGBTs) in power conversion applications. However, the short-circuit ruggedness of SiC power MOSFETs must be enhanced to match that of Si IGBTs for application in motor drives for electric vehicles. A new, user-configurable method with a series-connected, Si enhancement mode MOSFET (EMM) is demonstrated to improve the short-circuit withstand time of commercially available 1.2-kV SiC power MOSFETs by 86% with a 4.2% increase in on-resistance and a 13% increase in switching loss. In contrast, operating the 1.2-kV SiC power MOSFET with a reduced gate bias of 15 V produces an 80% improvement in short-circuit withstand time with 31% increase in on-resistance and a 31% increase in switching loss. It is demonstrated that the drain of the EMM can be used as a sensing node to monitor on-state current and to detect short-circuit events.}, number={2}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, month={Feb}, pages={2059–2067} }
 @article{agarwal_kanale_baliga_2021, title={Advanced 650 V SiC Power MOSFETs With 10 V Gate Drive Compatible With Si Superjunction Devices}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2020.3017215}, abstractNote={Advanced SiC planar-gate power MOSFETs have been successfully manufactured in a 6-inch commercial foundry with device structures optimized for operation with gate drive voltage of 10 V, compatible with gated drive voltage for Si superjunction products. The electrical characteristics of three advanced SiC MOSFET options are described in this article and compared with those of a state-of-the art Si superjunction MOSFET. The new advanced SiC power MOSFETs are demonstrated to exhibit superior on-state and switching losses with significantly better body-diode reverse recovery performance. Their short-circuit withstand time is also found to be significantly longer than typical commercially available planar-gate SiC power MOSFETs. These improved characteristics make the advanced SiC power MOSFETs suitable replacements for Si superjunction transistors to enhance high frequency circuit performance.}, number={3}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Agarwal, Aditi and Kanale, Ajit and Baliga, B. Jayant}, year={2021}, month={Mar}, pages={3335–3345} }
 @article{agarwal_han_baliga_2021, title={Assessment of Linear, Hexagonal, and Octagonal Cell Topologies for 650 V 4H-SiC Inversion-Channel Planar-Gate Power JBSFETs Fabricated With 27 nm Gate Oxide Thickness}, volume={9}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.3040353}, abstractNote={A 27 nm gate oxide thickness has been successfully used for manufacturing high performance 650V 4H-SiC planar-gate, inversion-channel power JBSFETs in a 6-inch commercial foundry with three (Linear, Hexagonal, and Octagonal) cell topologies. The 27 nm gate oxide thickness allows operation of these JBSFETs at a gate bias of 15 V compared with 20 V used in previous reports for devices with 55 nm gate oxide thickness. The width for the Schottky contact was varied to optimize the performance of the JBS diode in the third quadrant for each cell topology. An on-state voltage drop of 2.5 V or less was achieved in the third quadrant for all the cell topologies by current flow through the integrated JBS diode, satisfying the objective of effectively by-passing the MOSFET body diode. The best breakdown voltage was achieved using the Octagonal cell topology with a half-cell Schottky contact width of 1.1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>. It had a breakdown voltage of 850 V with a low leakage current of less than 5 nA at 650 V. The Linear cell (with half-cell Schottky contact width of 1.0 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>) and the Octagonal cell (with half-cell Schottky contact width of 2.8 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>) had blocking voltages of 800 V. The hexagonal cell topology (with half-cell Schottky contact width of 1.5 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>) had the worst blocking voltage of 715 V. Numerical simulation results are provided to show that the leakage current in all cell topologies begins to increase when the electric field at the Schottky contact exceeds 1.5 MV/cm. The lowest specific on-resistance was obtained with the hexagonal cell topology but its gate-drain charge was <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> larger than the conventional Linear cell design. The Octagonal cell topology with half-cell Schottky contact width of 1.1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> had the same specific on-resistance as the Linear cell case with <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> smaller gate-drain charge. This work demonstrates for the first time that excellent High-Frequency Figures-of-Merit can be achieved with a reduced gate drive voltage of 15 V for 650 V SiC JBSFETs by using a smaller gate oxide thickness of 27 nm and the Octagonal cell topology.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2021}, pages={79–88} }
 @article{kanale_baliga_2021, title={Comparison of BaSIC(DMM) and BaSIC(EMM) Topologies to Enhance Short-Circuit Capability in SiC Power MOSFETs}, ISSN={["1048-2334"]}, DOI={10.1109/APEC42165.2021.9487334}, abstractNote={SiC power MOSFETs have poor short-circuit (SC) withstand capability compared to Si IGBTs. A new method, called BaSIC, with a low voltage silicon MOSFET in series with the source of the SiC power MOSFET, has been recently demonstrated for improvement of the SC capability with minimal impact on normal circuit operation. In this paper, the two BaSIC implementations using either a depletion-mode MOSFET (DMM) or an enhancement-mode MOSFET (EMM) are compared for the first time. The user-configurable BaSIC(EMM) topology was found to result in a superior overall performance. A 1.86x improvement in SC capability was achieved with the BaSIC(EMM) topology with 4% increase in on-resistance and 13 % increase in switching loss versus the BaSIC(DMM) topology which achieved a 2.4x improvement in SC capability with a 19% increase in on-resistance and a 40% increase in switching loss. The BaSIC(DMM) topology offers simplicity of implementation, while the BaSIC(EMM) topology offers a unique user-programmable capability for power electronics engineers.}, journal={2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021)}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, pages={1275–1281} }
 @inproceedings{kanale_narasimhan_cheng_agarwal_shah_baliga_bhattacharya_hopkins_2021, title={Comparison of the Capacitances and Switching Losses of 1.2 kV Common-Source and Common- Drain Bidirectional Switch Topologies}, ISBN={9781665401821}, url={http://dx.doi.org/10.1109/WiPDA49284.2021.9645130}, DOI={10.1109/WiPDA49284.2021.9645130}, abstractNote={Bidirectional, or four-quadrant switches (FQS) can be designed as back-to-back MOSFETs connected in common-drain (CD) or common-source (CS) topologies. CDFQS and CS-FQS assembled from discrete 1.2 kV commercially available SiC power MOSFETs were characterized to obtain capacitance and switching loss values. The CD-FQS exhibited a 1. 17x larger turn-on loss compared to the CS-FQS, while the CS-FQS exhibited a 1. 52x larger turn-off loss compared to the CD-FQS. The CS-FQS exhibited a lower input capacitance, while the CD-FQS exhibited a lower output and reverse transfer capacitance.}, booktitle={2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Kanale, Ajit and Narasimhan, Sneha and Cheng, Tzu-Hsuan and Agarwal, Aditi and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2021}, pages={112–117} }
 @article{kanale_baliga_2021, title={Eliminating Repetitive Short-Circuit Degradation and Failure of 1.2-kV SiC Power MOSFETs}, volume={9}, ISSN={["2168-6785"]}, DOI={10.1109/JESTPE.2020.3045117}, abstractNote={Silicon carbide (SiC) power MOSFETs are known to degrade and eventually fail under repetitive short-circuit (SC) stress. In this article, a new approach, named Baliga Short-Circuit Improvement Concept (BaSIC) depletion-mode MOSFET (DMM), is demonstrated to prevent the degradation and failure of 1.2-kV SiC power MOSFETs under repetitive SC stress. The new concept utilizes a low-voltage, gate–source-shorted Si DMM connected to the source of the SiC MOSFET. It was experimentally verified that no degradation or failure of the SiC power MOSFET occurs after over 3000 SC events with the BaSIC(DMM) topology while the SiC power MOSFETs degraded and failed after 200 SC events without it.}, number={6}, journal={IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, month={Dec}, pages={6773–6779} }
 @article{kanale_baliga_2021, title={Excellent Static and Dynamic Scaling of Power Handling Capability of the BaSIC(DMM) Topology with 1.2 kV SiC Power MOSFETs}, DOI={10.1109/WiPDA49284.2021.9645145}, abstractNote={Enhanced short-circuit (SC) withstand capability for SiC Power MOSFETs has been recently achieved using the BaSIC(DMM) topology which employs a Gate-Source-Shorted Si Depletion Mode MOSFET (GSS Si DMM) in series with the source of the SiC Power MOSFET. This approach increases SC withstand capability with minimal impact on on-resistance and switching losses. In this paper, it is demonstrated for the first time that the Composite MOSFETs created within the BaSIC(DMM) Topology can be paralleled to increase current and power handling capability while maintaining good SC withstand capability. Experimental results on scaling the power were obtained using Composite MOSFET made with 1.2 kV 280 mΩ SiC Power MOSFETs and 100 V 64 mΩ Si DMM devices. Excellent linearity of current scaling and SC capability was experimentally achieved with 2, 3 and 4 paralleled composite MOSFETs.}, journal={2021 IEEE 8TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA)}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, pages={14–17} }
 @article{kumar_kokkonda_bhattacharya_baliga_veliadis_2021, title={High Voltage Output Characteristics and Short Circuit Robustness of HV SiC MOSFETs}, ISSN={["2329-3721"]}, DOI={10.1109/ECCE47101.2021.9595821}, abstractNote={The short circuit characteristics of the recently developed high voltage (HV) SiC MOSFETs are essential to ensure the proper functioning of the power converters during the short circuit fault conditions. The short circuit failure time can be estimated using the HV output characteristics of the MOSFETs with reasonable assumptions. The HV output characteristics of the 3.3 kV, 6.5 kV, and 10 kV SiC MOSFETs, developed by Wolfspeed, are measured for the first time. The estimated short circuit failure time is 3.5 μs, 7.4 μs and 8.1 μs for the 3.3 kV, 6.5 kV, and 10 kV SiC MOSFETs, respectively at the gate bias of 15 V. The analytical results are closely matching with the experimental short circuit failure results of the 6.5 kV SiC MOSFET. The short circuit robustness of the single 6.5 kV SiC MOSFET is found to be superior to the two series-connected 3.3 kV SiC MOSFETs.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Kumar, Ashish and Kokkonda, Raj Kumar and Bhattacharya, Subhashish and Baliga, Jayant and Veliadis, Victor}, year={2021}, pages={5277–5282} }
 @article{shah_narwal_bhattacharya_kanale_cheng_mehrotra_agarwal_baliga_hopkins_2021, title={Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for Solar PV Applications}, ISSN={["2329-3721"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85123361428&partnerID=MN8TOARS}, DOI={10.1109/ECCE47101.2021.9595533}, abstractNote={Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, $46 \mathrm{m}\Omega$, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, $400\mathrm{V}/277\mathrm{V}_{{\mathrm {RMS}}}$ hardware prototype are finally presented to verify the design process.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Shah, Suyash Sushilkumar and Narwal, Ramandeep and Bhattacharya, Subhashish and Kanale, Ajit and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2021}, pages={568–575} }
 @article{kumar_bhattacharya_baliga_veliadis_2021, title={Performance Comparison and Demonstration of 3-L Voltage Source Inverters Using 3.3 kV SiC MOSFETs for 2.3 kV High Speed Induction Motor Drive Applications}, ISSN={["1048-2334"]}, DOI={10.1109/APEC42165.2021.9487135}, abstractNote={Medium voltage direct-drive high-speed motor results in better efficiency and reduces the compressor system’s footprint in the oil and gas industry. This paper investigates the employment and the performance evaluation of the recently developed 3.3 kV SiC MOSFET power modules for a 2.3 kV three-phase high-speed motor drive application. Performance of the three popular three-level (3-L) converter topology, namely NPC, ANPC, and T-type, enabled by the 3.3 kV SiC MOSFETs and diodes is evaluated and compared with a 3.3 kV IGBT-based 2.3 kV drive system. At 10 kHz switching frequency, the test results show that the 3.3 kV SiC MOSFET-based 3-L NPC inverter has superior performance to the other 3-L converters at the motor frequency of 300 Hz. The 3.3 kV SiC MOSFET-based drive system is shown to have a significant improvement in reliability, power density, and efficiency in comparison to the 3.3 kV IGBT-based drive system. The 3.3 kV MOSFET module is demonstrated successfully using the heat run test in the 3-L inverter pole at 10 kHz switching frequency in the laboratory.}, journal={2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021)}, author={Kumar, Ashish and Bhattacharya, Subhashish and Baliga, Jayant and Veliadis, Victor}, year={2021}, pages={1103–1110} }
 @article{agarwal_baliga_2021, title={Performance Enhancement of 2.3 kV 4H-SiC Planar-Gate MOSFETs Using Reduced Gate Oxide Thickness}, volume={68}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2021.3102473}, abstractNote={Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula>) and high-frequency figures-of-merit (FOM[<inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {C}_{\text {gd}}$ </tex-math></inline-formula>], FOM[<inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm {ON}} \times {Q}_{\text {gd}}$ </tex-math></inline-formula>]) were improved by a factor of <inline-formula> <tex-math notation="LaTeX">$1.3\times $ </tex-math></inline-formula> by reducing the gate oxide thickness even at the larger blocking voltage. Analytical modeling shows that the channel and accumulation layer resistances are still important contributors even at this larger blocking voltage capability. Operating the 27 nm gate oxide devices with the commonly accepted ON-state gate oxide electric field of 4 MV/cm for reliable operation makes the <inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm {ON},\text {sp}}$ </tex-math></inline-formula> and FOMs for the 27 nm gate oxide case 10% worse than the 55 nm gate oxide case. However, the reduced gate bias of 11 V for the 27 nm gate oxide case reduces input switching power loss in half from a gate drive perspective. In addition, operation at this gate bias makes the saturation current for the 27 nm gate oxide devices three times smaller than for the conventional devices operating at a gate bias of 20 V, which will proportionally increase short-circuit withstand time.}, number={10}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Baliga, B. Jayant}, year={2021}, month={Oct}, pages={5029–5033} }
 @article{kumar_bhattacharya_baliga_veliadis_2021, title={Performance Evaluation of 10 kV SiC Current Switch Based PWM Current Source Inverter for 4.16 kV Motor Drive Applications}, ISSN={["1048-2334"]}, DOI={10.1109/APEC42165.2021.9487162}, abstractNote={Series-connected 6.5 kV symmetric gate-commutated thyristor (SGCTs) are widely used as the reverse blocking switch (referred to as the current switch in this paper) in 4.16 kV PWM current source inverter (CSI) based motor drive applications up to 420 Hz switching frequency. Modern 10 kV SiC MOSFETs and SiC diodes have the potential to be implemented as the current switch with lower switching loss and a smaller count of the active switches in the 4.16 kV CSI-based drives. In this paper, a 10 kV SiC current switch is presented to enable a medium voltage (MV) PWM-CSI for 4.16 kV motor drive applications. The higher switching frequency capability of the 10 kV SiC current switch reduces the output current harmonics and the dc link inductor size significantly. Experimental tests have shown that the electrical and thermal performance of the 10 kV SiC current switch-based CSI is shown to be reasonably acceptable and near to 10 kV SiC MOSFET-based VSI drives at 10 kHz switching frequency.}, journal={2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021)}, author={Kumar, Ashish and Bhattacharya, Subhashish and Baliga, Jayant and Veliadis, Victor}, year={2021}, pages={1219–1226} }
 @article{narasimhan_kanale_bhattacharya_baliga_2021, title={Performance Evaluation of 3.3 kV SiC MOSFET and Schottky Diode for Medium Voltage Current Source Inverter Application}, DOI={10.1109/WiPDA49284.2021.9645089}, abstractNote={This paper for the first time discusses the dynamic characterization of 3.3 kV SiC-based reverse-voltage blocking current switch for three different switch configurations - SiC MOSFET with a series diode, SiC MOSFETs connected in the common-source or common-drain configuration. The dynamic characterization of the current switch is performed using the conventional double-pulse test at different junction temperatures and different gate resistances. This paper also discusses the static characterization of the latest generation 3.3 kV SiC MOSFET and Schottky diode TO-247 packages. The static characterization of the MOS-FET includes output characteristics, transfer characteristics, junction capacitance measurement and 3rd quadrant characteristics. The static characteristics of the Schottky diode includes the on-state characteristics, and junction capacitance measurement. With the obtained static and dynamic characterization data, the three-phase current-source inverter losses is evaluated for the three different switch configurations and the preferred current switch configuration is selected for a medium voltage-based high-speed motor drive application.}, journal={2021 IEEE 8TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA)}, author={Narasimhan, Sneha and Kanale, Ajit and Bhattacharya, Subhashish and Baliga, Jayant}, year={2021}, pages={366–371} }
 @article{kanale_baliga_2021, title={Selection Methodology for Si Power MOSFETs Used to Enhance SiC Power MOSFET Short-Circuit Capability With the BaSIC(EMM) Topology}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2020.3043281}, abstractNote={The BaSIC(EMM) topology has been previously demonstrated to improve the short-circuit (SC) capability of 1.2-kV SiC power MOSFETs from 3.5 to 7.4 μs while producing a 17% increase in the net on-state resistance. However, a SC time of 10 μs could not be achieved. In this article, a systematic procedure for selection of the Si power MOSFET used in the BaSIC(EMM) topology is described based on information published by manufacturers of Si power MOSFETs in their datasheets. A tradeoff curve between the Si EMM drain saturation current at 150 °C versus its on-resistance at 25 °C is proposed in this article for determination of the best Si EMM product. The proposed methodology allowed identification of a superior Si EMM device. It was experimentally validated that a SC with-stand time of 11 μs, under a gate bias of 20 V applied to the 1.2-kV SiC power MOSFET at a drain bias of 800 V, was achievable with an increase in on-resistance of only 3.6%. These experimental results demonstrate a greatly improved tradeoff curve between SC time and increase in on-resistance.}, number={7}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, month={Jul}, pages={8243–8252} }
 @inproceedings{kanale_cheng_shah_han_agarwal_baliga_hopkins_bhattacharya_2021, title={Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487410}, DOI={10.1109/APEC42165.2021.9487410}, abstractNote={The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Shah, Suyash Sushilkumar and Han, Kijeong and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish}, year={2021}, month={Jun}, pages={1267–1274} }
 @article{kanale_baliga_2021, title={Theoretical Optimization of the Si GSS-DMM Device in the BaSIC Topology for SiC Power MOSFET Short-Circuit Capability Improvement}, volume={9}, ISSN={["2169-3536"]}, DOI={10.1109/ACCESS.2021.3078134}, abstractNote={The BaSIC(DMM) topology has been experimentally demonstrated to improve the short-circuit time for a 1.2 kV SiC power MOSFET product from <inline-formula> <tex-math notation="LaTeX">$4.8~\mu \text{s}$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$7.9~\mu \text{s}$ </tex-math></inline-formula> with a 17% increase in on-state resistance by utilizing a commercially available 100 V rated Gate-Source-Shorted (GSS) Si Depletion-Mode power MOSFET (DMM). The optimization of the Si GSS-DMM is discussed in this paper to achieve even superior performance, namely larger short-circuit time with less increase in on-resistance. It is theoretically demonstrated for the first time that a highly desirable short-circuit time of <inline-formula> <tex-math notation="LaTeX">$10~\mu \text{s}$ </tex-math></inline-formula>, similar to Si IGBTs, can be achieved for two SiC power MOSFET products with less than 3% increase in on-resistance. This was accomplished by reducing the breakdown voltage rating of the Si GSS-DMM from 100 V to 30 V, altering the cell design parameters, and utilizing the trench-gate design. The theoretical analysis provided in this paper provides valuable design guidelines for manufacturers of Si GSS-DMM devices to achieve optimum performance for use in the BaSIC(DMM) topology.}, journal={IEEE ACCESS}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2021}, pages={70039–70047} }
 @article{han_baliga_2020, title={1.2-kV 4H-SiC SenseFET With Monolithically Integrated Sensing Resistor}, volume={41}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2020.2964773}, abstractNote={A 1.2 kV rated 4H-SiC SenseFET structure with monolithically integrated sensing resistor is proposed and experimentally demonstrated. The SenseFET was fabricated on a 6-inch SiC wafer using the same fabrication process as the conventional MOSFET, where Tungsten-Silicided (WSi<sub>2</sub>) Poly-Si layer was patterned to form the Poly-Si gate and sensing resistor, <inline-formula> <tex-math notation="LaTeX">${R}_{S}$ </tex-math></inline-formula>, simultaneously. No impact of the integration of the Sense MOSFET and sense resistor on blocking characteristics was confirmed. Good linearity (within ±10%) of the sense voltage with main MOSFET drain current was observed, independent of drain current level, gate bias voltage, and temperature.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2020}, month={Mar}, pages={437–440} }
 @article{agarwal_han_baliga_2020, title={2.3 kV 4H-SiC Accumulation-Channel Split-Gate Planar Power MOSFETs With Reduced Gate Charge}, volume={8}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2020.2991355}, abstractNote={2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit (HF-FOM) of the 2.3 kV SG-MOSFETs were experimentally verified to be a factor of 1.8<inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> better than that of the conventional MOSFETs with no difference in specific on-resistance.}, number={1}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020}, pages={499–504} }
 @article{agarwal_han_baliga_2020, title={2.3-kV, 5-A 4H-SiC Ti and Ni JBS Rectifiers manufactured in Commercial Foundry: Impact of Implant Lateral Straggle}, DOI={10.1109/WiPDAAsia49671.2020.9360272}, abstractNote={This paper reports characteristics of 2.3-kV 5-A 4H-SiC Junction Barrier controlled Schottky (JBS) rectifiers manufactured in a 6-inch commercial foundry. Two types (Ni and Ti Schottky contact metal) of JBS rectifiers were successfully fabricated. The electrical performance of the Ni and Ti JBS rectifiers is compared at temperatures up to 1500 C. The on-state voltage drop (@ 5 A) of the Ti devices increased from 1.4 to 1.8 V with increasing temperature while that for Ni devices increased from 2.0 to 2.3 V, maintaining values well below that of the SiC P-N junction as required for a JBS diode. The leakage current for the Ni JBS diodes remained below 2 nA @ 500V even up to 1500 C. In contrast, an increase in leakage current to an acceptable level of 100 nA @ 500V was observed for the Ti JBS diodes at 150°C due to its lower barrier height.Analytical modelling indicated that lateral straggle of the $P^{+}$ ion-implant plays an important role in determining the measured on-state voltage drop and reverse leakage characteristics. Simulations were performed to confirm the effect of lateral implant straggle. The simulations demonstrated that lateral implant straggle increases the on-resistance and reduces the leakage current of the JBS rectifier but has no effect on the knee voltage. The experimental results in this paper demonstrate that 4H-SiC JBS rectifiers with 2.3 kV blocking voltage can be manufactured using either Ni or Ti Schottky contacts with excellent on-state voltage drop and leakage current up to 150$^{0}C$.}, journal={2020 IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS IN ASIA (WIPDA ASIA)}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2020} }
 @article{agarwal_han_jayant baliga_2020, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V (vol 40, pg 1792, 2019)}, volume={41}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2956966}, number={1}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Jayant Baliga, B.}, year={2020}, month={Jan}, pages={195–195} }
 @article{kanale_baliga_2020, title={Achieving Short Circuit Capability for 600 V GaN FETs Using a Gate-Source-Shorted Si Depletion-Mode MOSFET in Series with the Source}, DOI={10.1109/WiPDAAsia49671.2020.9360275}, abstractNote={Gallium Nitride FETs have poor short-circuit withstand capability at high DC bus voltages with on-state gate drive voltage. In this paper, the BaSIC(DMM) topology that employs a low voltage Si depletion-mode MOSFET (DMM) in series with source of the GaN FET is demonstrated to suppress the peak short-circuit current and extend the SC withstand time. Experimental results are provided for commercially available 600 V Cascode GaN FETs. The SC withstand time was increased from 0.33 $\mu$ s to 4.35 $\mu$ s at a drain bias of 400 V with gate bias of 8 V, an improvement by a factor of 13x. Under normal power circuit operating conditions, the BaSIC(DMM) topology produces a 29 % increase in on-resistance and almost no change in switching losses.}, journal={2020 IEEE WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS IN ASIA (WIPDA ASIA)}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2020} }
 @article{agarwal_han_baliga_2020, title={Comparison of 2.3-kV 4H-SiC Accumulation-Channel Planar Power MOSFETs Fabricated With Linear, Square, Hexagonal, and Octagonal Cell Topologies}, volume={67}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2020.3005632}, abstractNote={The performance of four cell topologies is compared for 2.3-kV 4H-SiC power MOSFETs fabricated in a commercial 6-in foundry. The devices were simultaneously manufactured with the same channel length (0.5 <inline-formula> <tex-math notation="LaTeX">$ {\mu } \text{m}$ </tex-math></inline-formula>), JFET width (1.1 <inline-formula> <tex-math notation="LaTeX">$ {\mu } \text{m}$ </tex-math></inline-formula>), and gate oxide thickness (55 nm) for comparison. In addition, an octagonal cell design with a JFET width of 1.5 <inline-formula> <tex-math notation="LaTeX">$ {\mu } \text{m}$ </tex-math></inline-formula> was included for comparison. The square and hexagonal cell designs had the lowest specific ON-resistance, but their breakdown voltage was found to be reduced below 2.3 kV due to sharp cell corners. The smallest reverse transfer capacitance and gate charge were observed for the octagonal cell design with significantly larger (~5<inline-formula> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula>) values for the square and hexagonal designs. The high-frequency figure-of-merit HF-FOM[<inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm{\scriptscriptstyle ON}}{\ast } {C}_{\text {rss}}$ </tex-math></inline-formula>] for the octagonal cell design was <inline-formula> <tex-math notation="LaTeX">$3.5\times $ </tex-math></inline-formula> superior to the hexagonal and square cells and <inline-formula> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> better than the linear cell. Its high-frequency figure-of-merit HF-FOM[<inline-formula> <tex-math notation="LaTeX">${R}_{\mathrm{\scriptscriptstyle ON}} {\ast } {Q}_{\text {gd}}$ </tex-math></inline-formula>] was <inline-formula> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> superior to the hexagonal and square cells and <inline-formula> <tex-math notation="LaTeX">$1.2\times $ </tex-math></inline-formula> better than the linear cell. This work demonstrates that the square and hexagonal cells are the best for low-frequency applications, whereas the octagonal cell design is the most suitable for achieving the best high-frequency performance of 2.3-kV 4H-SiC power MOSFETs.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. J.}, year={2020}, pages={3673–3678} }
 @article{kanale_baliga_2020, title={Enhancing Short Circuit Capability of 1.2-kV Si IGBT Using a Gate-Source Shorted Si Depletion Mode MOSFET in Series With the Emitter}, volume={35}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2019.2953589}, abstractNote={Short-circuit (SC) capability is a critical requirement for power switches in modern power electronics applications. A tradeoff between on-state voltage drop, switching loss, and SC capability of insulated gate bipolar transistors (IGBTs) is performed by manufacturers. In general, IGBTs optimized with low on-state voltage have poor SC capability compared with those with good SC capability. In this report, a novel method is described to improve the SC capability of IGBTs optimized with low on-state voltage drop by using a gate-source-shorted Si depletion-mode (DM) mosfet connected in series with the emitter. A seven-fold increase in the SC capability of commercially available 1.2-kV IGBTs was achieved at high dc bus voltages with minimal impact on on-state and switching loss performance. The proposed method also provides a sensing voltage signal at the drain of the Si DM-mosfet, which can be used to monitor the on-state current magnitude and to detect SC fault conditions.}, number={6}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Kanale, Ajit and Baliga, B. Jayant}, year={2020}, month={Jun}, pages={6350–6361} }
 @article{agarwal_han_baliga_2019, title={600 V 4H-SiC MOSFETs Fabricated in Commercial Foundry With Reduced Gate Oxide Thickness of 27 nm to Achieve IGBT-Compatible Gate Drive of 15 V}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2942259}, abstractNote={The measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated in a 6 inch commercial foundry with 27 nm gate oxide thickness are compared with 55 nm gate oxide devices. The High-Frequency Figures-of-Merit (HF-FOMs) of the SiC MOSFETs with 27 nm gate oxide were found to surpass that of commercially available 600 V P7 Si CoolMOS products for the first time. Statistical parametric distribution data and wafer-maps for the 27 nm devices are provided to demonstrate that excellent yield and uniformity can be achieved with the reduced gate oxide thickness. These devices can be operated at 15 V gate bias compatible with IGBT gate drivers.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={Nov}, pages={1792–1795} }
 @article{han_baliga_2019, title={Analysis and Experimental Quantification of 1.2-kV 4H-SiC Split-Gate Octagonal MOSFET}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2917637}, abstractNote={A 1.2-kV rated 4H-SiC split-gate octagonal cell MOSFET (SG-OCTFET) is proposed and successfully fabricated in a 6-in foundry for the first time. The measured results quantify the benefits of the SG-OCTFET structure: improvement in high-frequency figures of merit (HF-FOM) (<inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON}}\times $ </tex-math></inline-formula> C<inline-formula> <tex-math notation="LaTeX">$_{\text {gd}}$ </tex-math></inline-formula>) by <inline-formula> <tex-math notation="LaTeX">$1.8\times $ </tex-math></inline-formula>, HF-FOM (<inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON}}\times $ </tex-math></inline-formula> Q<inline-formula> <tex-math notation="LaTeX">$_{\text {gd}}$ </tex-math></inline-formula>) by <inline-formula> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula>, and FOM (<inline-formula> <tex-math notation="LaTeX">$\text{C}_{\text {iss}}/\text{C}_{\text {gd}}$ </tex-math></inline-formula>) by <inline-formula> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> compared with the optimized compact OCTFET design due to the reduced gate-to-drain overlap area. An important conclusion of this letter is that unlike commercially available 1.2-kV SiC power MOSFETs with linear cell topology, the 1.2-kV SG-OCTFET design can outperform commercially available 600-V Si super-junction devices.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Jul}, pages={1163–1166} }
 @article{han_baliga_2019, title={Comparison of Four Cell Topologies for 1.2-kV Accumulation- and Inversion-Channel 4H-SiC MOSFETs: Analysis and Experimental Results}, volume={66}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2019.2905736}, abstractNote={The electrical characteristics of 1.2-kV-rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs with linear, square, hexagonal, and octagonal cell topologies fabricated using the same design rules and process flow in a 6-in foundry are compared for the first time. TCAD numerical simulations have been conducted to analyze the structures. For all the cell topologies, it was found that the Acc MOSFETs have lower specific ON-resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ </tex-math></inline-formula>) than the Inv counterparts due to higher channel mobility resulting in 1.3–<inline-formula> <tex-math notation="LaTeX">$2.0\times $ </tex-math></inline-formula> smaller high-frequency figure-of-merit (HF-FOM[<inline-formula> <tex-math notation="LaTeX">${R} _{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ </tex-math></inline-formula>]), where <inline-formula> <tex-math notation="LaTeX">${Q} _{\textsf {gd}}$ </tex-math></inline-formula> is the gate-to-drain charge. It is observed that the square and hexagonal cell topologies with the same structural dimensions show similar electrical performance. When compared with the standard linear cell topology: 1) the hexagonal cell topology has <inline-formula> <tex-math notation="LaTeX">$1.15\times $ </tex-math></inline-formula> better specific ON-resistance and <inline-formula> <tex-math notation="LaTeX">$1.12\times $ </tex-math></inline-formula> worse HF-FOM[<inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ </tex-math></inline-formula>] and 2) the octagonal cell topology has <inline-formula> <tex-math notation="LaTeX">$1.5\times $ </tex-math></inline-formula> worse specific ON-resistance and <inline-formula> <tex-math notation="LaTeX">$1.4\times $ </tex-math></inline-formula> better HF-FOM[<inline-formula> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\textsf {gd}}$ </tex-math></inline-formula>]. In addition, the octagonal cell topology has a much superior figure-of-merit (FOM[<inline-formula> <tex-math notation="LaTeX">${C} _{\textsf {iss}}/{C} _{\textsf {rss}}$ </tex-math></inline-formula>]), where <inline-formula> <tex-math notation="LaTeX">${C} _{\textsf {iss}}$ </tex-math></inline-formula> is the input capacitance and <inline-formula> <tex-math notation="LaTeX">${C} _{\textsf {gd}}$ </tex-math></inline-formula> is the reverse transfer capacitance.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={May}, pages={2321–2326} }
 @article{han_baliga_2019, title={Comprehensive Physics of Third Quadrant Characteristics for Accumulation- and Inversion-Channel 1.2-kV 4H-SiC MOSFETs}, volume={66}, ISSN={["1557-9646"]}, DOI={10.1109/TED.2019.2929733}, abstractNote={Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{{\text {knee}}})$ </tex-math></inline-formula> of −1.2 V compared with −1.9 V for the Inv MOSFETs (at <inline-formula> <tex-math notation="LaTeX">${V}_{g} = {0}$ </tex-math></inline-formula> V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Sep}, pages={3923–3928} }
 @article{agarwal_han_baliga_2019, title={Impact of Cell Topology on Characteristics of 600V 4H-SiC Planar MOSFETs}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2019.2908078}, abstractNote={This letter compares the measured electrical characteristics of 600 V planar-gate inversion-channel 4H-SiC power MOSFETs fabricated with four different cell topologies (Linear, Square, Hexagonal, and Octagonal) for the first time. The High-Frequency Figures-of-Merit (HF-FOMs) of these devices were compared with the commercially available SiC device and the Si CoolMOS product. It was found that the HF-FOMs of the 600-V SiC product and our fabricated conventional Linear cell device are much worse in comparison to the Si CoolMOS product. However, the 600 V SiC power MOSFET with comparable performance to the Si CoolMOS product could be achieved by using the Octagonal cell topology.}, number={5}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant}, year={2019}, month={May}, pages={773–776} }
 @article{han_baliga_2019, title={The 1.2-kV 4H-SiC OCTFET: A New Cell Topology With Improved High-Frequency Figures-of-Merit}, volume={40}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2018.2889221}, abstractNote={A 1.2 kV rated 4H-SiC OCTFET device with octagonal-cell topology is proposed and experimentally demonstrated for the first time. The device was first optimized using TCAD numerical simulations. Devices were then successfully fabricated in a 6-inch foundry. From the measured electrical characteristics, the OCTFET is demonstrated to have <inline-formula> <tex-math notation="LaTeX">$\textsf {1.4}\times $ </tex-math></inline-formula> superior high frequency figures-of-merits (HF-FOM) [<inline-formula> <tex-math notation="LaTeX">$\textsf {R}_{\textsf {on}}\times \textsf {Q}_{\textsf {gd}}$ </tex-math></inline-formula>], and <inline-formula> <tex-math notation="LaTeX">$\textsf {2.1}\times $ </tex-math></inline-formula> superior HF-FOM [<inline-formula> <tex-math notation="LaTeX">$\textsf {R}_{\textsf {on}}\times \textsf {C}_{\textsf {gd}}$ </tex-math></inline-formula>] compared with the conventional linear-cell MOSFET.}, number={2}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J.}, year={2019}, month={Feb}, pages={299–302} }
 @article{han_baliga_sung_2018, title={A Novel 1.2 kV 4H-SiC Buffered-Gate (BG) MOSFET: Analysis and Experimental Results}, volume={39}, ISSN={["1558-0563"]}, DOI={10.1109/led.2017.2785771}, abstractNote={A novel 1.2-kV-rated 4H-SiC buffered-gate MOSFET (BG-MOSFET) structure is proposed and experimentally demonstrated to have superior high frequency figures-of-merit (HF-FOMs) for the first time. From the measured data on devices fabricated in a 6-in foundry, the BG-MOSFET is demonstrated to have <inline-formula> <tex-math notation="LaTeX">$4.0\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$2.6\times $ </tex-math></inline-formula> smaller HF-FOM [<inline-formula> <tex-math notation="LaTeX">${R}_{ {\scriptscriptstyle{\text {ON}}}}\times {Q}_{\text {gd}}$ </tex-math></inline-formula>], and <inline-formula> <tex-math notation="LaTeX">$3.6\times $ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$2.1\times $ </tex-math></inline-formula> smaller HF-FOM [<inline-formula> <tex-math notation="LaTeX">${R}_{ {\scriptscriptstyle{\text {ON}}}}\times {C}_{\text {gd}}$ </tex-math></inline-formula>], when compared with the conventional MOSFET and split-gate MOSFET, respectively.}, number={2}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Han, Kijeong and Baliga, B. J. and Sung, Woongje}, year={2018}, month={Feb}, pages={248–251} }
 @article{jiang_sung_baliga_wang_lee_huang_2018, title={Electrical Characteristics of 10-kV 4H-SiC MPS Rectifiers with High Schottky Barrier Height}, volume={47}, ISSN={["1543-186X"]}, DOI={10.1007/s11664-017-5812-2}, number={2}, journal={JOURNAL OF ELECTRONIC MATERIALS}, author={Jiang, Yifan and Sung, Woongje and Baliga, Jayant and Wang, Sizhen and Lee, Bongmook and Huang, Alex}, year={2018}, month={Feb}, pages={927–931} }
 @inproceedings{kumar_parashar_baliga_bhattacharya_2018, title={Single shot avalanche energy characterization of 10kV, 10A 4H-SiC MOSFETs}, volume={2018-March}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85046957199&partnerID=MN8TOARS}, DOI={10.1109/apec.2018.8341404}, abstractNote={Higher switching frequency capability and lower switching loss associated with 10kV 4H-SiC MOSFETs make them attractive for medium voltage applications, mostly in inductive circuits e.g. solid state transformers, grid connectors and high speed machine drives. Due to exposure to inductive circuits, avalanche ruggedness of these MOSFETs needs to be established to improve their reliability in case of unintended unclamped inductive switching. In this paper, the avalanche ruggedness of 10kV, 10A 4H-SiC MOSFETs is established experimentally using single shot unclamped inductive switching. The minimum and the maximum energy is found out for the MOSFET to remain in avalanche without being failed permanently. The junction temperature at the permanent failure is estimated using semiconductor device physics.}, booktitle={Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC}, author={Kumar, A. and Parashar, S. and Baliga, J. and Bhattacharya, Subhashish}, year={2018}, pages={2737–2742} }
 @article{sung_baliga_2017, title={A Comparative Study 4500-V Edge Termination Techniques for SiC Devices}, volume={64}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2017.2664051}, abstractNote={This paper compares five edge termination techniques for SiC high-voltage devices: single zone junction termination extension (JTE), ring assisted-JTE (RA-JTE), multiple floating zone-JTE, hybrid-JTE, and floating field rings. PiN diodes with these edge terminations were fabricated on a 4.5kV-rated 4H-silicon carbide (4H-SiC) epi-layer. It was experimentally demonstrated that the Hybrid-JTE provides a nearly ideal breakdown voltage (~ 99% of the ideal parallel plane breakdown voltage) with a stable avalanche blocking behavior. RA-JTE, with tight control of the JTE implant dose, is demonstrated to be the most area-efficient edge termination structure for SiC power devices.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sung, Woongje and Baliga, B. J.}, year={2017}, month={Apr}, pages={1647–1652} }
 @inproceedings{raheja_gohil_han_acharya_baliga_battacharya_labreque_smith_lal_2017, title={Applications and characterization of four quadrant GaN switch}, volume={2017-January}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85041481367&partnerID=MN8TOARS}, DOI={10.1109/ecce.2017.8096397}, abstractNote={Bi-directional switches, also called four quadrant switches (FQS), are the basic building blocks in many power converter circuits, such as cyclo-converters, matrix converters etc. Conventional approaches to realize bi-directional switch involves combination of unidirectional controllable blocking device (IGBT or MOSFET) and diode. In this approach, current flows through multiple devices for any direction of current flow. This leads to higher conduction losses. Moreover, use of multiple devices increases system size. The die size and semiconductor losses can be reduced by realizing a bi-directional switch using a single die. Further improvement can be achieved by using Gallium Nitride (GaN) semiconductor. This paper discusses characterization of such a four quadrant GaN switch, made using a single die. Static characterization is performed, where the on-state resistances are obtained along with the output characteristics. A double pulse test setup has been built for characterizing FQS's and the experiments were performed to obtain the turn-on and turn-off switching energies.}, booktitle={2017 ieee energy conversion congress and exposition (ecce)}, author={Raheja, U. and Gohil, G. and Han, K. and Acharya, Sayan and Baliga, B. J. and Battacharya, S. and Labreque, M. and Smith, P. and Lal, R.}, year={2017}, pages={1967–1974} }
 @article{sung_baliga_2017, title={On Developing One-Chip Integration of 1.2 kV SiC MOSFET and JBS Diode (JBSFET)}, volume={64}, ISSN={["1557-9948"]}, DOI={10.1109/tie.2017.2696515}, abstractNote={This paper presents the design, fabrication, and characterization of the SiC JBSFET (junction barrier Schottky (JBS) diode integrated MOSFET). The fabrication of the JBSFET adopted a novel single metal, single thermal treatment process to simultaneously form ohmic contacts on n+, p+ implanted regions, and Schottky contact on the n-4H-SiC epilayer. The presented SiC JBSFET uses 40% smaller wafer area because the diode and MOSFET share the edge termination as well as the current conducting drift region. The proposed single chip solution of MOSFET/JBS diode functionalities eliminates the parasitic inductance between separately packaged devices allowing a higher frequency operation in a power converter.}, number={10}, journal={IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS}, author={Sung, Woongje and Baliga, B. J.}, year={2017}, month={Oct}, pages={8206–8212} }
 @article{cai_bodle_mathieu_amos_hamouda_bernacki_mccarty_loboa_2017, title={Primary cilia are sensors of electrical field stimulation to induce osteogenesis of human adipose-derived stem cells}, volume={31}, ISSN={["1530-6860"]}, DOI={10.1096/fj.201600560r}, abstractNote={In this study, we report for the first time that the primary ciliumacts as a crucial sensor for electrical field stimulation (EFS)–enhanced osteogenic response in osteoprogenitor cells. In addition, primary cilia seem to functionally modulate effects of EFS‐induced cellular calciumoscillations. Primary cilia are organelles that have recently been implicated to play a crucial sensor role for many mechanical and chemical stimuli on stem cells. Here, we investigate the role of primary cilia in EFS‐enhanced osteogenic response of human adipose‐derived stem cells (hASCs) by knocking down 2 primary cilia structural proteins, polycystin‐1 and intra flagellar protein‐88. Our results indicate that structurally integrated primary cilia are required for detection of electrical field signals in hASCs. Further more, by measuring changes of cytoplasmic calcium concentration in hASCs during EFS, our findings also suggest that primary ciliamay potentially function as a crucial calcium‐signaling nexus in hASCs during EFS.—Cai, S., Bodle, J. C., Mathieu, P. S., Amos, A., Hamouda, M., Bernacki, S., McCarty, G., Loboa, E. G. Primary cilia are sensors of electrical field stimulation to induce osteogenesis of human adipose‐derived stem cells. FASEB J. 31, 346–355 (2017) www.fasebj.org}, number={1}, journal={FASEB JOURNAL}, author={Cai, Shaobo and Bodle, Josephine C. and Mathieu, Pattie S. and Amos, Alison and Hamouda, Mehdi and Bernacki, Susan and McCarty, Greg and Loboa, Elizabeth G.}, year={2017}, month={Jan}, pages={346–355} }
 @article{han_baliga_sung_2017, title={Split-gate 1.2-kV 4H-SiC MOSFET: Analysis and experimental validation}, volume={38}, DOI={10.1109/led.2017.2738616}, abstractNote={The 1.2-kV-rated 4H-SiC Split Gate MOSFET (SG-MOSFET) structure is demonstrated to have a superior high-frequency figures-of-merit (HF-FOMs) by numerical simulations, with experimental validation for the first time. Excellent electrical characteristics (specific on-resistance, threshold voltage, breakdown voltage, reverse transfer capacitance, and gate-to- drain charge) were measured from devices fabricated on a 6-in SiC wafer. Compared with the conventional MOSFET, the SG-MOSFET has <inline-formula> <tex-math notation="LaTeX">$2.4\times $ </tex-math></inline-formula> smaller HF-FOM [<inline-formula> <tex-math notation="LaTeX">$\text{R}_{\text {on}}\times \text{Q}_{\text {gd}}$ </tex-math></inline-formula>] due to the reduced gate-to-drain charge.}, number={10}, journal={IEEE Electron Device Letters}, author={Han, K. and Baliga, B. J. and Sung, W.}, year={2017}, pages={1437–1440} }
 @article{sung_baliga_2016, title={A Near Ideal Edge Termination Technique for 4500V 4H-SiC Devices: The Hybrid Junction Termination Extension}, volume={37}, ISSN={["1558-0563"]}, DOI={10.1109/led.2016.2623423}, abstractNote={This letter presents a new edge termination technique named a hybrid junction termination extension (Hybrid-JTE), which combines ring-assisted JTE and multiple floating zone JTE. Based on the parameters of the drift layer specified by the wafer vendor, the measured breakdown voltage of the fabricated p-i-n diode using the Hybrid-JTE is as high as 5450 V, which is close (~99%) of the ideal parallel plane p-n junction. Furthermore, measured breakdown voltages from randomly chosen 32 p-i-n diodes across the wafer show very tight distribution: 29 diodes provide breakdown voltages higher than 5000 V at 100 μA.}, number={12}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sung, Woongje and Baliga, B. J.}, year={2016}, month={Dec}, pages={1609–1612} }
 @article{sung_baliga_huang_2016, title={Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices}, volume={63}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2016.2532602}, abstractNote={This paper reviews the bevel-edge termination techniques for silicon carbide (SiC) power devices, such as bevel junction termination extension (JTE), resistive-bevel termination, bevel-assisted JTE, and positive-bevel termination. The proposed bevel-edge termination techniques significantly reduce the chip size for SiC power devices. PiN diodes and test structures were fabricated to quantify the relative performance of the proposed structures. Quantitative comparison in chip size reduction, process schemes, and future research directions is discussed in detail.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sung, Woongje and Baliga, B. Jayant and Huang, Alex Q.}, year={2016}, month={Apr}, pages={1630–1636} }
 @article{sung_baliga_2016, title={Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) Using a Single Ohmic/Schottky Process Scheme}, volume={37}, ISSN={["1558-0563"]}, DOI={10.1109/led.2016.2618720}, abstractNote={This letter reports a new 900 V 4H-SiC JBSFET containing an MOSFET with an integrated JBS diode in the center area of the chip. Both MOSFET and JBS diode structures utilize the same edge termination structure,which results in 30% reduction in SiC wafer area consumption in case of 10 A rating device. In order to form a Schottky contact for the JBS diode as well as ohmic contacts for n+ source and p+ body of the MOSFET, a simple metal process flow has been newly developed. It was found that Ni can simultaneously form ohmic contacts on n+ and p+ implanted regions while it remains a Schottky contact on the n-epitaxial drift layer when it is annealed at moderate temperature (900°C for 2 min). The proposed JBSFET was successfully fabricated using a nine-mask on 6-in 4H-SiC wafers.}, number={12}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sung, Woongje and Baliga, B. J.}, year={2016}, month={Dec}, pages={1605–1608} }
 @inproceedings{baliga_2016, title={SIC power devices: From conception to social impact (invited paper)}, DOI={10.1109/essderc.2016.7599619}, abstractNote={This invited paper reviews the evolution of silicon carbide power devices from the initial proposal for wide bandgap semiconductors for power electronic applications in 1979 to current commercially available devices. The potential social impact on this technology on energy savings and the environment is briefly discussed.}, booktitle={2016 46th european solid-state device research conference (essderc)}, author={Baliga, B. J.}, year={2016}, pages={192–197} }
 @article{sung_huang_baliga_2015, title={Bevel Junction Termination Extension-A New Edge Termination Technique for 4H-SiC High-Voltage Devices}, volume={36}, ISSN={["1558-0563"]}, DOI={10.1109/led.2015.2427654}, abstractNote={A new edge termination method, referred to as a bevel junction termination extension (Bevel-JTE), is presented for high-voltage silicon carbide devices. The 4H-SiC PiN rectifiers, with a breakdown voltage of 1600 V (~95% of the theoretical value), were fabricated using Bevel-JTEs. The Bevel-JTE technique significantly reduces the chip size by decreasing space occupied by edge termination while providing broad process latitude for parameter variations, such as implantation dose and activation anneal condition.}, number={6}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sung, Woongje and Huang, Alex Q. and Baliga, B. Jayant}, year={2015}, month={Jun}, pages={594–596} }
 @inproceedings{vechalapu_tripathi_mainali_baliga_bhattacharya_2015, title={Soft switching characterization of 15 kV SiC n-IGBT and performance evaluation for high power converter applications}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84963579482&partnerID=MN8TOARS}, DOI={10.1109/ecce.2015.7310246}, abstractNote={The 15 kV SiC IGBT with 2 μm and 5 μm field-stop buffer layer thicknesses are two state of the art HV SiC devices. These 15 kV SiC IGBTs generate high dv/dt with two slopes in punch through and non-punch through regions. To design 15 kV SiC IGBT with reduced dv/dt and single slope dv/dt similar to 10-15 kV SiC MOSFET, requires significantly larger drift epitaxial layer thickness and it increases the size and cost of the 15 kV SiC IGBT. This paper presents the zero voltage switching (ZVS) characteristics of 15 kV SiC N-IGBTs to reduce the dv/dt at switching pole along with reduction in the switching losses and increase in the switching frequency limits with external snubber capacitor. The ZVS characteristics are reported up to 9 kV dc bus voltage at 25°C and 150°C for both IGBTs. This paper also reports continuous mode experimental demonstration of zero voltage switching (ZVS) of 5 μm 15 kV IGBT in a medium voltage half bridge converter up to 7 kV dc bus voltage and calculation of power dissipation per IGBT module and its comparison of switching frequency limits with hard switching of half bridge converter.}, booktitle={2015 IEEE Energy Conversion Congress and Exposition, ECCE 2015}, author={Vechalapu, K. and Tripathi, A. and Mainali, K. and Baliga, B.J. and Bhattacharya, Subhashish}, year={2015}, pages={4151–4158} }
 @inproceedings{sung_huang_baliga_ji_ke_hopkins_2015, title={The first demonstration of symmetric blocking SiC gate turn-off (GTO) thyristor}, ISBN={9781479962594 9781479962617}, url={http://dx.doi.org/10.1109/ISPSD.2015.7123438}, DOI={10.1109/ispsd.2015.7123438}, abstractNote={This paper reports the development of symmetric blocking SiC p-GTO thyristors. The proposed thyristor structure features a positive bevel edge termination implemented by orthogonal dicing technique. In this paper, a detailed design of the device structure, forward current-voltage characteristics, and symmetric blocking capabilities are discussed.}, note={\urlhttps://ieeexplore.ieee.org/document/7123438/}, booktitle={2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)}, publisher={IEEE}, author={Sung, Woongje and Huang, Alex Q. and Baliga, B. J. and Ji, Inhwan and Ke, Haotao and Hopkins, Douglas C.}, year={2015}, month={May}, pages={257–260} }
 @inproceedings{kadavelugu_bhattcharya_baliga_ryu_grider_palmour_2014, title={Zero voltage switching characterization of 12 kV SiC N-IGBTs}, DOI={10.1109/ispsd.2014.6856048}, abstractNote={This paper reports experimental zero voltage switching (ZVS) characteristics of the state-of-the-art 12 kV SiC N-IGBTs with 2 μm and 5 μm field-stop buffer layer thicknesses. Extensive results up to 7 kV and 150°C are presented for both IGBTs with and without an external snubber capacitor. The 12 kV SiC IGBTs have been found to have significantly larger magnitude of turn-off current bump in comparison to the results reported for the commercial (≤ 6.5 kV) Si IGBTs, because of deep punch-through design. The turn-off current shape is majorly influenced by slower voltage rise before the punch-through, followed by faster voltage rise after the punch-through voltage. In addition, the difference in current gain resulting from different buffer layer thicknesses has considerable effect on the overall switching behavior and energy loss of the two IGBTs. A detailed explanation of all these phenomena is presented along with the considerations for power converter design while employing the ZVS technique with these ultrahigh voltage IGBTs.}, booktitle={Proceedings of the international symposium on power semiconductor}, author={Kadavelugu, A. and Bhattcharya, S. and Baliga, B. J. and Ryu, S. H. and Grider, D. and Palmour, J.}, year={2014}, pages={350–353} }
 @article{baliga_2013, title={Analytical Modeling of IGBTs: Challenges and Solutions}, volume={60}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2012.2222415}, abstractNote={With the availability of advanced computing capability, it is fashionable to analyze and design insulated-gate bipolar transistors (IGBTs) using sophisticated 2-D and 3-D numerical simulation tools. However, analytical modeling of IGBTs allows a deeper understanding of the physics of operation, which can foster innovation. This paper reviews 1-D analytical models developed for the IGBT on-state characteristics, switching behavior, and safe operating area for symmetric (nonpunchthrough) and asymmetric (punchthrough) devices.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Baliga, B. J.}, year={2013}, month={Feb}, pages={535–543} }
 @misc{baliga_2013, title={Gallium nitride devices for power electronic applications}, volume={28}, ISSN={["1361-6641"]}, DOI={10.1088/0268-1242/28/7/074011}, abstractNote={Recent success with the fabrication of high-performance GaN-on-Si high-voltage HFETs has made this technology a contender for power electronic applications. This paper discusses the properties of GaN that make it an attractive alternative to established silicon and emerging SiC power devices. Progress in development of vertical power devices from bulk GaN is reviewed followed by analysis of the prospects for GaN-on-Si HFET structures. Challenges and innovative solutions to creating enhancement-mode power switches are reviewed.}, number={7}, journal={SEMICONDUCTOR SCIENCE AND TECHNOLOGY}, author={Baliga, B. Jayant}, year={2013}, month={Jul} }
 @inproceedings{huang_wang_li_huang_baliga_2013, title={Short-circuit capability of 1200V SiC MOSFET and JFET for fault protection}, DOI={10.1109/apec.2013.6520207}, abstractNote={The short-circuit capability of power switches is crucial for the fault protection. In this paper, 1200V SiC MOSFET and normally-off SiC JFET have been characterized and their short-circuit capabilities have been studied and analyzed at 400V DC bus voltage. Due to different physics in the channels, SiC MOSFET and SiC JFET show different types of temperature coefficient. During the short-circuit operation, the saturation current, Isat, of SiC MOSFET increases for several microseconds before the gentle decreasing while that of SiC JFET decreases drastically from the very beginning. The SiC MOSFETs failed after short-circuit operations of 80μs and 50μs at 10V and 15V gate bias respectively while the SiC JFET could survive a short-circuit time more than 1.4msec.}, booktitle={2013 twenty-eighth annual ieee applied power electronics conference and exposition (apec 2013)}, author={Huang, X. and Wang, G. Y. and Li, Y. S. and Huang, A. Q. and Baliga, B. J.}, year={2013}, pages={197–200} }
 @inproceedings{huang_baliga_huang_suvorov_capell_cheng_agarwal_2013, title={SiC Symmetric Blocking Terminations Using Orthogonal Positive Bevel Termination and Junction Termination Extension}, DOI={10.1109/ispsd.2013.6694475}, abstractNote={Symmetric blocking power semiconductor switches require two edge terminations, one for the reverse blocking junction and the other one for the forward blocking junction. In this work, we demonstrated 1100V SiC symmetric blocking edge terminations using orthogonal positive bevel (OPB) termination and a one-zone Junction Termination Extension (JTE). The OPB was formed by orthogonally sawing 45° V-shape trenches into the SiC wafer with a diamond-coated dicing blade. The surface damage was then repaired with dry-etch in SF6/O2 plasma, which reduced the leakage current by around two orders of magnitude. As limited by field reach-through, both the OPB and the JTE terminations show breakdown voltage of 1100V. The P+P-N+ diodes fabricated on the same wafer with the OPB termination showed 1610V avalanche breakdown which was around 83% of ideal value.}, booktitle={Proceedings of the international symposium on power semiconductor}, author={Huang, X. and Baliga, B. J. and Huang, A. Q. and Suvorov, A. and Capell, C. and Cheng, L. and Agarwal, A.}, year={2013}, pages={179–182} }
 @article{sung_van brunt_baliga_huang_2012, title={A Comparative Study of Gate Structures for 9.4-kV4H-SiC Normally On Vertical JFETs}, volume={59}, ISSN={["0018-9383"]}, DOI={10.1109/ted.2012.2203337}, abstractNote={This paper reports the development of 9.4-kV 4H-SiC normally on lateral-channel vertical JFETs. The developed JFETs utilize a buried layer to create a lateral conduction channel, shielding the source from the effects of drain bias. The lowest measured <formula formulatype="inline"><tex Notation="TeX">$R_{\rm on, sp}$</tex></formula> was 127 <formula formulatype="inline"><tex Notation="TeX">$\hbox{m}\Omega\cdot\hbox{cm}^{2}$</tex></formula>. Measurements indicate that the channel resistivity can be further reduced by channel optimization. The fabricated JFETs exhibit pentode-like <formula formulatype="inline"><tex Notation="TeX">$I_{D}$</tex></formula>–<formula formulatype="inline"><tex Notation="TeX">$V_{\rm DS}$ </tex></formula> characteristics with a high forward direct-current blocking gain of over 500. This paper provides a comparative study of gate structures in order to achieve the lowest on -state switching losses and to provide stable forward blocking characteristics for a normally on JFET.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sung, Woongje and Van Brunt, Edward and Baliga, B. Jayant and Huang, Alex Q.}, year={2012}, month={Sep}, pages={2417–2423} }
 @article{sung_baliga_huang_2012, title={A Novel 4H-SiC Fault Isolation Device with Improved Trade-off between On-state Voltage Drop and Short Circuit SOA}, volume={717-720}, ISBN={["978-3-03785-419-8"]}, ISSN={["0255-5476"]}, DOI={10.4028/www.scientific.net/msf.717-720.1045}, abstractNote={This paper aims to introduce a solid-state fault isolation device (FID) for the short circuit protection application in the power distribution systems. The key performance of a FID is to have a low on-state loss and a strong short circuit safe operating area (SCSOA). As a FID, a novel 15kV 4H-SiC field controlled diode (FCD) with a p+buried layer is proposed to provide an improved trade-off between the on-state forward voltage drop and the saturation current. Dynamic response to the fault and the application example of the proposed FCD are described in this paper.}, journal={SILICON CARBIDE AND RELATED MATERIALS 2011, PTS 1 AND 2}, author={Sung, Woongje and Baliga, B. J. and Huang, Alex Q.}, year={2012}, pages={1045–1048} }
 @article{huang_van brunt_baliga_huang_2012, title={Orthogonal Positive-Bevel Termination for Chip-Size SiC Reverse Blocking Devices}, volume={33}, ISSN={["1558-0563"]}, DOI={10.1109/led.2012.2215003}, abstractNote={Symmetric blocking power semiconductor switches require positive-bevel edge terminations for the reverse blocking p-n junction. This technique has been extensively applied to silicon wafer-size devices with high current ratings. In this letter, we propose and experimentally demonstrate, for the first time, that an orthogonal positive-bevel termination can be used for the reverse blocking junction of chip-size SiC devices. The edge termination was formed by sawing the SiC wafer with a V-shaped dicing blade. For proof of concept, our experiment was done on a SiC wafer with a 15.8-μm 6.1 × 1015 cm-3 p-type epitaxial layer grown on an N+ substrate. The positive-bevel termination resulted in a breakdown voltage of over 1000 V as limited by reach-through breakdown even without removal of damage from the sawing. The leakage current was found to be reduced by two orders of magnitude after reactive ion etching of the SiC bevel surface to remove the sawing damage.}, number={11}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Huang, Xing and Van Brunt, Edward and Baliga, B. Jayant and Huang, Alex Q.}, year={2012}, month={Nov}, pages={1592–1594} }
 @article{sung_van brunt_baliga_huang_2011, title={A New Edge Termination Technique for High-Voltage Devices in 4H-SiC-Multiple-Floating-Zone Junction Termination Extension}, volume={32}, ISSN={["0741-3106"]}, DOI={10.1109/led.2011.2144561}, abstractNote={A new edge termination method, referred to as multiple-floating-zone junction termination extension (MFZ-JTE), is presented for high-voltage devices in 4H-SiC. 4H-SiC PiN rectifiers with a breakdown voltage of 10 kV (about 88% of the theoretical value) were fabricated using MFZ-JTEs. The MFZ-JTE technique only requires a single pattern-and-implant step while providing significant process latitude for parameter variations such as implantation dose and activation anneal condition.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sung, Woongje and Van Brunt, Edward and Baliga, B. J. and Huang, Alex Q.}, year={2011}, month={Jul}, pages={880–882} }
 @article{ozbek_baliga_2011, title={Finite-Zone Argon Implant Edge Termination for High-Voltage GaN Schottky Rectifiers}, volume={32}, ISSN={["0741-3106"]}, DOI={10.1109/led.2011.2162221}, abstractNote={In this letter, the results obtained with a finite termination by argon ion implantation at the periphery of GaN Schottky barrier diodes are reported. It is demonstrated that the implant region width required to obtain the ideal plane parallel breakdown voltage of 1700 V is 50 μm.}, number={10}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Ozbek, A. Merve and Baliga, B. Jayant}, year={2011}, month={Oct}, pages={1361–1363} }
 @article{ozbek_baliga_2011, title={Planar Nearly Ideal Edge-Termination Technique for GaN Devices}, volume={32}, ISSN={["0741-3106"]}, DOI={10.1109/led.2010.2095825}, abstractNote={In this letter, a simple edge termination is described which can be used to achieve nearly ideal parallel-plane breakdown voltage for GaN devices. This technique involves implanting a neutral species on the edges of devices to form a high-resistive amorphous layer. With this termination, formed by using argon implantation, the breakdown voltage of GaN Schottky barrier diodes was increased from 300 V for unterminated diodes to 1650 V after termination.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Ozbek, A. Merve and Baliga, B. Jayant}, year={2011}, month={Mar}, pages={300–302} }
 @misc{ozbek_baliga_2011, title={Tunneling coefficient for GaN Schottky barrier diodes}, volume={62}, ISSN={["1879-2405"]}, DOI={10.1016/j.sse.2011.04.016}, abstractNote={In this report, the tunneling coefficient (CT) for GaN Schottky barrier diodes is extracted for analytical computation of the reverse leakage current. The extraction method is based up on fitting experimental data to the analytical equation by adjusting Schottky barrier height (ϕBN) to account for defects. The tunneling coefficient (7.1 ± 0.74) × 10−12 cm2 V−2 for GaN Schottky contacts is found to be independent of the size of the contact inspite of the presence of defects.}, number={1}, journal={SOLID-STATE ELECTRONICS}, author={Ozbek, A. Merve and Baliga, B. Jayant}, year={2011}, month={Aug}, pages={1–4} }
 @inproceedings{sung_huang_baliga_2010, title={A novel 4H-SiC IGBT structure with improved trade-off between short circuit capability and on-state voltage drop}, booktitle={Proceedings of the international symposium on power semiconductor}, author={Sung, W. and Huang, A. Q. and Baliga, B. J.}, year={2010}, pages={217–220} }
 @book{baliga_2009, title={Advanced power rectifier concepts}, ISBN={9780387755885}, DOI={10.1007/978-0-387-75589-2}, publisher={New York: Springer}, author={Baliga, B. J.}, year={2009} }
 @article{sung_wang_huang_baliga_2009, title={Design and investigation of frequency capability of 15kV 4H-SiC IGBT}, ISBN={["978-1-4244-3525-8"]}, ISSN={["1943-653X"]}, DOI={10.1109/ispsd.2009.5158054}, abstractNote={15kV 4H-SiC n-channel asymmetric and symmetric IGBTs were designed to minimize the on state and switching power loss. A Current Enhancement Layer was adopted to reduce the forward voltage drop for each IGBTs. For the asymmetric IGBT, it was found that the frequency capability of the device was affected most by adjusting the buffer region parameters such as doping concentration, thickness, and lifetime. For the symmetric IGBT, the p+ substrate doping concentration and drift region lifetime were investigated to obtain maximum switching frequency capability. A comparison of frequency capabilities between power MOSFETs, asymmetric, and symmetric IGBTs has been made. IGBTs provide lower power loss than power MOSFETs up to approximately 7 kHz.}, journal={2009 21ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS}, author={Sung, Woongje and Wang, Jun and Huang, Alex Q. and Baliga, B. Jayant}, year={2009}, pages={271–274} }
 @article{huang_baliga_2009, title={FREEDM System: Role of Power Electronics and Power Semiconductors in Developing an Energy Internet}, ISBN={["978-1-4244-3525-8"]}, ISSN={["1943-653X"]}, DOI={10.1109/ispsd.2009.5157988}, abstractNote={The Future Renewable Electric Energy Delivery and Management (FREEDM) Systems Center is a National Science Foundation (NSF) Generation-III Engineering Research Center (ERC) established in 2008 with the mission to develop the fundamental and enabling technologies necessary for a new and paradigm shifting power grid infrastructure, the FREEDM System. This paper will highlight the role of power electronics and power semiconductors in developing an energy internet. The revolutionary impact of high voltage SiC and GaN power devices in utility and FREEDM System is discussed.}, journal={2009 21ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS}, author={Huang, Alex Q. and Baliga, Jay}, year={2009}, pages={9–12} }
 @article{wang_huang_baliga_2009, title={RBSOA Study of High Voltage SiC Bipolar Devices}, ISBN={["978-1-4244-3525-8"]}, ISSN={["1063-6854"]}, DOI={10.1109/ispsd.2009.5158052}, abstractNote={Rapid improvement of 4H-SiC material quality and maturation of SiC device processing have enabled the development of high voltage SiC bipolar devices for high voltage switching applications. As one of the major concern of bipolar devices, the onset of dynamic avalanche breakdown and reverse biased safe operating area (RBSOA) of SiC pnp and npn transistors have been systematically analyzed in this paper. The theoretical analysis predicts the onset power density of dynamic avalanche breakdown of SiC bipolar devices is more than twenty times larger than that of Si bipolar devices, and SiC bipolar devices have a near square RBSOA. The predicted rugged turn-off behavior of SiC bipolar devices is verified by numerical simulations of 10-kV SiC emitter turn-off thyristors (ETOs). The excellent ruggedness of SiC bipolar devices make them attractive for high voltage (≥10-kV) switching applications.}, journal={2009 21ST INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS}, author={Wang, Jun and Huang, Alex Q. and Baliga, B. Jayant}, year={2009}, pages={263–266} }
 @article{wang_huang_sung_liu_baliga_2009, title={Smart Grid Technologies}, volume={3}, ISSN={["1941-0115"]}, DOI={10.1109/MIE.2009.932583}, abstractNote={The need for power semiconductor devices with high-voltage, high- frequency, and high-temperature operation capability is growing, especially for advanced power conversion and military applications, and hence the size and weight of the power electronic system are reduced. Development of 15-kV SiC IGBTs and their impact on utility applications is discussed.}, number={2}, journal={IEEE INDUSTRIAL ELECTRONICS MAGAZINE}, author={Wang, Jun and Huang, Alex Q. and Sung, Woongje and Liu, Yu and Baliga, B. Jayant}, year={2009}, month={Jun}, pages={16–23} }
 @book{baliga_2008, title={Fundamentals of power semiconductor devices}, DOI={10.1007/978-0-387-47314-7}, abstractNote={Fundamentals of Power Semiconductor Devices provides an in-depth treatment of the physics of operation of power semiconductor devices that are commonly used by the power electronics industry. Analytic}, publisher={New York: Springer}, author={Baliga, B. Jayant}, year={2008} }
 @misc{baliga_2001, title={Methods of forming power semiconductor devices having T-shaped gate electrodes}, volume={6,303,410}, number={2001 Oct. 16}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={2001}, month={Oct} }
 @misc{baliga_2001, title={Silicon carbide power devices having trench-based silicon carbide charge coupling regions therein}, volume={6,313,482}, number={2001 Nov. 6}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={2001}, month={Nov} }
 @article{baliga_2001, title={The future of power semiconductor device technology}, volume={89}, ISSN={["1558-2256"]}, DOI={10.1109/5.931471}, abstractNote={Power electronic systems have benefited greatly during the past ten years from the revolutionary advances that have occurred in power discrete devices. The introduction of power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 1970s and the insulated gate bipolar transistors (IGBTs) in the 1980s enabled design of very compact high-efficiency systems due to the greatly enhanced power gain resulting from the high input impedance of these structures. Recently, significant improvements in the performance of silicon-power MOSFETs has been achieved by using innovative vertical structures with charge coupled regions. Meanwhile, silicon IGBTs continue to dominate the medium- and high-voltage application space sue to scaling of their voltage ratings and refinements to their gate structure achieved by using very large scale integration (VLSI) technology and trench gate regions. Research on a variety of MOS-gated thyristors has also been conducted, resulting in some promising improvements in the tradeoff between on-state power loss, switching power loss, and the safe-operating-area. Concurrent improvements in power rectifiers have been achieved at low-voltage ratings using Schottky rectifier structures containing trenches and at high-voltage ratings using structures that combine junction and Schottky barrier contacts. On the longer term, silicon carbide Schottky rectifiers and power MOSFETs offer at least another tenfold improvement in performance. Although the projected performance enhancements have been experimentally demonstrated, the defect density and cost of the starting material are determining the pace of commercialization of this technology at present.}, number={6}, journal={PROCEEDINGS OF THE IEEE}, author={Baliga, BJ}, year={2001}, month={Jun}, pages={822–832} }
 @misc{baliga_2000, title={Bidirectional silicon carbide power devices having voltage supporting regions therein for providing improved blocking voltage capability}, volume={6,023,078}, number={2000 Feb. 8}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={2000}, month={Feb} }
 @article{sawant_baliga_2000, title={Current saturation control in silicon emitter switched thyristors}, volume={44}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(99)00217-8}, abstractNote={Abstract In this paper a novel Dual Channel Emitter Switched Thyristor (DC-EST) structure with diode diverter connected to the P-base region is shown to provide reduced saturation current density without compromising the on-state voltage drop. During the on-state, the diode diverter does not carry any current and the P-base region is effectively floating in potential, which results in a low on-state voltage drop. During current saturation, as the P-base potential rises, the diode diverter diverts the holes collected in the P-base, thus leading to an improved forward biased safe operating area (FBSOA). The saturation current density is lowered significantly which is desirable to achieve a good short circuit safe operating area (SCSOA). The dynamic clamping behavior of the diode diverter allows for independent optimization of the forward drop and saturation current density. Experimental results are reported to confirm the superior characteristics observed through simulations. The novel diode diverter DC-EST structure is found to be particularly suitable for high voltage (4 kV) applications.}, number={1}, journal={SOLID-STATE ELECTRONICS}, author={Sawant, S and Baliga, BJ}, year={2000}, month={Jan}, pages={133–142} }
 @misc{baliga_2000, title={Power semiconductor devices that utilize buried insulating regions to achieve higher than parallel-plane breakdown voltages}, volume={6,075,259}, number={2000 June 13}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={2000}, month={Jun} }
 @article{bobde_baliga_2000, title={Silicon planar ACCUFET: improved power MOSFET structure}, volume={36}, ISSN={["0013-5194"]}, DOI={10.1049/el:20000647}, abstractNote={An improved power MOSFET structure in silicon. Called the planar ACCUmulation channel field effect transistor (planar ACCUFET) is proposed. In this device, the P base and the deep P/sup +/ regions of the conventional DMOSFET are replaced by a depleted N-type base region created using a buried P/sup +/ region. Numerical simulations show that the planar ACCUFET has good forward blocking characteristics with low leakage current. The specific on-resistance, as well as the gate charge of the planar ACCUFET are lower than those of a DMOSFET with the same voltage rating. Furthermore, the planar ACCUFET requires a smaller thermal budget for fabrication than the DMOSFET.}, number={10}, journal={ELECTRONICS LETTERS}, author={Bobde, MD and Baliga, BJ}, year={2000}, month={May}, pages={913–915} }
 @article{sawant_sridhar_baliga_1999, title={An experimental analysis of the dual gate emitter switched thyristor (DG-EST)}, volume={43}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(99)00148-3}, abstractNote={In recent years, various dual MOS gated thyristor structures have been proposed to improve the three pronged trade-off of forward voltage drop, turn-off time and forward biased safe operating area when compared to single gate devices. The dual gate emitter switched thyristor (DG-EST), with its unique thyristor current partitioning mechanism, has been reported to posses superior characteristics when compared to conventional single gate ESTs. In this paper, a detailed study of the device physics of operation of the DG-EST is presented, supported by two dimensional numerical simulations. Effects of variations in the floating emitter length, lifetime in the drift region and temperature on the forward voltage drop are experimentally observed. An analytical model predicting the maximum controllable current density (JMCC) of the DG-EST is reported and confirmed through experimental measurements. The DG-EST is found to have a superior trade-off curve of on-state voltage drop versus turn-off time when compared to the conventional emitter switched thyristor (C-EST).}, number={10}, journal={SOLID-STATE ELECTRONICS}, author={Sawant, S and Sridhar, S and Baliga, BJ}, year={1999}, month={Oct}, pages={1901–1908} }
 @article{shenoy_baliga_1999, title={Analysis and optimization of the planar 6H-SiC ACCUFET}, volume={43}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(98)00244-5}, abstractNote={This paper discusses the optimization of the planar 6H-SiC ACCUFET structure based upon analysis, simulations and experimental results. Two-dimensional numerical simulations demonstrate that the maximum electric field in the gate oxide can be kept below 3.5 MV cm−1 even at the maximum blocking voltage of 1500 V, by proper device design thereby eliminating the oxide rupture problem seen in SiC UMOSFETs. The trade-off between specific on-resistance and the maximum gate oxide electric field is obtained using simulations. The fabricated 6H-SiC unterminated devices had a blocking voltage of about 350 V with a specific on-resistance of 18 mΩ cm2 at room temperature for a gate bias of only 5 V. This measured specific on-resistance is within 20% of the analytically calculated and simulated specific on-resistance for the same device. High temperature measurements show that the threshold voltage decreases with temperature and the accumulation channel mobility (∼125 cm2 V−1 s−1) is almost independent of temperature. The specific on-resistance exhibited positive temperature coefficient, as opposed to the undesirable negative temperature coefficient observed on previously reported high voltage SiC MOSFETs.}, number={2}, journal={SOLID-STATE ELECTRONICS}, author={Shenoy, PM and Baliga, BJ}, year={1999}, month={Feb}, pages={213–220} }
 @article{thapar_baliga_1999, title={Enhancing the maximum controllable current density of the accumulation channel driven bipolar transistor}, volume={43}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(98)00255-X}, abstractNote={The phenomenon of potential barrier lowering in the N-base region limits the maximum controllable current density (Jmcc) of the accumulation channel bipolar transistor (ACBT). The barrier lowering occurs when the hole current flowing into the P/N-base collector junction of the ACBT creates a bias opposing the built-in potential of the P/N-base junction. A significant improvement in the Jmcc of the ACBT has been obtained after electron radiation because the hole current flowing into the P/N-base junction is decreased as a result of the reduction in minority carrier lifetime. Furthermore, the Jmcc of the ACBT is shown to increase significantly by ramping the gate electrode to negative voltages during turn-off. The enhancement in the Jmcc brought about by this method is limited by the channel density of the PMOSFET created along the deep trench sidewall on application of a negative gate bias. A new dual gate ACBT structure, integrating a high channel density PMOSFET within its unit cell, is proposed and demonstrated to be superior to the conventional ACBT structure.}, number={2}, journal={SOLID-STATE ELECTRONICS}, author={Thapar, N and Baliga, BJ}, year={1999}, month={Feb}, pages={395–402} }
 @article{chilukuri_shenoy_baliga_1999, title={High-temperature operation of SiC planar ACCUFET}, volume={35}, ISSN={["1939-9367"]}, DOI={10.1109/28.806062}, abstractNote={Power losses in SiC switches can be up to two orders of magnitude lower than those in silicon devices, and hence, SiC devices exhibit a tremendous potential for applications in UPS, motor control, etc. Due to very low diffusion coefficients in SiC, UMOSFETs have been fabricated, but their performance has been limited by premature oxide breakdown and low inversion layer mobility. A novel planar vertical MOSFET structure (called ACCUFET), which eliminates both these problems, has been proposed. In this paper, the authors discuss high temperature characteristics of ACCUFETs fabricated from 6H-SiC and 4H-SiC polytypes. A room temperature specific on-resistance (R/sub on,sp/) of 18 m/spl Omega/-cm/sup 2/ was measured on the best 6H-SiC device at a logic-level gate drive voltage of only 5 V, which was in excellent agreement with 15 m/spl Omega/-cm/sup 2/ obtained in simulations. The measured R/sub on,sp/ for the 6H-SiC ACCUFET is within 2.5/spl times/ of the drift region resistance which is the best value obtained so far for any high voltage SiC MOSFET. The forward voltage drop of the best 6H-SiC ACCUFET at 50 A/cm/sup 2/ was 0.9 V, which is much less than that of a 1200 V IGBT (typically 3 V for a high speed device). The R/sub on,sp/ exhibited a positive temperature coefficient, which is extremely desirable since it allows paralleling of devices and also improves reliability by avoiding current filamentation problems. In contrast, the room R/sub on,sp/ for the best 4H-SiC reduced rapidly with increase in temperature to 128 m/spl Omega/-cm/sup 2/ at 450 K. At room temperature, the unterminated 6H-SiC and 4H-SiC devices had a breakdown voltage (BV) of 350 V and 450 V, respectively, with a leakage current of <100 /spl mu/A. However, a breakdown voltage of 1240 V is obtainable from the epitaxial material.}, number={6}, journal={IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS}, author={Chilukuri, RK and Shenoy, PM and Baliga, BJ}, year={1999}, pages={1458–1462} }
 @misc{baliga_1999, title={Methods of forming silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein}, volume={5,950,076}, number={1999 Sept. 7}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1999}, month={Sep} }
 @article{ramamurthy_sawant_baliga_1999, title={Modeling the [dV/dt] of the IGBT during inductive turn off}, volume={14}, ISSN={["0885-8993"]}, DOI={10.1109/63.774195}, abstractNote={Insulated gate bipolar transistor (IGBT)-based pulsewidth modulation (PWM) inverters are commonly used in inductive load circuits such as motor control. During clamped inductive load turn off of the IGBT, high-power losses occur during two phases. Due to the large inductive motor load, the voltage across the IGBT rises to the bus voltage while carrying the full-rated current. In the second phase, the current decreases as the IGBT goes into its forward blocking mode. In this paper, the turn-off process during the first phase is analyzed in detail for the first time. A simple analytical model has been derived, based upon the initial steady-state minority carrier distribution, which allows predicting the rate of rise of the voltage during this time period where the collector current remains constant. The predictions of the analytical model are in excellent agreement with results obtained from two-dimensional (2-D) numerical simulations over a broad range of minority carrier lifetime values. This analytical model provides a good estimate (within 10%) of the power losses incurred during the first phase of turn off.}, number={4}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Ramamurthy, A and Sawant, S and Baliga, BJ}, year={1999}, month={Jul}, pages={601–606} }
 @misc{baliga_1999, title={Power semiconductor devices having improved high frequency switching and breakdown characteristics}, volume={5,998,833}, number={1999 Dec. 7}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1999}, month={Dec} }
 @misc{baliga_1999, title={Power semiconductor devices having trench-based gate electrodes and field plates}, volume={6,388,286}, number={1999 Aug 18}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1999}, month={Aug} }
 @misc{baliga_1999, title={Semiconductor switching devices having buried gate electrodes and methods of forming same}, volume={5,912,497}, number={1999 June 15}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1999}, month={Jun} }
 @article{baliga_1999, title={SiC promises higher power MOS devices}, volume={47}, number={24}, journal={Electronic Design}, author={Baliga, B. J.}, year={1999}, month={Nov}, pages={27} }
 @article{raghunathan_baliga_1999, title={Temperature dependence of hole impact ionization coefficients in 4H and 6H-SiC}, volume={43}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(98)00248-2}, abstractNote={Hole impact ionization coefficients have been accurately measured as a function of temperature in both 4H and 6H-SiC using the pulsed electron beam induced current (P-EBIC) technique. For Chynoweth's equation (α=a e−b/E), our measurements gave an ap value of (2.6±0.12)×106/cm and a bp value of (1.5±0.01)×107 V/cm for 6H-SiC at room temperature while the values of ap and bp for 4H-SiC were found to be (3.25±0.3)×106/cm and (1.71±0.04)×107 V/cm, respectively, at room temperature. The coefficient ap was found to decrease with increasing temperature for both polytypes while the coefficient bp remained constant. Based upon this data, the breakdown voltage of the 4H and 6H-SiC devices is predicted to increase with temperature which is an important desirable characteristic for power devices.}, number={2}, journal={SOLID-STATE ELECTRONICS}, author={Raghunathan, R and Baliga, BJ}, year={1999}, month={Feb}, pages={199–211} }
 @article{mahalingam_baliga_1999, title={The graded doped trench MOS Barrier Schottky rectifier: a low forward drop high voltage rectifier}, volume={43}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(98)00250-0}, abstractNote={Abstract A novel high voltage Schottky rectifier, called the Graded Doped Trench MOS Barrier Schottky (GD-TMBS) rectifier, is described in this paper. It is shown to have very low forward drop with excellent reverse blocking characteristics through device simulation and electrical characterization of fabricated devices. A linearly graded drift region doping profile is shown to result in an uniform electric field in the drift region resulting in the ability to support blocking voltages proportional to the trench depth. Two-dimensional device simulations have shown that breakdown voltages of upto 200 V can be achieved with a very low forward drop of 0.54 V. The measured on-state drop of fabricated 60 and 100 V GD-TMBS are about half those of conventional Schottky rectifiers. Power dissipation analysis indicates higher operating temperatures (150°C) with reduced heat sink sizes when compared to conventional Schottky barrier diodes.}, number={1}, journal={SOLID-STATE ELECTRONICS}, author={Mahalingam, S and Baliga, BJ}, year={1999}, month={Jan}, pages={1–9} }
 @article{thapar_baliga_1998, title={An experimental evaluation of the on-state performance of trench IGBT designs}, volume={42}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(97)00301-8}, abstractNote={The on-state performance of non-self aligned and self aligned trench IGBT designs is experimentally evaluated and compared for the first time in this paper. In contrast to previous reports based only on numerical simulations, experimental results presented in this paper demonstrate that the non-self aligned trench IGBT designs are superior to the self-aligned trench IGBT designs. Furthermore, the variation in the on-state voltage drop with the unit cell parameters of the non-self trench IGBT obtained through numerical simulations show trends that are opposite to those observed experimentally. Our analysis indicates that the disagreement between the experimental and numerical simulation results arises due to the assumption of an ideal ohmic contact to the N+ emitter of the TIGBT designs made in previous numerical simulations.}, number={5}, journal={SOLID-STATE ELECTRONICS}, author={Thapar, N and Baliga, BJ}, year={1998}, month={May}, pages={771–776} }
 @article{yamazaki_baliga_1998, title={Analysis and suppression of latch-up during IGBT mode of DG-BRT operation}, volume={42}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(97)00215-3}, abstractNote={The influence of P-base doping concentration on the saturation characteristics of the dual gate BRT (DG-BRT) structure in the IGBT mode of operation is analyzed in this paper by two dimensional simulation. The common base current gains (αPNP and αNPN) of the inherent PNP and NPN transistors within the DG-BRT structure have been extracted as a function of operating current density. Based upon these values, it is demonstrated that, by using P-base concentration of 5×1018 cm−3, the sum of the current gains (αPNP+αNPN) can be made less than unity in the IGBT mode of operation to suppress latch-up. This results in a significant enhancement of the forward biased safe operating area.}, number={3}, journal={SOLID-STATE ELECTRONICS}, author={Yamazaki, T and Baliga, BJ}, year={1998}, month={Mar}, pages={393–399} }
 @article{thapar_baliga_1998, title={Analytical model for the threshold voltage of Accumulation Channel MOS-Gate devices}, volume={42}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(98)00179-8}, abstractNote={An analytical model for the threshold voltage of Accumulation Channel MOS-Gate devices is developed for the first time in this paper. Using the model, an equation for the threshold voltage is derived in terms of the design and fabrication process parameters. The values of the threshold voltage predicted by the analytical equation are found to be in excellent agreement with those extracted from numerical simulations and experimental measurements on both silicon and silicon carbide devices. The analysis in this paper is therefore useful in choosing the design and fabrication process parameters required to tailor the threshold voltage of Accumulation Channel MOS-Gate bipolar and unipolar devices.}, number={11}, journal={SOLID-STATE ELECTRONICS}, author={Thapar, N and Baliga, BJ}, year={1998}, month={Nov}, pages={1975–1979} }
 @book{singh_baliga_1998, title={Cryogenic operation of silicon power devices}, ISBN={0792381572}, DOI={10.1007/978-1-4615-5751-7}, abstractNote={The advent of low temperature superconductors in the early 1960's converted what had been a laboratory curiosity with very limited possibilities to a prac tical means of fabricating electrical compone}, publisher={Boston, MA: Kluwer Academic Publishers}, author={Singh, R. and Baliga, B. J.}, year={1998} }
 @article{nagapudi_sunkavalli_baliga_1998, title={Effect of collector structure on the FBSOA of the dielectrically-isolated LIGBT}, volume={45}, ISSN={["1557-9646"]}, DOI={10.1109/16.669579}, abstractNote={In this paper, the dependence of the forward biased safe operating area (FBSOA) on the collector structures of the dielectrically-isolated (DI) lateral insulated gate bipolar transistor (LIGBT) has been analyzed. In addition to the on-state and switching characteristics, pulsed measurements were performed to determine the FBSOA of these devices. Two-dimensional (2-D) numerical simulations were performed to understand the physics behind the operation of devices fabricated with various collector designs. These studies reveal that some of the structures behave like the conventional LIGBT, while others behave like the LDMOSFET with respect to their FBSOA. Some of the structures also exhibit a unique high-voltage blocking ability while carrying current, while having much smaller breakdown voltages.}, number={5}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Nagapudi, V and Sunkavalli, R and Baliga, BJ}, year={1998}, month={May}, pages={1155–1161} }
 @article{sawant_baliga_1998, title={Improved DC-EST structure with diode diverter}, volume={34}, ISSN={["0013-5194"]}, DOI={10.1049/el:19980967}, abstractNote={A novel emitter switched thyristor (EST) structure with a diode diverter is introduced to obtain superior current saturation characteristics with an excellent forward bias safe operating area, without compromising the on-state voltage drop. The new structure consists of a diode diverter connected to the p-base region of the DC-EST. The saturation current density is lowered significantly, which is desirable to achieve a good saturation current safe operating area. Experimental results are reported to confirm the superior characteristics observed through simulations.}, number={13}, journal={ELECTRONICS LETTERS}, author={Sawant, S and Baliga, BJ}, year={1998}, month={Jun}, pages={1358–1360} }
 @article{sridevan_baliga_1998, title={Lateral N-channel inversion mode 4H-SiC MOSFET's}, volume={19}, ISSN={["0741-3106"]}, DOI={10.1109/55.701425}, abstractNote={Advances in MOS devices on silicon carbide (SiC) have been greatly hampered by the low inversion layer mobilities. In this paper, the electrical characteristics of lateral n-channel MOSFETs fabricated on 4H-SiC are reported for the first time. Inversion layer electron mobilities of 165 cm/sup 2//V/spl middot/s in 4H-SiC MOSFETs were measured at room temperature. These MOSFETs were fabricated using a low temperature deposited oxide, with subsequent oxidation anneal, as the gate dielectric.}, number={7}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Sridevan, S and Baliga, BJ}, year={1998}, month={Jul}, pages={228–230} }
 @article{raghunathan_baliga_1998, title={P-type 4H and 6H-SiC high-voltage Schottky barrier diodes}, volume={19}, ISSN={["0741-3106"]}, DOI={10.1109/55.661168}, abstractNote={High-voltage Schottky barrier diodes have been successfully fabricated for the first time on p-type 4H- and 6H-SiC using Ti as the barrier metal. Good rectification was confirmed at temperatures as high as 250/spl deg/C. The barrier heights were estimated to be 1.8-2.0 eV for 6H-SiC and 1.1-1.5 eV for 4H-SiC at room temperature using both I-V and C-V measurements. The specific on resistance (R/sub on,sp/) for 4H- and 6H-SiC were found to be 25 m/spl Omega/ cm/sup -2/ and 70 m/spl Omega/ cm/sup -2/ at room temperature. A monotonic decrease in resistance occurs with increasing temperature for both polytypes due to increased ionization of dopants. An analytical model is presented to explain the decrease of R/sub on,sp/ with temperature for both 4H and 6H-SiC which fits the experimental data. Critical electric field strength for breakdown was extracted for the first time in both p-type 4H and 6H-SiC using the breakdown voltage and was found to be 2.9/spl times/10/sup 6/ V/cm and 3.3/spl times/10/sup 6/ V/cm, respectively. The breakdown voltage remained fairly constant with temperature for 4H-SiC while it was found to decrease with temperature for 6H-SiC.}, number={3}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Raghunathan, R and Baliga, BJ}, year={1998}, month={Mar}, pages={71–73} }
 @article{mehrotra_baliga_1998, title={Reverse blocking lateral MOS-gated switches for AC power control applications}, volume={42}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(97)00286-4}, abstractNote={Two new high voltage reverse blocking lateral device structures, called the lateral MOS gated thyristor (LMGT) and lateral IGBT with P+-diverter (LIGBT-D), are presented. Both of these devices are designed to support high reverse voltage suitable for ac power control applications. These devices utilize thyristor current conduction controlled by MOS gate and realize MOS gate controlled switching and current saturation characteristics. The fabricated devices had a bidirectional blocking voltage capability of 600 V. Switching measurements yielded a turn-off time 3 and 5 μs for the LMGT and LIGBT-D devices.}, number={4}, journal={SOLID-STATE ELECTRONICS}, author={Mehrotra, M and Baliga, BJ}, year={1998}, month={Apr}, pages={573–579} }
 @article{raghunathan_baliga_1998, title={Role of defects in producing negative temperature dependence of breakdown voltage in SiC}, volume={72}, ISSN={["0003-6951"]}, DOI={10.1063/1.121591}, abstractNote={Electron beam induced current (EBIC) techniques were employed in order to understand the role of defects on the breakdown characteristics of SiC. EBIC images revealed that certain defects caused enhanced multiplication leading to the catastrophic failures in SiC diodes. The impact ionization coefficients for holes measured at the defective site (αp,eff) were found to be higher than those measured at a nondefective site. Also, αp,eff measured at the defective site was found to increase with increasing temperature in contrast with a defect free diode where αp decreases with increasing temperature, clearly indicating that the defects produce the observed negative temperature coefficient of breakdown voltage in SiC.}, number={24}, journal={APPLIED PHYSICS LETTERS}, author={Raghunathan, R and Baliga, BJ}, year={1998}, month={Jun}, pages={3196–3198} }
 @misc{sridevan_mclarty_baliga_1998, title={Silicon carbide switching devices having near ideal breakdown voltage capability and ultralow on-state resistance}, volume={5,742,076}, number={1998 Apr. 21}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Sridevan, S. and McLarty, P. K. and Baliga, B. J.}, year={1998}, month={Apr} }
 @misc{thapar_shenoy_baliga_1998, title={Static-induction transistors having heterojunction gates and methods of forming same}, volume={5,753,938}, number={1998 May 19}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Thapar, N. I. and Shenoy, P. M. and Baliga, B. J.}, year={1998}, month={May} }
 @article{venkataraghavan_baliga_1998, title={The dV/dt capability of MOS-gated thyristors}, volume={13}, ISSN={["0885-8993"]}, DOI={10.1109/63.704134}, abstractNote={In this paper, a detailed study of the dV/dt capability of MOS-gated thyristors is performed. It is shown that in addition to the conventional mode of dV/dt-induced turn-on in thyristors, termed the intrinsic mode, there exists another distinct mode of dV/dt-induced turn-on, peculiar to the MOS-gated thyristor structure, which the authors term the extrinsic dV/dt mode. The effective dV/dt capability is determined by both modes and is degraded by the presence of an external gate-cathode resistance and parasitic gate-anode capacitance. The existence of these two modes of dV/dt-induced turn-on is demonstrated experimentally, and the effect of device parameters on the dV/dt capability is studied.}, number={4}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Venkataraghavan, P and Baliga, BJ}, year={1998}, month={Jul}, pages={660–666} }
 @article{sunkavalli_baliga_1997, title={Analysis of on-state carrier distribution in the DI-LIGBT}, volume={41}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(96)00247-X}, abstractNote={The on-state carrier distribution in the drift region of the DI-LIGBT with thin silicon layers is studied in this paper. Numerical simulations indicate that carrier enhancement due to the formation of an accumulation region underneath the gate near the emitter has a strong impact on the on-state carrier distribution. This results in improved on-state characeristics by reducing the middle region voltage drop, due to the enhanced conductivity modulation of the drift region. A simple one-dimensional analytical modeling is carried out to study the effect of this carrier enhancement on on-state voltage drop. The results are verified by measurements performed on DI-LIGBTs fabricated on 5 and 10 μm thick silicon layers.}, number={5}, journal={SOLID-STATE ELECTRONICS}, author={Sunkavalli, R and Baliga, BJ}, year={1997}, month={May}, pages={733–738} }
 @article{sridhar_baliga_1997, title={Current saturation mechanism and FBOSA of the SIMEST}, volume={41}, ISSN={["0038-1101"]}, DOI={10.1016/S0038-1101(96)00202-X}, abstractNote={It is demonstrated that the current saturation mechanism for the SIMEST is due to operation of the thyristor region in a non-regenerative mode by the shunting of holes from the P-base region via a lateral P-MOSFET, a mechanism not observed in previous power devices. The FBSOA of the SIMEST is shown to be limited by avalanche breakdown in the drift region at low current densities and by the breakdown of the lateral N-channel MOSFET at high current densities. The effects of the parametric variations on the output characteristics and the FBSOA are reported for the first time.}, number={4}, journal={SOLID-STATE ELECTRONICS}, author={Sridhar, S and Baliga, BJ}, year={1997}, month={Apr}, pages={561–566} }
 @misc{baliga_thapar_1997, title={Depleted base transistor with high forward voltage blocking capability}, volume={5,679,966}, number={1997 Oct. 21}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Thapar, Naresh I.}, year={1997}, month={Oct} }
 @article{sunkavalli_baliga_tamba_1997, title={Dielectrically isolated lateral merged PiN Schottky (LMPS) diodes}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.641373}, abstractNote={The concept of the RESURF DI lateral merged PiN Schottky (LMPS) diodes is introduced and experimentally demonstrated. The LMPS diode combines the advantages of fast switching times of Schottky diodes with the low forward drops exhibited by LPiN diodes. An increase in the ratio of Schottky area relative to the p-n junction area is shown to result in superior reverse recovery characteristics at the expense of an increase in the forward voltage drop. This tradeoff between forward drop and switching speed is achieved in a simple manner by varying the relative areas of the Schottky and p-n junction regions during device design. Since lifetime control is not a viable option in integrated diodes used in power IC's, the LMPS concept allows tailoring the characteristics of integrated power diodes to the application frequency for the first time.}, number={11}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sunkavalli, R and Baliga, BJ and Tamba, A}, year={1997}, month={Nov}, pages={2011–2016} }
 @article{shenoy_baliga_1997, title={High voltage P+ polysilicon/N- 6H-SiC heterojunction diodes}, volume={33}, ISSN={["0013-5194"]}, DOI={10.1049/el:19970678}, abstractNote={A novel P/sup +/ polysilicon/N 6H-SiC heterojunction diode is reported which combines the advantages of both Schottky barrier diodes and pn junction diodes. The unterminated heterojunction diodes have excellent rectification characteristics and a high breakdown voltage of 220 V. The forward voltage drop measured at 100 A/cm/sup 2/ is 2.7 V, close to the calculated value of 2.4 V. The suitability of this device for high speed switching applications was experimentally confirmed using reverse recovery measurements.}, number={12}, journal={ELECTRONICS LETTERS}, author={Shenoy, PM and Baliga, BJ}, year={1997}, month={Jun}, pages={1086–1087} }
 @article{alok_baliga_1997, title={Kinetics of enhanced thermal oxidation of silicon carbide using amorphization by ion implantation}, volume={144}, ISSN={["0013-4651"]}, DOI={10.1149/1.1837545}, abstractNote={The kinetics of a thermal oxidation scheme with enhanced growth rate for 6H-SiC is reported in this paper. This scheme is based upon the formation of a thick amorphous layer created using high-dose ion implantation followed by thermal oxidation. The oxide thickness has been demonstrated to be larger in the amorphized region, when compared to the unimplanted (monocrystalline SiC) region, after dry oxidation. The oxide growth rate was parabolic in nature in the amorphized region, in contrast to a mixed linear-parabolic growth rate observed for the monocrystalline region.}, number={3}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Alok, D and Baliga, BJ}, year={1997}, month={Mar}, pages={1135–1137} }
 @misc{baliga_alok_1997, title={Methods of fabricating voltage breakdown resistant monocrystalline silicon carbide semiconductor devices}, volume={5,635,412}, number={1997 June 3}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Alok, D.}, year={1997}, month={Jun} }
 @misc{baliga_1997, title={Methods of forming silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein}, volume={5,681,762}, number={1997 Oct. 28}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1997}, month={Oct} }
 @article{sridhar_baliga_1997, title={Output characteristics of the dual channel EST}, volume={41}, ISSN={["1879-2405"]}, DOI={10.1016/S0038-1101(97)00036-1}, abstractNote={Analysis of the output characteristics of the Dual Channel EST (DC-EST) is provided for the first time in this article. It is demonstrated by analytical modelling and with the aid of two dimensional numerical simulations that the output resistance in the region of current saturation is determined by the activation of the narrow base NPN transistor in the IGBT segment. Based upon this model, the experimentally observed degradation in the output resistance with an increase in the distance between the shorts in the P-base region of the main thyristor segment can be explained. This model is shown to be consistent with the experimentally observed degradation in the output resistance with larger design rules used for device fabrication because this determines the current level at which the NPN transistor becomes activated. The observed reduction in the output resistance results in a degradation in the forward bias safe operating area.}, number={8}, journal={SOLID-STATE ELECTRONICS}, author={Sridhar, S and Baliga, BJ}, year={1997}, month={Aug}, pages={1133–1138} }
 @article{sridhar_baliga_1997, title={SIMFCT: A MOS-gated FCT with high voltage-current saturation}, volume={44}, ISSN={["1557-9646"]}, DOI={10.1109/16.641374}, abstractNote={This paper describes the SIMFCT: a new MOS-gated power device in which SIMOX technology is used to integrate a series MOSFET with a vertical FCT structure. The SIMFCT, exhibits high voltage-current saturation beyond the breakdown voltage of the lateral series MOSFET, and since it does not have a parasitic thyristor, it possesses a superior FBSOA when compared to the IGBT. The physics of device operation, results of two-dimensional numerical simulations and experimentally measured characteristics on SIMFCT structures fabricated using a nine mask SIMOX Smart Power process are presented.}, number={11}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Sridhar, S and Baliga, BJ}, year={1997}, month={Nov}, pages={2017–2021} }
 @misc{baliga_1997, title={Schottky barrier rectifiers and methods of forming same}, volume={5,612,567}, number={1997 Mar. 18}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1997}, month={Mar} }
 @article{alok_baliga_1997, title={SiC device edge termination using finite area argon implantation}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.585559}, abstractNote={In this paper, the results obtained with limited area amorphization by argon ion-implantation at the periphery of 6H-SiC Schottky barrier diodes are reported. It is demonstrated that only 50 /spl mu/m of implant region is required at the periphery to obtain ideal plane parallel breakdown voltages. The leakage current at small reverse bias voltages was found to be directly proportional to the implant area.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Alok, D and Baliga, BJ}, year={1997}, month={Jun}, pages={1013–1017} }
 @article{thapar_baliga_1997, title={The accumulation channel driven bipolar transistor (ACBT)}, volume={18}, ISSN={["1558-0563"]}, DOI={10.1109/55.568754}, abstractNote={A new three-terminal power switch called the Accumulation Channel driven Bipolar Transistor (ACBT) is proposed and experimentally demonstrated. In the on-state, the characteristics of the ACBT have been found to approach those of a P-I-N rectifier with a MOSFET in series for regulating its current, an equivalent circuit considered to be an ideal for MOS/Bipolar power devices. Unlike previous devices, the high off-state voltage is supported by the formation of a potential barrier to the flow of electrons from the N/sup +/ emitter into the N-drift region within a depletion region. The absence of the P-base region within the ACBT cells eliminates the parasitic four layer PNPN thyristor which had limited the performance of previous MOS/Bipolar transistor structures. Consequently, the ACBT structure has large maximum controllable and surge current densities in addition to low on-state voltage drop and high-voltage current saturation capability.}, number={5}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Thapar, N and Baliga, BJ}, year={1997}, month={May}, pages={178–180} }
 @misc{baliga_1997, title={Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance}, volume={5,637,898}, number={1997 June 10}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1997}, month={Jun} }
 @misc{baliga_1996, title={Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein}, volume={5543637}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1996}, month={Jun} }
 @misc{baliga_1995, title={Insulated gate bipolar transistor with reduced susceptibility to parasitic latch-up}, volume={5396087}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1995}, month={Jul} }
 @misc{baliga_1995, title={Multifunctional semiconductor switching device having gate-controlled regenerative and non-regenerative conduction modes, and method of operating same}, volume={5412228}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1995}, month={Feb} }
 @misc{baliga_1995, title={Silicon carbide switching device with rectifying-gate}, volume={5396085}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1995}, month={Jul} }
 @misc{shekar_baliga_1994, title={Emitter switched thyristor without parasitic thyristor latch-up susceptibility}, volume={5293054}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Shekar, M. S. and Baliga, B. J.}, year={1994}, month={Aug} }
 @misc{shekar_baliga_1994, title={MOS gated thyristor having on-state current saturation capability}, volume={5319222}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Shekar, M. S. and Baliga, B. J.}, year={1994}, month={Jul} }
 @article{bhatnagar_baliga_1993, title={COMPARISON OF 6H-SIC, 3C-SIC, AND SI FOR POWER DEVICES}, volume={40}, ISSN={["0018-9383"]}, DOI={10.1109/16.199372}, abstractNote={The drift region properties of 6H- and 3C-SiC-based Schottky rectifiers and power MOSFETs that result in breakdown voltages from 50 to 5000 V are defined. Using these values, the output characteristics of the devices are calculated and compared with those of Si devices. It is found that due to very low drift region resistance, 5000-V SiC Schottky rectifiers and power MOSFETs can deliver on-state current density of 100 A/cm/sup 2/ at room temperature with a forward drop of only 3.85 and 2.95 V, respectively. Both devices are expected to have excellent switching characteristics and ruggedness due to the absence of minority-carrier injection. A thermal analysis shows that 5000-V, 6H-, and 3C-SiC MOSFETs and Schottky rectifiers would be approximately 20 and 18 times smaller than corresponding Si devices, and that operation at higher temperatures and at higher breakdown voltages than conventional Si devices is possible. Also, a significant reduction in the die size is expected. >}, number={3}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={BHATNAGAR, M and BALIGA, BJ}, year={1993}, month={Mar}, pages={645–655} }
 @misc{baliga_1993, title={Silicon carbide power MOSFET with floating field ring and floating field plate}, volume={5233215}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1993}, month={Mar} }
 @misc{baliga_1991, title={Integrated circuit power device with automatic removal of defective devices and method of fabricating same}, volume={5021861}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.}, year={1991}, month={Apr} }
 @book{baliga, title={Advanced power MOSFET concepts}, publisher={New York: Springer}, author={Baliga, B. Jayant} }
 @misc{baliga, title={Asymmetrical field controlled thyristor}, volume={4,937,644}, number={1990 Jun. 26}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={Base resistance controlled thyristor with integrated single-polarity gate control}, volume={5241194}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={Base resistance controlled thyristor with single-polarity turn-on and turn-off control}, volume={5198687}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{mehrotra_baliga, title={Bidirectional AC switching device with MOS-gated turn-on and turn-off control}, volume={5493134}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Mehrotra, M. and Baliga, B. J.} }
 @misc{shekar_baliga_korec, title={Dual-channel emitter switched thyristor with trench gate}, volume={5,471,075}, number={1995 Nov. 28}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Shekar, M. S. and Baliga, B. J. and Korec, J.} }
 @misc{baliga, title={Electric field-controlled semiconductor device}, volume={4,132,996}, number={1979 Jan. 2}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={Emitter switched thyristor with buried dielectric layer}, volume={5306930}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={Field-controlled bipolar transistor}, volume={4,331,969}, number={1982 May 25}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga_houston_krishna, title={Gate modulated bipolar transistor}, volume={4,032,961}, number={1977 Jun. 28}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Houston, D. E. and Krishna, S.} }
 @misc{baliga, title={Gated base controlled thyristor}, volume={5,099,300}, number={1992 Mar. 24}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={High voltage silicon carbide MESFETs and methods of fabricating same}, volume={5399883}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @inbook{baliga, title={How the super-transistor works}, booktitle={The solid-state century: The past, present, and future of the transistor}, publisher={New York: Scientific American, Inc.}, author={Baliga, B. J.}, pages={34–41} }
 @misc{baliga_venkatraman, title={Integrated circuit power device with external disabling of defective devices and method of fabricating same}, volume={5446310}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Venkatraman, P.} }
 @misc{baliga, title={Integrated circuit power device with transient responsive current limiting means}, volume={5392187}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{nandakumar_baliga, title={Integrated multicelled semiconductor switching device for high current applications}, volume={5296725}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Nandakumar, M. and Baliga, B. J.} }
 @misc{baliga_korec, title={Latch-up resistant bipolar transistor with trench IGFET and buried collector}, volume={5,488,236}, number={1996 Jan. 30}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Korec, J.} }
 @misc{shekar_baliga, title={MOS gated thyristor with remote turn-off electrode}, volume={5317171}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Shekar, M. S. and Baliga, B. J.} }
 @misc{tu_baliga, title={Merged P-I-N/Schottky power rectifier having extended P-I-N junction}, volume={5241195}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Tu, S.-H. L. and Baliga, B. J.} }
 @misc{baliga_alok_bhatnagar, title={Method for forming a p-n junction in silicon carbide}, volume={5,318,915}, number={1994 Jun. 7}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J and Alok, D. and Bhatnagar, M.} }
 @misc{baliga, title={Method for forming an oxide-filled trench in silicon carbide}, volume={5270244}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga, title={Method of fabricating high voltage silicon carbide MESFETs}, volume={5459089}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga_bhatnagar, title={Method of fabricating silicon carbide field effect transistor}, volume={5322802}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Bhatnagar, M.} }
 @misc{baliga_alok, title={Method of forming trenches in monocrystalline silicon carbide}, volume={5,436,174}, number={1995 Jul. 25}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Alok, D.} }
 @inproceedings{sung_han_baliga, title={Optimization of the JFET region of 1.2kV SiC MOSFETs for improved high frequency figure of merit (HF-FOM)}, booktitle={2017 IEEE 5th Workshop on Wide Bandgap Power Devices and Applications (WIPDA)}, author={Sung, W. J. and Han, K. J. and Baliga, B. J.}, pages={238–241} }
 @inbook{baliga, title={Power devices}, booktitle={Modern semiconductor device physics}, publisher={New York: Wiley}, author={Baliga, B. J.}, pages={183–252} }
 @misc{tu_baliga, title={Schottky barrier rectifier including schottky barrier regions of differing barrier heights}, volume={5262668}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Tu, S.-H. L. and Baliga, B. J.} }
 @misc{mehrotra_baliga, title={Schottky barrier rectifier with MOS trench}, volume={5365102}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Mehrotra, M. and Baliga, B. J.} }
 @misc{temple_baliga, title={Self-protection against breakover turn-on failure in thyristors through selective base lifetime control}, volume={4,165,517}, number={1979 Aug. 21}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Temple, V. A. K. and Baliga, B. J.} }
 @book{baliga, title={Silicon RF power MOSFETS}, ISBN={9812561218}, publisher={Singapore; Hackensack, NJ: World Scientific}, author={Baliga, B. J.} }
 @misc{baliga, title={Silicon carbide field effect device}, volume={5323040}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{baliga_bhatnagar, title={Silicon carbide field effect transistor}, volume={5338945}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Bhatnagar, M.} }
 @misc{baliga, title={Trench gate lateral MOSFET}, volume={5,434,435}, number={1995 Jul. 18}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J.} }
 @misc{shekar_nandakumar_baliga, title={Unit cell arrangement for emitter switched thyristor with base resistance control}, volume={5294816}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Shekar, M. S. and Nandakumar, M. and Baliga, B. J.} }
 @misc{baliga_alok, title={Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices}, volume={5,449,925}, number={1995 Sep. 12}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Baliga, B. J. and Alok, D.} }