2009 conference paper

The Benefits of 3D networks-on-chip as shown with LDPC decoding

2009 IEEE International Conference on 3d Systems Integration, 89–96.

By: C. Mineo n & W. Davis n

TL;DR: The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC componets built from detailed circuit simulation. (via Semantic Scholar)
UN Sustainable Development Goal Categories
9. Industry, Innovation and Infrastructure (OpenAlex)
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2005 journal article

Demystifying 3D ICs: The procs and cons of going vertical


By: W. Davis n, J. Wilson n, S. Mick n, M. Xu*, H. Hua*, C. Mineo n, A. Sule n, M. Steer n, P. Franzon n

TL;DR: A practical introduction to the design trade-offs of the currently available 3D IC technology options is provided, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Sources: Web Of Science, ORCID
Added: August 6, 2018

Citation Index includes data from a number of different sources. If you have questions about the sources of data in the Citation Index or need a set of data which is free to re-distribute, please contact us.

Certain data included herein are derived from the Web of Science© and InCites© (2024) of Clarivate Analytics. All rights reserved. You may not copy or re-distribute this material in whole or in part without the prior written consent of Clarivate Analytics.