@inproceedings{mineo_davis_2009, title={The Benefits of 3D networks-on-chip as shown with LDPC decoding}, DOI={10.1109/3dic.2009.5306585}, abstractNote={In this work we describe our network-on-chip (NoC) simulator, which fills the gap between architectural level and circuit level NoC simulation. The core is a fast, high level transaction-based NoC simulator, which accesses carefully compiled power, timing, and area models for basic NoC componets built from detailed circuit simulation. It makes use of the architectural evaluator, which performs a detailed global interconnect analysis within the framework of industry-standard design tools. Using low density parity check decoding as a test vehicle, the NoC simulator is used in an NoC design study comparing 2D and 3D integrated circuits, and shows a method by which on-chip networks can be optimized.}, booktitle={2009 IEEE International Conference on 3d Systems Integration}, author={Mineo, C. and Davis, W. R.}, year={2009}, pages={89–96} }
 @article{davis_wilson_mick_xu_hua_mineo_sule_steer_franzon_2005, title={Demystifying 3D ICs: The procs and cons of going vertical}, volume={22}, ISSN={["1558-1918"]}, DOI={10.1109/MDT.2005.136}, abstractNote={This article provides a practical introduction to the design trade-offs of the currently available 3D IC technology options. It begins with an overview of techniques, such as wire bonding, microbumps, through vias, and contactless interconnection, comparing them in terms of vertical density and practical limits to their use. We then present a high-level discussion of the pros and cons of 3D technologies, with an analysis relating the number of transistors on a chip to the vertical interconnect density using estimates based on Rent's rule. Next, we provide a more detailed design example of inductively coupled interconnects, with measured results of a system fabricated in a 0.35-/spl mu/m technology and an analysis of misalignment and crosstalk tolerances. Lastly, we present a case study of a fast Fourier transform (FFT) placed and routed in a 0.18-/spl mu/m through-via silicon-on-insulator (SOI) technology, comparing the 3D design to a traditional 2D approach in terms of wire length and critical-path delay.}, number={6}, journal={IEEE DESIGN & TEST OF COMPUTERS}, author={Davis, WR and Wilson, J and Mick, S and Xu, M and Hua, H and Mineo, C and Sule, AM and Steer, M and Franzon, PD}, year={2005}, pages={498–510} }