@article{zimmer_bhat_mueller_mohan_2015, title={Intrusion Detection for CPS Real-Time Controllers}, ISBN={["978-3-662-45927-0"]}, ISSN={["1860-4676"]}, DOI={10.1007/978-3-662-45928-7_12}, abstractNote={Security in CPS-based real-time embedded systems controlling the power grid has been an afterthought, but it is becoming a critical issue as CPS systems are networked and inter-dependent. This work presents a set of mechanisms for timebased intrusion detection, i.e., the execution of unauthorized instructions in realtime CPS environments. The novelty is the utilization of information obtained by static timing analysis for intrusion detection. Real-time CPS systems are unique in that timing bounds on code sections are readily available since they are required for schedulability analysis.We demonstrate how micro-timings can be exploited for multiple granularity levels of application code to track execution progress. Through bounds checking of these micro-timings, we develop techniques to detect intrusions (1) in a self-checking manner by the application and (2) through the operating system scheduler, which are novel contributions to the real-time/embedded systems domain to the best of our knowledge.}, journal={CYBER PHYSICAL SYSTEMS APPROACH TO SMART ELECTRIC POWER GRID}, author={Zimmer, Christopher and Bhat, Balasubramany and Mueller, Frank and Mohan, Sibin}, year={2015}, pages={329–358} }
 @article{zimmer_mueller_2015, title={NoCMsg: A Scalable Message-Passing Abstraction for Network-on-Chips}, volume={12}, ISSN={["1544-3973"]}, DOI={10.1145/2701426}, abstractNote={The number of cores of contemporary processors is constantly increasing and thus continues to deliver ever higher peak performance (following Moore’s transistor law). Yet high core counts present a challenge to hardware and software alike. Following this trend, the network-on-chip (NoC) topology has changed from buses over rings and fully connected meshes to 2D meshes.}, number={1}, journal={ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION}, author={Zimmer, Christopher and Mueller, Frank}, year={2015}, month={Apr} }
 @article{zimmer_mueller_2015, title={Reliable and scalable communication for the power grid}, DOI={10.1007/978-3-662-45928-7_8}, abstractNote={Future smart power grids require constant data availability for actuation of control decisions. The job of ensuring the timely arrival of data falls onto the network that connects these intelligent devices. This network needs to be fault tolerant. When nodes, devices or communication links fail along a default route of a message from A to B, the underlying hardware and software layers should ensure that this message will actually be delivered as long as alternative routes exist. Existence and discovery of multi-route pathways is essential in ensuring delivery of critical data. In this work, we present methods of developing network topologies of smart devices that enable multi-route discovery in an intelligent power grid. This is accomplished through the utilization of software overlays that (1) maintain a digital structure for the physical network and (2) identify new routes in the case of faults. The resulting cyber network structure is scalable, reliable and inexpensive to build by extending existing infrastructure.}, journal={Cyber physical systems approach to smart electric power grid}, author={Zimmer, C. and Mueller, F.}, year={2015}, pages={195–217} }
 @article{zimmer_mueller_2014, title={NoCMsg: Scalable NoC-Based Message Passing}, ISSN={["2376-4414"]}, DOI={10.1109/ccgrid.2014.19}, abstractNote={Current processor design with ever more cores may ensure that theoretical compute performance still follows past increases (resting from Moore's law), but they also increasingly present a challenge to hardware and software alike. As the core count increases, the network-on-chip(NoC) topology has changed from buses over rings and fully connected meshes to 2D meshes. The question is which programming paradigm provides the scalability needed to ensure performance is close to theoretical peak, where 2D meshes provide the most scalable design to date. This work contributes NoCMsg, a low-level message passing abstraction over NoCs. NoCMsg is specifically designed for large core counts in2D meshes. Its design ensures deadlock free messaging for wormhole Manhattan-path routing over the NoC. Experimental results on the Tile Pro hardware platform show that NoCMsg can significantly reduce communication times by up to 86% for single packet messages and up to40% for larger messages compared to other NoC-based message approaches. Results further demonstrate the potential of NoC messaging to outperform shared memory abstractions by up to 93% as core counts and inter-process communication increase, i.e., we observe that shared memory scales up to about 16 cores while message passing performs well beyond that threshold on this platform. To the best of our knowledge, this is the first head-on comparison of shared memory and advanced message passing specifically designed for NoCs on an actual hardware platform with larger core counts on a single socket.}, journal={2014 14TH IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND GRID COMPUTING (CCGRID)}, author={Zimmer, Christopher and Mueller, Frank}, year={2014}, pages={186–195} }
 @article{zimmer_mueller_2012, title={Low ContentionMapping of Real-Time Tasks onto a TilePro 64 Core Processor}, ISSN={["1545-3421"]}, DOI={10.1109/rtas.2012.36}, abstractNote={Predictability of task execution is paramount for real-time systems so that upper bounds of execution times can be determined via static timing analysis. Static timing analysis on network-on-chip (NoC) processors may result in unsafe underestimations when the underlying communication paths are not considered. This stems from contention on the underlying network when data from multiple sources share parts of a routing path in the NoC. Contention analysis must be performed to provide safe and reliable bounds. In addition, the overhead incurred by contention due to inter-process communication (IPC) can be reduced by mapping tasks to cores in such a way that contention is minimized. This paper makes several contributions to increase pre-predictability of real-time tasks on NoC architectures. First, we contribute a constraint solver that exhaustively maps real-time tasks onto cores to minimize contention and improve predictability. Second, we develop a novel TDMA-like approach to map communication traces into time frames to ensure separation of analysis for temporally disjoint communication. Third, we contribute a novel multi-heuristic approximation, H Solver, for rapid discovery of low contention solutions. H Solver reduces contention by up to 70% when compared with naive and constrained exhaustive solutions. We evaluate our experiments using a micro-benchmark of task system IPC on the TilePro64, a real, physical NoC processor with 64 cores. To the best of our knowledge, this is the first work to consider IPC for worst-case time frames to simplify analysis and to measure the impact on actual hardware for NoC-based real-time multi core systems.}, journal={2012 IEEE 18TH REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM (RTAS)}, author={Zimmer, Christopher and Mueller, Frank}, year={2012}, pages={131–140} }