Works (7)
Updated: December 4th, 2023 07:07
2018 journal article
Developing Noise-Resistant Three-Dimensional Single Particle Tracking Using Deep Neural Networks
ANALYTICAL CHEMISTRY, 90(18), 10748–10757.
MeSH headings : Fluorescent Dyes / chemistry; Imaging, Three-Dimensional; Microscopy, Fluorescence; Neural Networks, Computer; Particle Size; Signal-To-Noise Ratio
TL;DR:
This work test deep neural networks (DNNs) in recognizing and differentiating very similar image patterns incurred in 3D SPT and shows that for high S/N images, both DNNs and conventional correlation coefficient-based method perform well, however, when theS/N drops close to 1, conventional methods completely fail while DNN's show strong resistance to both artificial and experimental noises.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
3. Good Health and Well-being
(Web of Science)
Sources: Web Of Science, NC State University Libraries
Added: October 16, 2018
2016 article
A Model-Driven Approach to Warp/Thread-Block Level GPU Cache Bypassing
2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC).
TL;DR:
This paper proposes a simple yet effective performance model to estimate the impact of cache contention and resource congestion as a function of the number of warps/thread blocks to bypass the cache, and designs a hardware-based dynamic warp/thread-block level GPU cache bypassing scheme.
(via Semantic Scholar)
dl.acm.org (publisher PDF)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2016 conference paper
Optimizing memory efficiency for deep convolutional neural networks on GPUs
SC '16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 633–644.
TL;DR:
This work studies the memory efficiency of various CNN layers and reveals the performance implication from both data layouts and memory access patterns, which shows the universal effect of the proposed optimizations on both single layers and various networks.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2015 conference paper
Automatic data placement into GPU on-chip memory resources
2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 23–33.
TL;DR:
This paper focuses on programs that have already been reasonably optimized either manually by programmers or automatically by compiler tools and proposed compiler algorithms refine these programs by revising data placement across different types of GPU on-chip resources to achieve both performance enhancement and performance portability.
(via Semantic Scholar)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2015 journal article
CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 30(1), 3–19.
author keywords: GPGPU; nested parallelism; compiler; local memory
TL;DR:
This paper first study a set of GPGPU benchmarks that contain parallel loops, and highlights that the benefits of leveraging such parallel loops using dynamic parallelism are too limited to offset its overhead, and presents the proposed solution to exploit nested parallelism in CUDA, referred to as CUDA-NP.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2014 conference paper
Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs
Ieee international symposium on performance analysis of systems and, 231–241.
Source: NC State University Libraries
Added: August 6, 2018
2014 conference paper
yaSpM: Yet Another SpMV Framework on GPUs
Proceedings of the 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 49(8), 107–118.
Event: 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming at Orlando, FL
author keywords: SpMV; Segmented Scan; BCCOO; OpenCL; CUDA; GPU; Parallel algorithms
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
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