Chao Li

Developing Noise-Resistant Three-Dimensional Single Particle Tracking Using Deep Neural Networks

ANALYTICAL CHEMISTRY, 90(18), 10748–10757.

A model-driven approach to warp/thread-block level CPU cache bypassing

2016 53rd acm/edac/ieee design automation conference (dac).

Optimizing memory efficiency for deep convolutional neural networks on GPUs

SC '16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 633–644.

Automatic data placement into GPU on-chip memory resources

2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 23–33.

CUDA-NP: Realizing nested thread-level parallelism in GPGPU applications

Journal of Computer Science and Technology, 30(1), 3–19.

Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs

Ieee international symposium on performance analysis of systems and, 231–241.

yaSpMV: Yet another SpMV framework on GPUs

ACM SIGPLAN Notices, 49(8), 107–118.