Works (7)

Updated: December 4th, 2023 07:07

2018 journal article

Developing Noise-Resistant Three-Dimensional Single Particle Tracking Using Deep Neural Networks

ANALYTICAL CHEMISTRY, 90(18), 10748–10757.

By: Y. Zhong n, C. Li n, H. Zhou n  & G. Wang n

co-author countries: United States of America πŸ‡ΊπŸ‡Έ
MeSH headings : Fluorescent Dyes / chemistry; Imaging, Three-Dimensional; Microscopy, Fluorescence; Neural Networks, Computer; Particle Size; Signal-To-Noise Ratio
Sources: Web Of Science, ORCID
Added: October 16, 2018

2016 article

A Model-Driven Approach to Warp/Thread-Block Level GPU Cache Bypassing

2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC).

By: H. Dai n, C. Li n, H. Zhou n , S. Gupta *, C. Kartsaklis* & M. Mantor*

co-author countries: United States of America πŸ‡ΊπŸ‡Έ
Sources: Web Of Science, ORCID
Added: August 6, 2018

2016 conference paper

Optimizing memory efficiency for deep convolutional neural networks on GPUs

SC '16: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, 633–644.

By: C. Li n, Y. Yang *, M. Feng *, S. Chakradhar* & Huiyang

co-author countries: Japan πŸ‡―πŸ‡΅ United States of America πŸ‡ΊπŸ‡Έ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2015 conference paper

Automatic data placement into GPU on-chip memory resources

2015 IEEE/ACM International Symposium on Code Generation and Optimization (CGO), 23–33.

By: C. Li n, Y. Yang *, Z. Lin n  & H. Zhou n 

co-author countries: Japan πŸ‡―πŸ‡΅ United States of America πŸ‡ΊπŸ‡Έ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2015 journal article

CUDA-NP: Realizing Nested Thread-Level Parallelism in GPGPU Applications

JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 30(1), 3–19.

By: Y. Yang *, C. Li n & H. Zhou n 

co-author countries: United States of America πŸ‡ΊπŸ‡Έ
author keywords: GPGPU; nested parallelism; compiler; local memory
Sources: Web Of Science, ORCID
Added: August 6, 2018

2014 conference paper

Understanding the tradeoffs between software-managed vs. hardware-managed caches in GPUs

Ieee international symposium on performance analysis of systems and, 231–241.

By: C. Li, Y. Yang, H. Dai, S. Yan, F. Mueller & H. Zhou 

Source: NC State University Libraries
Added: August 6, 2018

2014 conference paper

yaSpM: Yet Another SpMV Framework on GPUs

Proceedings of the 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 49(8), 107–118.

By: S. Yan*, C. Li n, Y. Zhang* & H. Zhou n 

co-author countries: China πŸ‡¨πŸ‡³ United States of America πŸ‡ΊπŸ‡Έ

Event: 19th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming at Orlando, FL

author keywords: SpMV; Segmented Scan; BCCOO; OpenCL; CUDA; GPU; Parallel algorithms
Sources: Web Of Science, ORCID
Added: August 6, 2018

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