Works (23)
Updated: July 5th, 2023 16:04
2007 chapter
Combining cluster sampling with single pass methods for efficient sampling regimen design
In 2007 IEEE International Conference On Computer Design (pp. 472–479). New York: IEEE.
Source: NC State University Libraries
Added: August 6, 2018
2005 journal article
Enhancing memory-level parallelism via recovery-free value prediction
IEEE Transactions on Computers, 54(7), 897–912.
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2005 journal article
High-performance and low-cost dual-thread VLIW processor using weld architecture paradigm
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 16(12), 1132–1142.
author keywords: multithreaded processors; VLIW architectures; modeling of computer architecture
TL;DR:
This paper analyzes the performance impact of the dual-thread VLIW processor, which includes analysis of migrating disambiguation hardware for speculative load operations to the compiler and of the sensitivity of the model to the variation of branch misprediction, second-level cache miss penalties, and register file copy time.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
2005 journal article
Optimal chip-package codesign for high-performance DSP
IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28(2), 288–297.
author keywords: chip-package codesign; fast Fourier transform (FFT); seamless high off-chip connectivity (SHOCC)
TL;DR:
This paper presents the design of a fast Fourier transform (FFT) engine that gives SRAM-like performance in a DRAM-based system and uses almost 100% of the available burst-mode memory bandwidth.
(via Semantic Scholar)
citeseerx.ist.psu.edu (repository)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
2004 journal article
Opportunities and challenges in embedded systems
IEEE Micro, 24(4), 38208.
Source: NC State University Libraries
Added: August 6, 2018
2003 journal article
Adaptive mode control: A static-power-efficient cache design
ACM Transactions on Embedded Computing Systems, 2(3), 347–372.
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2003 journal article
Modeling value speculation: An optimal edge selection problem
IEEE TRANSACTIONS ON COMPUTERS, 52(3), 277–292.
author keywords: value prediction; value speculation; optimal edge selection; data dependence graph; critical path reduction
TL;DR:
From the experimental results of running the optimal edge selection algorithm for the 20 most heavily executed paths selected from each SPECint95 benchmark, several insights are shown.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
2003 chapter
Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors
In Languages and Compilers for Parallel Computing (Vol. 2624, pp. 223–238).
TL;DR:
This paper presents a new global scheduling algorithm using treegions called Tree Traversal Scheduling (TTS), and considers them analogous to superblocks with the same amount of code expansion as the base treegion.
(via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, Crossref
Added: August 6, 2018
2002 article
Choosing the brain(s) of an embedded system
Conte, T. M. (2002, July). COMPUTER, Vol. 35, pp. 106–107.
TL;DR:
Embedded processors are fundamentally different from desktop processors -costs are too tight for fancy chip sets and expensive packaging.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
11. Sustainable Cities and Communities
(Web of Science)
Source: Web Of Science
Added: August 6, 2018
2001 conference paper
Adaptive mode control: A static-power-efficient cache design
2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70.
TL;DR:
Simulations show an average of 73% of I-cache lines and 54% of D-cache lines are put in sleep mode with an average IPC impact of only 1.7%, for 64KB caches, and this work proposes applying sleep mode only to the data store and not the tag store.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018
2000 journal article
Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility
IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814–825.
author keywords: microarchitecture; processor architecture; instruction cache; VLIW; instruction-set encoding; list encoding
TL;DR:
This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code, and presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPa of the code.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
2000 journal article
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137.
author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
TL;DR:
This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications and the use of a near-optimal search to tailor a processor design to a benchmark.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
1999 article
30th Annual ACM/IEEE International Symposium on Microarchitecture, Part II - Editors' Introduction
Conte, T., Hwu, W. M., & Smotherman, M. (1999, December). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 425–426.
TL;DR:
This volume represents contributions to this important topic by leading researchers in the field of forecasting and includes the latest research on forecasting macroeconomic and financial variables in the presence of structural breaks and/or model uncertainty.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1999 article
Challenges in processor modeling and validation
IEEE MICRO, Vol. 19, pp. 9–14.
TL;DR:
The methodology for designing state-of-the-art microprocessors involves modeling at various levels of abstraction, which can range from early-stage (microarchitectural) performance-only models to final-stage, detailed register-transfer-level (RTL) models.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1999 article
Special issue: 30th Annual ACM/IEEE International Symposium on Microarchitecture, Part I
Conte, T., Hwu, W. M., & Smotherman, M. (1999, October). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 325–326.
TL;DR:
This special issue on InstructionLevel Parallel Processing introduces this collection of new and exciting technical papers in this subject area and introduces the three papers that appear in the current issue.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1998 journal article
Combining trace sampling with single pass methods for efficient cache simulation
IEEE TRANSACTIONS ON COMPUTERS, 47(6), 714–720.
author keywords: performance analysis; sampling techniques; single pass algorithms; stacking algorithms; trace-driven simulation
TL;DR:
A single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1998 journal article
MPS: Miss-path scheduling for multiple-issue processors
IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397.
author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
TL;DR:
This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS, which is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1998 journal article
Performance analysis and its impact on design
COMPUTER, 31(5), 41–49.
TL;DR:
This work focuses on architectural performance, typically measured in cycles per instruction, and covers some of the advances in dealing with modern problems in performance analysis.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1998 journal article
Subword extensions for video processing on mobile systems
IEEE CONCURRENCY, 6(3), 13–16.
TL;DR:
Most general purpose microprocessor architectures have recently extended their instruction set architectures to include parallel instructions for improved performance on multimedia applications, including MPEG (Motion Pictures Expert Group) video, which includes micro SIMD execution using packed data types.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Source: Web Of Science
Added: August 6, 2018
1998 conference paper
Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures
Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308–315. Los Alamitos, Calif.: IEEE Computer Society Press.
Source: NC State University Libraries
Added: August 6, 2018
1998 journal article
Value speculation scheduling for high performance processors
ACM SIGPLAN NOTICES, 33(11), 262–271.
author keywords: value speculation; value prediction; VLIW instruction scheduling; instruction level parallelism
Source: Web Of Science
Added: August 6, 2018
1997 journal article
Compilers for instruction-level parallelism
COMPUTER, 30(12), 63-&.
TL;DR:
Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance, as research continues to find better ways to use more hardware parallelism over a broader class of applications.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
1997 article
Optimization of VLIW compatibility systems employing dynamic rescheduling
Conte, T. M., & Sathaye, S. W. (1997, April). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83–112.
author keywords: object-code compatibility; dynamic rescheduling; instruction level parallelism
TL;DR:
This paper presents a technique called Dynamic Rescheduling that applies software techniques dynamically, using intervention by the OS: at each first-time page fault, the page of code is rescheduled for the new generation, if required.
(via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018
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