Thomas M. Conte

Combining cluster sampling with single pass methods for efficient sampling regimen design

In 2007 IEEE International Conference On Computer Design (pp. 472–479). New York: IEEE.

Enhancing memory-level parallelism via recovery-free value prediction

IEEE Transactions on Computers, 54(7), 897–912.

Enhancing memory-level parallelism via recovery-free value prediction

IEEE Transactions on Computers, 54, 897–912.

High-performance and low-cost dual-thread VLIW processor using weld architecture paradigm

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 16(12), 1132–1142.

Optimal chip-package codesign for high-performance DSP

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28(2), 288–297.

Opportunities and challenges in embedded systems

IEEE Micro, 24(4), 38208.

Adaptive mode control: A static-power-efficient cache design

ACM Transactions on Embedded Computing Systems, 2(3), 347–372.

Modeling value speculation: An optimal edge selection problem

IEEE TRANSACTIONS ON COMPUTERS, 52(3), 277–292.

Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors

In Languages and Compilers for Parallel Computing (Vol. 2624, pp. 223–238).

Choosing the brain(s) of an embedded system

Conte, T. M. (2002, July). COMPUTER, Vol. 35, pp. 106–107.

Adaptive mode control: A static-power-efficient cache design

2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70.

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814–825.

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137.

30th Annual ACM/IEEE International Symposium on Microarchitecture, Part II - Editors' Introduction

Conte, T., Hwu, W. M., & Smotherman, M. (1999, December). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 425–426.

Challenges in processor modeling and validation

IEEE MICRO, Vol. 19, pp. 9–14.

Special issue: 30th Annual ACM/IEEE International Symposium on Microarchitecture, Part I

Conte, T., Hwu, W. M., & Smotherman, M. (1999, October). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 325–326.

Combining trace sampling with single pass methods for efficient cache simulation

IEEE TRANSACTIONS ON COMPUTERS, 47(6), 714–720.

MPS: Miss-path scheduling for multiple-issue processors

IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397.

Performance analysis and its impact on design

COMPUTER, 31(5), 41–49.

Subword extensions for video processing on mobile systems

IEEE CONCURRENCY, 6(3), 13–16.

Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures

Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308–315. Los Alamitos, Calif.: IEEE Computer Society Press.

Value speculation scheduling for high performance processors

ACM SIGPLAN NOTICES, 33(11), 262–271.

Compilers for instruction-level parallelism

COMPUTER, 30(12), 63-&.

Optimization of VLIW compatibility systems employing dynamic rescheduling

Conte, T. M., & Sathaye, S. W. (1997, April). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83–112.