Works (23)

Updated: July 5th, 2023 16:04

2007 chapter

Combining cluster sampling with single pass methods for efficient sampling regimen design

In 2007 IEEE International Conference On Computer Design (pp. 472โ€“479). New York: IEEE.

By: P. Bryan & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

2005 journal article

Enhancing memory-level parallelism via recovery-free value prediction

IEEE Transactions on Computers, 54(7), 897โ€“912.

By: Huiyang & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2005 journal article

High-performance and low-cost dual-thread VLIW processor using weld architecture paradigm

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 16(12), 1132โ€“1142.

By: E. Ozer* & T. Conte n

co-author countries: United Kingdom of Great Britain and Northern Ireland ๐Ÿ‡ฌ๐Ÿ‡ง United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: multithreaded processors; VLIW architectures; modeling of computer architecture
Source: Web Of Science
Added: August 6, 2018

2005 journal article

Optimal chip-package codesign for high-performance DSP

IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28(2), 288โ€“297.

By: P. Mehrotra n, V. Rao n, T. Conte n & P. Franzon nโ€‰

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: chip-package codesign; fast Fourier transform (FFT); seamless high off-chip connectivity (SHOCC)
Sources: Web Of Science, ORCID
Added: August 6, 2018

2004 journal article

Opportunities and challenges in embedded systems

IEEE Micro, 24(4), 38208.

By: A. Bechini, T. Conte & C. Prete

Source: NC State University Libraries
Added: August 6, 2018

2003 journal article

Adaptive mode control: A static-power-efficient cache design

ACM Transactions on Embedded Computing Systems, 2(3), 347โ€“372.

By: Huiyang, M. Toburen n, E. Rotenberg n & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2003 journal article

Modeling value speculation: An optimal edge selection problem

IEEE TRANSACTIONS ON COMPUTERS, 52(3), 277โ€“292.

By: C. Fu, J. Bodine n & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: value prediction; value speculation; optimal edge selection; data dependence graph; critical path reduction
Source: Web Of Science
Added: August 6, 2018

2003 chapter

Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors

In Languages and Compilers for Parallel Computing (Vol. 2624, pp. 223โ€“238).

By: H. Zhou nโ€‰, M. Jenningsโ€‰ n & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: Web Of Science, ORCID, Crossref
Added: August 6, 2018

2002 article

Choosing the brain(s) of an embedded system

Conte, T. M. (2002, July). COMPUTER, Vol. 35, pp. 106โ€“107.

By: T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

2001 conference paper

Adaptive mode control: A static-power-efficient cache design

2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61โ€“70.

By: Huiyang, M. Toburen n, E. Rotenberg n & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Sources: NC State University Libraries, ORCID
Added: August 6, 2018

2000 journal article

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814โ€“825.

By: T. Conte n & S. Sathaye*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: microarchitecture; processor architecture; instruction cache; VLIW; instruction-set encoding; list encoding
Source: Web Of Science
Added: August 6, 2018

2000 journal article

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129โ€“137.

By: T. Conte n, K. Menezes*, S. Sathaye* & M. Toburen n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
Source: Web Of Science
Added: August 6, 2018

1999 article

30th Annual ACM/IEEE International Symposium on Microarchitecture, Part II - Editors' Introduction

Conte, T., Hwu, W. M., & Smotherman, M. (1999, December). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 425โ€“426.

By: T. Conte*, W. Hwu & M. Smotherman

Source: Web Of Science
Added: August 6, 2018

1999 article

Challenges in processor modeling and validation

IEEE MICRO, Vol. 19, pp. 9โ€“14.

By: P. Boseโ€‰*, T. Conte n & T. Austin*

co-author countries: United Kingdom of Great Britain and Northern Ireland ๐Ÿ‡ฌ๐Ÿ‡ง United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

1999 article

Special issue: 30th Annual ACM/IEEE International Symposium on Microarchitecture, Part I

Conte, T., Hwu, W. M., & Smotherman, M. (1999, October). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 325โ€“326.

By: T. Conte*, W. Hwu & M. Smotherman

Source: Web Of Science
Added: August 6, 2018

1998 journal article

Combining trace sampling with single pass methods for efficient cache simulation

IEEE TRANSACTIONS ON COMPUTERS, 47(6), 714โ€“720.

By: T. Conte n, M. Hirsch n & W. Hwuโ€‰*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: performance analysis; sampling techniques; single pass algorithms; stacking algorithms; trace-driven simulation
Source: Web Of Science
Added: August 6, 2018

1998 journal article

MPS: Miss-path scheduling for multiple-issue processors

IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382โ€“1397.

By: S. Banerjia*, S. Sathaye*, K. Menezes* & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
Source: Web Of Science
Added: August 6, 2018

1998 journal article

Performance analysis and its impact on design

COMPUTER, 31(5), 41โ€“49.

By: P. Boseโ€‰* & T. Conte*

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

1998 journal article

Subword extensions for video processing on mobile systems

IEEE CONCURRENCY, 6(3), 13โ€“16.

By: M. Jenningsโ€‰ n & T. Conte

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

1998 conference paper

Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures

Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308โ€“315. Los Alamitos, Calif.: IEEE Computer Society Press.

By: E. Ozer, S. Banerjia & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

1998 journal article

Value speculation scheduling for high performance processors

ACM SIGPLAN NOTICES, 33(11), 262โ€“271.

By: C. Fu n, M. Jenningsโ€‰ n, S. Larin n & T. Conte n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: value speculation; value prediction; VLIW instruction scheduling; instruction level parallelism
Source: Web Of Science
Added: August 6, 2018

1997 journal article

Compilers for instruction-level parallelism

COMPUTER, 30(12), 63-&.

By: M. Schlansker*, T. Conte n, J. Dehnert, K. Ebciogluโ€‰*, J. Fangโ€‰* & C. Thompson*

co-author countries: Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ United States of America ๐Ÿ‡บ๐Ÿ‡ธ
Source: Web Of Science
Added: August 6, 2018

1997 article

Optimization of VLIW compatibility systems employing dynamic rescheduling

Conte, T. M., & Sathaye, S. W. (1997, April). INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83โ€“112.

By: T. Conte n & S. Sathaye n

co-author countries: United States of America ๐Ÿ‡บ๐Ÿ‡ธ
author keywords: object-code compatibility; dynamic rescheduling; instruction level parallelism
Source: Web Of Science
Added: August 6, 2018

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