Thomas M. Conte

Works (24)

Updated: July 5th, 2023 16:04

2007 chapter

Combining cluster sampling with single pass methods for efficient sampling regimen design

In 2007 IEEE International Conference On Computer Design (pp. 472–479). New York: IEEE.

By: P. Bryan & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

2005 article

Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction

Zhou, H., & Conte, T. M. (2005, May 24). IEEE Transactions on Computers, Vol. 54, pp. 897–912.

By: H. Zhou*  & T. Conte*

topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Cloud Computing and Resource Management
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2005 journal article

Enhancing memory-level parallelism via recovery-free value prediction

IEEE Transactions on Computers, 54(7), 897–912.

By: H. Zhou & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

2005 article

High-performance and low-cost dual-thread VLIW processor using Weld architecture paradigm

Ozer, E., & Conte, T. M. (2005, November 1). IEEE Transactions on Parallel and Distributed Systems.

By: E. Ozer* & T. Conte n

author keywords: multithreaded processors; VLIW architectures; modeling of computer architecture
topics (OpenAlex): Parallel Computing and Optimization Techniques; Embedded Systems Design Techniques; Interconnection Networks and Systems
TL;DR: This paper analyzes the performance impact of the dual-thread VLIW processor, which includes analysis of migrating disambiguation hardware for speculative load operations to the compiler and of the sensitivity of the model to the variation of branch misprediction, second-level cache miss penalties, and register file copy time. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2005 journal article

Optimal chip-package codesign for high-performance DSP

IEEE Transactions on Advanced Packaging, 28(2), 288–297.

By: P. Mehrotra n, V. Rao n, T. Conte n & P. Franzon n 

author keywords: chip-package codesign; fast Fourier transform (FFT); seamless high off-chip connectivity (SHOCC)
topics (OpenAlex): Advancements in Photolithography Techniques; Digital Filter Design and Implementation; VLSI and FPGA Design Techniques
TL;DR: This paper presents the design of a fast Fourier transform (FFT) engine that gives SRAM-like performance in a DRAM-based system and uses almost 100% of the available burst-mode memory bandwidth. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, Crossref
Added: August 6, 2018

2004 journal article

Opportunities and challenges in embedded systems

IEEE Micro, 24(4), 38208.

By: A. Bechini, T. Conte & C. Prete

Source: NC State University Libraries
Added: August 6, 2018

2003 article

Adaptive mode control

Zhou, H., Toburen, M. C., Rotenberg, E., & Conte, T. M. (2003, August 1). ACM Transactions on Embedded Computing Systems, Vol. 2, pp. 347–372.

By: H. Zhou n , M. Toburen n, E. Rotenberg n  & T. Conte n

topics (OpenAlex): Low-power high-performance VLSI design; Semiconductor materials and devices; Ferroelectric and Negative Capacitance Devices
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7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2003 article

Modeling value speculation: an optimal edge selection problem

Fu, N. C.-ying, Bodine, J. T., & Conte, T. M. (2003, March 1). IEEE Transactions on Computers.

By: N. Fu, J. Bodine n & T. Conte n

author keywords: value prediction; value speculation; optimal edge selection; data dependence graph; critical path reduction
topics (OpenAlex): Parallel Computing and Optimization Techniques; Distributed systems and fault tolerance; Advanced Data Storage Technologies
TL;DR: From the experimental results of running the optimal edge selection algorithm for the 20 most heavily executed paths selected from each SPECint95 benchmark, several insights are shown. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2003 chapter

Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors

In Languages and Compilers for Parallel Computing (Vol. 2624, pp. 223–238).

By: H. Zhou n , M. Jennings  n & T. Conte n

Ed(s): H. G. Dietz (Ed.),

topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Distributed and Parallel Computing Systems
TL;DR: This paper presents a new global scheduling algorithm using treegions called Tree Traversal Scheduling (TTS), and considers them analogous to superblocks with the same amount of code expansion as the base treegion. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, Crossref
Added: August 6, 2018

2002 article

Adaptive mode control: a static-power-efficient cache design

Zhou, N. H., Toburen, M. C., Rotenberg, E., & Conte, T. M. (2002, November 13). 2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, pp. 61–70.

By: N. Zhou n , M. Toburen n, E. Rotenberg n  & T. Conte n

topics (OpenAlex): Low-power high-performance VLSI design; Parallel Computing and Optimization Techniques; Semiconductor materials and devices
TL;DR: Simulations show an average of 73% of I-cache lines and 54% of D-cache lines are put in sleep mode with an average IPC impact of only 1.7%, for 64KB caches, and this work proposes applying sleep mode only to the data store and not the tag store. (via Semantic Scholar)
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7. Affordable and Clean Energy (OpenAlex)
Sources: NC State University Libraries, NC State University Libraries
Added: August 6, 2018

2002 article

Choosing the brain(s) of an embedded system

Conte, T. M. (2002, July 1). Computer.

By: T. Conte n

topics (OpenAlex): Embedded Systems Design Techniques
TL;DR: Embedded processors are fundamentally different from desktop processors -costs are too tight for fancy chip sets and expensive packaging. (via Semantic Scholar)
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Source: Web Of Science
Added: August 6, 2018

2000 article

Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility

Conte, T. M., & Sathaye, S. (2000, January 1). IEEE Transactions on Computers.

By: T. Conte n & S. Sathaye*

author keywords: microarchitecture; processor architecture; instruction cache; VLIW; instruction-set encoding; list encoding
topics (OpenAlex): Parallel Computing and Optimization Techniques; Embedded Systems Design Techniques; Real-Time Systems Scheduling
TL;DR: This paper shows that the changes in the page size are only due to insertion and/or deletion of NOPs in the code, and presents an ISA encoding, called list encoding, which does not require explicit encoding of the NOPa of the code. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

2000 article

System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design

Conte, T. M., Menezes, K. N., Sathaye, S. W., & Toburen, M. C. (2000, April 1). IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

By: T. Conte n, K. Menezes*, S. Sathaye* & M. Toburen n

author keywords: high-level synthesis; instruction-level parallelism; near-optimal search; power dissipation; superscalar
topics (OpenAlex): Parallel Computing and Optimization Techniques; Low-power high-performance VLSI design; Embedded Systems Design Techniques
TL;DR: This paper presents systematic techniques to find low-power high-performance superscalar processors tailored to specific user applications and the use of a near-optimal search to tailor a processor design to a benchmark. (via Semantic Scholar)
UN Sustainable Development Goals Color Wheel
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

1999 article

Challenges in processor modeling and validation [Guest Editors' introduction]

Bose, P., Conte, T. M., & Austin, T. M. (1999, May 1). IEEE Micro.

By: P. Bose *, T. Conte n & T. Austin*

topics (OpenAlex): Parallel Computing and Optimization Techniques
TL;DR: The methodology for designing state-of-the-art microprocessors involves modeling at various levels of abstraction, which can range from early-stage (microarchitectural) performance-only models to final-stage, detailed register-transfer-level (RTL) models. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1999 article

Editor's Introduction

Conte, T., Hwu, W.-M., & Smotherman, M. (1999, October 1). International Journal of Parallel Programming.

By: T. Conte*, W. Hwu & M. Smotherman

topics (OpenAlex):
TL;DR: This special issue on InstructionLevel Parallel Processing introduces this collection of new and exciting technical papers in this subject area and introduces the three papers that appear in the current issue. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1999 article

Editors' Introduction

Conte, T., Hwu, W.-M., & Smotherman, M. (1999, December 1). International Journal of Parallel Programming.

By: T. Conte*, W. Hwu & M. Smotherman

topics (OpenAlex):
TL;DR: This volume represents contributions to this important topic by leading researchers in the field of forecasting and includes the latest research on forecasting macroeconomic and financial variables in the presence of structural breaks and/or model uncertainty. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1998 article

Combining trace sampling with single pass methods for efficient cache simulation

Conte, T. M., Hirsch, M. A., & Hwu, W.-M. W. (1998, June 1). IEEE Transactions on Computers.

By: T. Conte n, M. Hirsch n & W. Hwu*

author keywords: performance analysis; sampling techniques; single pass algorithms; stacking algorithms; trace-driven simulation
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Distributed and Parallel Computing Systems
TL;DR: A single pass method used in combination with trace sampling techniques to produce a fast and accurate approach for simulating multiple sizes of caches simultaneously. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1998 article

MPS: miss-path scheduling for multiple-issue processors

Banerjia, S., Sathaye, S. W., Menezes, K. N., & Conte, T. M. (1998, January 1). IEEE Transactions on Computers.

By: S. Banerjia*, S. Sathaye*, K. Menezes* & T. Conte n

author keywords: multiple instruction issue; miss path scheduling; instruction level parallelism; schedule cache
topics (OpenAlex): Parallel Computing and Optimization Techniques; Embedded Systems Design Techniques; Real-Time Systems Scheduling
TL;DR: This paper presents the design of a multiple issue processor that uses an alternative approach called miss path scheduling or MPS, which is removed from the processor pipeline altogether and placed on the path between the instruction cache and the next level of memory. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1998 article

Performance analysis and its impact on design

Bose, P., & Conte, T. M. (1998, May 1). Computer.

By: P. Bose * & T. Conte*

topics (OpenAlex): Parallel Computing and Optimization Techniques; Embedded Systems Design Techniques; Interconnection Networks and Systems
TL;DR: This work focuses on architectural performance, typically measured in cycles per instruction, and covers some of the advances in dealing with modern problems in performance analysis. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1998 article

Subword extensions for video processing on mobile systems

Jennings, M. D., & Coate, T. M. (1998, July 1). IEEE Concurrency.

By: M. Jennings  n & T. Coate*

topics (OpenAlex): Video Coding and Compression Technologies; Advanced Data Compression Techniques; Multimedia Communication and Technology
TL;DR: Most general purpose microprocessor architectures have recently extended their instruction set architectures to include parallel instructions for improved performance on multimedia applications, including MPEG (Motion Pictures Expert Group) video, which includes micro SIMD execution using packed data types. (via Semantic Scholar)
UN Sustainable Development Goals Color Wheel
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy (OpenAlex)
Source: Web Of Science
Added: August 6, 2018

1998 conference paper

Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures

Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308–315. Los Alamitos, Calif.: IEEE Computer Society Press.

By: E. Ozer, S. Banerjia & T. Conte

Source: NC State University Libraries
Added: August 6, 2018

1998 article

Value speculation scheduling for high performance processors

Fu, C.-Y., Jennings, M. D., Larin, S. Y., & Conte, T. M. (1998, October 1). ACM SIGPLAN Notices.

By: C. Fu n, M. Jennings  n, S. Larin n & T. Conte n

author keywords: value speculation; value prediction; VLIW instruction scheduling; instruction level parallelism
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Embedded Systems Design Techniques
Source: Web Of Science
Added: August 6, 2018

1997 article

Compilers for instruction-level parallelism

Schlansker, M., Conte, T. M., Dehnert, J., Ebcioglu, K., Fang, J. Z., & Thompson, C. L. (1997, January 1). Computer.

By: M. Schlansker*, T. Conte n, J. Dehnert, K. Ebcioglu *, J. Fang * & C. Thompson*

topics (OpenAlex): Parallel Computing and Optimization Techniques; Embedded Systems Design Techniques; Software Testing and Debugging Techniques
TL;DR: Discovering and exploiting instruction level parallelism in code will be key to future increases in microprocessor performance, as research continues to find better ways to use more hardware parallelism over a broader class of applications. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

1997 article

Optimization of VLIW compatibility systems employing dynamic rescheduling

Conte, T. M., & Sathaye, S. W. (1997, April 1). International Journal of Parallel Programming.

By: T. Conte n & S. Sathaye n

author keywords: object-code compatibility; dynamic rescheduling; instruction level parallelism
topics (OpenAlex): Parallel Computing and Optimization Techniques; Advanced Data Storage Technologies; Embedded Systems Design Techniques
TL;DR: This paper presents a technique called Dynamic Rescheduling that applies software techniques dynamically, using intervention by the OS: at each first-time page fault, the page of code is rescheduled for the new generation, if required. (via Semantic Scholar)
Source: Web Of Science
Added: August 6, 2018

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