Thomas M. Conte

Bryan, P. D., & Conte, T. M. (2007). Combining cluster sampling with single pass methods for efficient sampling regimen design. In 2007 IEEE International Conference On Computer Design (pp. 472–479). New York: IEEE.

Huiyang, & Conte, T. M. (2005). Enhancing memory-level parallelism via recovery-free value prediction. IEEE Transactions on Computers, 54(7), 897–912. https://doi.org/10.1109/tc.2005.117

Ozer, E., & Conte, T. M. (2005). High-performance and low-cost dual-thread VLIW processor using weld architecture paradigm. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 16(12), 1132–1142. https://doi.org/10.1109/TPDS.2005.150

Mehrotra, P., Rao, V., Conte, T. M., & Franzon, P. D. (2005). Optimal chip-package codesign for high-performance DSP. IEEE TRANSACTIONS ON ADVANCED PACKAGING, 28(2), 288–297. https://doi.org/10.1109/TADVP.2005.846937

Bechini, A., Conte, T. M., & Prete, C. A. (2004). Opportunities and challenges in embedded systems. IEEE Micro, 24(4), 38208.

Huiyang, Toburen, M. C., Rotenberg, E., & Conte, T. M. (2003). Adaptive mode control: A static-power-efficient cache design. ACM Transactions on Embedded Computing Systems, 2(3), 347–372. https://doi.org/10.1145/860176.860181

Fu, C. Y., Bodine, J. T., & Conte, T. M. (2003). Modeling value speculation: An optimal edge selection problem. IEEE TRANSACTIONS ON COMPUTERS, 52(3), 277–292. https://doi.org/10.1109/TC.2003.1183944

Zhou, H., Jennings, M. D., & Conte, T. M. (2003). Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. In Languages and Compilers for Parallel Computing (Vol. 2624, pp. 223–238). https://doi.org/10.1007/3-540-35767-x_15

Conte, T. M. (2002, July). Choosing the brain(s) of an embedded system. COMPUTER, Vol. 35, pp. 106–107. https://doi.org/10.1109/MC.2002.1016908

Huiyang, Toburen, M. C., Rotenberg, E., & Conte, T. M. (2001). Adaptive mode control: A static-power-efficient cache design. 2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70. https://doi.org/10.1109/pact.2001.953288

Conte, T. M., & Sathaye, S. (2000). Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility. IEEE TRANSACTIONS ON COMPUTERS, 49(8), 814–825. https://doi.org/10.1109/12.868027

Conte, T. M., Menezes, K. N., Sathaye, S. W., & Toburen, M. C. (2000). System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 8(2), 129–137. https://doi.org/10.1109/92.831433

Conte, T., Hwu, W. M., & Smotherman, M. (1999, December). 30th Annual ACM/IEEE International Symposium on Microarchitecture, Part II - Editors' Introduction. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 425–426. https://doi.org/10.1023/A:1018739115760

Bose, P., Conte, T. M., & Austin, T. M. (1999). Challenges in processor modeling and validation. IEEE MICRO, Vol. 19, pp. 9–14. https://doi.org/10.1109/MM.1999.768495

Conte, T., Hwu, W. M., & Smotherman, M. (1999, October). Special issue: 30th Annual ACM/IEEE International Symposium on Microarchitecture, Part I. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 27, pp. 325–326. https://doi.org/10.1023/A:1018745822603

Conte, T. M., Hirsch, M. A., & Hwu, W. M. W. (1998). Combining trace sampling with single pass methods for efficient cache simulation. IEEE TRANSACTIONS ON COMPUTERS, 47(6), 714–720. https://doi.org/10.1109/12.689650

Banerjia, S., Sathaye, S. W., Menezes, K. N., & Conte, T. M. (1998). MPS: Miss-path scheduling for multiple-issue processors. IEEE TRANSACTIONS ON COMPUTERS, 47(12), 1382–1397. https://doi.org/10.1109/12.737684

Bose, P., & Conte, T. M. (1998). Performance analysis and its impact on design. COMPUTER, 31(5), 41–49. https://doi.org/10.1109/2.675632

Jennings, M. D., & Conte, T. M. (1998). Subword extensions for video processing on mobile systems. IEEE CONCURRENCY, 6(3), 13–16. https://doi.org/10.1109/4434.708250

Ozer, E., Banerjia, S., & Conte, T. M. (1998). Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures. Proceedings, 31st annual ACM/IEEE International Symposium on Microarchitecture: November 30-December 2, 1998, Dallas, Texas / co-sponsored by ACM SIGMICRO, IEEE Computer Society Technical Committee on Microprogramming and Microarchitecture., 308–315. Los Alamitos, Calif.: IEEE Computer Society Press.

Fu, C. Y., Jennings, M. D., Larin, S. Y., & Conte, T. M. (1998). Value speculation scheduling for high performance processors. ACM SIGPLAN NOTICES, 33(11), 262–271. https://doi.org/10.1145/291006.291058

Schlansker, M., Conte, T. M., Dehnert, J., Ebcioglu, K., Fang, J. Z., & Thompson, C. L. (1997). Compilers for instruction-level parallelism. COMPUTER, 30(12), 63-&. https://doi.org/10.1109/2.642817

Conte, T. M., & Sathaye, S. W. (1997, April). Optimization of VLIW compatibility systems employing dynamic rescheduling. INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, Vol. 25, pp. 83–112. https://doi.org/10.1007/BF02700048