@article{bonner-stewart_wilson_floyd_2020, title={Tunable 0.7-2.8-GHz Reflection-Mode N-Path Filters in 45-nm SOI CMOS}, volume={68}, ISSN={["1557-9670"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85086269923&partnerID=MN8TOARS}, DOI={10.1109/TMTT.2020.2971489}, abstractNote={This article presents the principles of operation of a reflection-mode $N$ -path filter and then discusses both single-balanced and double-balanced implementations. The single-balanced approach can be used to realize tunable filters with extremely low insertion loss; however, the circuit also exhibits harmonic responses. The double-balanced reflector naturally rejects even-order harmonics and can be modified to cancel the third harmonics as well to provide a tunable $N$ -path filter with the second through fourth harmonics rejected. This comes at the expense of increased insertion loss to support the required balun circuitry used to balance the mixers. Prototypes for both types of filters have been realized in the 45-nm SOI CMOS technology. Measurements on the single-balanced reflection-mode filter indicate 0.8–2.4-dB insertion loss across a 700–3000-MHz tuning range. The input-referred 1-dB compression point is 0 dBm and the input-referred third-order intercept point (IIP3) is +10-dBm in-band and +22-dBm out-of-band (OOB), and the circuit consumes 2.5–7.2 mW of power. Measurements on the double-balanced reflection-mode filter indicate 1.9–4.4-dB insertion loss across a 700–2800-MHz tuning range. The input-referred 1-dB compression point is +0.75 dBm, and IIP3 is >+16.3-dBm in-band and >+19.5-dBm OOB, and the circuit consumes a total of 4.0–15.6 mW of power.}, number={6}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Bonner-Stewart, Jeffrey and Wilson, Charley, III and Floyd, Brian A.}, year={2020}, month={Jun}, pages={2343–2357} }
 @article{wilson_floyd_2019, title={Harmonic Performance of Mixer-First Receivers With Circulant-Symmetric Basebands}, volume={66}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85051814188&partnerID=MN8TOARS}, DOI={10.1109/TCSI.2018.2856257}, abstractNote={In this paper, we analyze a mixer-first receiver, which includes passive polyphase mixers, low-noise baseband amplifiers, and baseband circulant-symmetric polyphase feedback. This analysis is performed for input frequencies located around any harmonic frequency of the local oscillator. From this, circuits and methods are introduced, which allow control of the receiver’s harmonic input impedance through the use of resistive–capacitive ( $RC$ ) baseband feedback networks. We show that the harmonic input admittance of the mixer-first receiver is related to the discrete Fourier transform of the baseband circulant. This Fourier relationship allows control of the harmonic impedance response across frequencies. The noise figure of the receiver with circulant-symmetric feedback can approach that of an equivalent mixer-first receiver having harmonic feedforward cancelation without the additional power consumption of a cancelation stage. Harmonic impedance shaping can improve the blocker tolerance by decreasing the harmonic conversion gain. A single design can be reconfigured to use these techniques for fundamental-frequency or subharmonic operation. Derivations for impedance, conversion gain, and noise figure are included and a linear time-invariant circuit model is introduced. These are validated through circuit simulation using a combination of 45-nm silicon-on-insulator CMOS technology and behavioral baseband models.}, number={1}, journal={IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS}, author={Wilson, Charley and Floyd, Brian}, year={2019}, pages={161–174} }
 @inproceedings{wilson_floyd_2016, title={20-30 GHz mixer-first receiver in 45-nm SOI CMOS}, volume={2016-July}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-84980371004&partnerID=MN8TOARS}, DOI={10.1109/rfic.2016.7508323}, abstractNote={A 20-30 GHz mixer-first receiver implemented in 45-nm SOI CMOS is presented. The receiver employs four-phase passive mixing with input inductor to realize tunable impedance matching up to 30 GHz. The receiver achieves an 8-dB noise figure with reconfigurable 8.9 to 20.6-dB conversion gain and 2:1 impedance tuning range. Input 1-dB compression point ranges from -13 to -9.3 dBm and power consumption is 41 mW.}, booktitle={2016 ieee radio frequency integrated circuits symposium (rfic)}, author={Wilson, C. and Floyd, Brian}, year={2016}, pages={344–347} }