@inproceedings{sinha_cheng_parmar_hopkins_2023, title={Advanced GaN IPM for High-Frequency Converter Applications Enabled with Thin-Substrates}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec43580.2023.10131488}, DOI={10.1109/apec43580.2023.10131488}, abstractNote={Extracting the potential of Wide Bandgap (WBG) semiconductor devices needs enhanced electrical and thermal packaging. This paper presents a half-bridge GaN-based Integrated Power Module (IPM) with inclusive gate drivers, driver caps, and decoupling caps for a 500kHz/0.8kW converter application. Presented are the design, fabrication, and experimental characterization of a dense, double-side cooled IPM utilizing an advanced epoxy-resin insulated metal substrate (eIMS) with 120µm thin dielectric for 400V/ 8.3ns high edge-rate switching (i.e. with $dv/dt$ of highest frequency of interest (HFI)). The common mode (CM) capacitance has been optimized. The thermal performance of the module was validated through ANSYS simulation, and the symmetry of the sandwiched substrate structure ensured for symmetric temperature distribution and stress management. An experimental Double Pulse Test (DPT) board with low isolation capacitance was developed to characterize the maximum dynamic performance. Finally, the CM effects on a full-bridge converter application are evaluated to show the efficacy of thin-substrate packaging for application at industrial power levels.}, booktitle={2023 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Sinha, Sourish S. and Cheng, Tzu-Hsuan and Parmar, Keval and Hopkins, Douglas C.}, year={2023}, month={Mar}, pages={2596–2603} }
 @inproceedings{narwal_rawat_kanale_cheng_agarwal_bhattacharya_baliga_hopkins_2023, title={Analysis and Characterization of Four-quadrant Switches based Commutation Cell}, volume={2023-March}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec43580.2023.10131312}, DOI={10.1109/apec43580.2023.10131312}, abstractNote={A four-quadrant switch (FQS) blocks either polarity voltage and controls current flow in both directions. Unlike voltage-source converters, in which two-quadrant switches operate over a narrow voltage range, four-quadrant switches are required to operate over a wide range of both voltage and current in applications such as matrix converters and current-source converters. Furthermore, matrix converters require multi-step commutation schemes compared to two-step schemes for current-bidirectional switch based voltage-source converters and voltage-bidirectional switch based current-source converters. This paper provides a generalized overview of commutation schemes used for two and four quadrant switches based two-level commutation cells, identifies comparison indices for FQS commutation schemes, and discusses the need for adaptive commutation-step times for wide voltage and current variation applications. Also, the static and dynamic characteristics of 1.2 kV rated FQS implementations utilizing commercial SiC MOSFETs from four different manufacturers and novel monolithic SiC BiDirectional Field Effect Transistor (BiDFET) have been reported.}, booktitle={2023 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Narwal, Ramandeep and Rawat, Shubham and Kanale, Ajit and Cheng, Tzu-Hsuan and Agarwal, Aditi and Bhattacharya, Subhashish and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2023}, month={Mar}, pages={209–216} }
 @article{narwal_bhattacharya_baliga_hopkins_2023, title={Bidirectional Three-phase Current Source Converter based Buck-boost AC/DC System using Bidirectional Switches}, ISSN={["2473-7631"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85168253560&partnerID=MN8TOARS}, DOI={10.1109/ITEC55900.2023.10186945}, abstractNote={The 1.2 kV 4H-SiC BiDirectional Field Effect Transistor (BiDFET) is the first monolithic SiC bidirectional switch, which offers a lower voltage drop and semiconductor devices count alternative to the reverse-voltage-blocking (RB) switch used in the current-source converters (CSC). The bidirectional switch based CSC also allows DC-link current reversal for bidirectional power flow and provides multiple system-level benefits in a buck-boost AC/DC system consisting of buck-type DC/DC converter and CSC. This paper discusses the selection of buck converter duty cycle and CSC modulation index for the system's buck-boost operation with a wide variation in DC voltage. CSC modulation schemes categorized based on the number of hard-turn-on transitions per switching cycle are also analyzed along with the three-step and four-step commutation schemes that are essential for the CSC commutation cells. Finally, the different schemes are evaluated and compared through the experimental results of a 10 kW, 480 $\mathbf{V}_{\mathbf{RMS},\mathbf{LL}}/$ (400 - 800) V AC/DC system.}, journal={2023 IEEE TRANSPORTATION ELECTRIFICATION CONFERENCE & EXPO, ITEC}, author={Narwal, Ramandeep and Bhattacharya, Subhashish and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2023} }
 @inproceedings{hopkins_sinha_2023, title={Design & Integration of Solid-State Circuit Protection}, booktitle={IEEE Applied Power Electronics Conference}, author={Hopkins, Douglas C. and Sinha, Sourish S.}, year={2023}, month={Mar} }
 @inproceedings{finite element analysis and fatigue life prediction of a laterally conducting gan-based power package under thermal cyclingasme 2023 int’l mechanical eng. congress and exposition_2023, url={https://event.asme.org/IMECE}, booktitle={ASME 2023 Int’l Mechanical Eng. Congress and Exposition}, year={2023}, month={Oct} }
 @article{mehrotra_hopkins_2023, title={Methodologies of Cascading to Realize High Voltage Cascaded Super Cascode Power Switch}, volume={11}, ISSN={["2168-6785"]}, url={https://doi.org/10.1109/JESTPE.2023.3314025}, DOI={10.1109/JESTPE.2023.3314025}, abstractNote={Development of high-voltage (HV) high-current (HC) power semiconductor devices is limited due to relatively low yield, expensive material and fabrication costs, and retracted dynamic performance from paralleling many HV, low-current (LC) devices. An alternative is a serial connection of low-voltage (LV) HC devices to create a supercascode power switch (SCPS). This article describes a methodology of cascading SCPSs to realize an even higher voltage cascaded supercascode power switch (CSCPS), which optimizes switching through multilayered cascades of normally-on devices, e.g., JFETs or depletion-mode GaN HEMTs. The method provides a topology optimization of cascaded cells dependent on switching losses, net charge reduction in network capacitors, and avalanche energy management. Simulation and test results are provided for a single-layer “2S-3C” 6-kV CSCPS. The 6-kV JFET CSCPS showed 408- $\text{m}\Omega $ ON-resistance, leakage current of 0.7 mA at 4.8 kV, and 40-ns rise with 30-ns fall in current at 4 kV/20 A.}, number={6}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2023}, pages={5853–5862} }
 @article{bhattacharya_narwal_shah_baliga_agarwal_kanale_han_hopkins_cheng_2023, title={Power Conversion Systems Enabled by SiC BiDFET Device}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237060}, DOI={10.1109/MPEL.2023.3237060}, abstractNote={The BiDirectional Field-Effect Transistor (BiDFET) can enable circuit topologies requiring four-quadrant switches, that were earlier designed using discrete combinations of MOSFETs, IGBTs, GaN HEMTs, and PiN diodes. The monolithic nature of the BiDFET allows lower device count, smaller switch volume, lower inductance, and simpler packaging, and hence more reliable and commercially viable implementation in power electronics converters. The matrix converter topologies, now feasible using BiDFETs, can eliminate the bulky and unreliable dc link capacitors or inductors required for conventional voltage-source or current-source converters in ac–ac and ac–dc applications. The 1.2 kV BiDFET has the potential to disrupt all the applications utilizing 1.2 kV switches, including electric vehicle (EV) drivetrain, bidirectional EV chargers, industrial motor drives, solid-state transformers, datacenter power supplies, elevator drives, dc microgrids, energy storage grid integration, solid-state breakers, etc.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Bhattacharya, Subhashish and Narwal, Ramandeep and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Agarwal, Aditi and Kanale, Ajit and Han, Kijeong and Hopkins, Douglas C. and Cheng, Tzu-Hsuan}, year={2023}, month={Mar}, pages={39–43} }
 @article{baliga_hopkins_bhattacharya_agarwal_cheng_narwal_kanale_shah_han_2023, title={The BiDFET Device and Its Impact on Converters}, volume={10}, ISSN={["2329-9215"]}, url={https://doi.org/10.1109/MPEL.2023.3237059}, DOI={10.1109/MPEL.2023.3237059}, abstractNote={The matrix converter topology for direct ac-to-ac conversion offers elimination of the bulky and unreliable d.c. link capacitors used in the popular voltage-source inverter (VSI) with a front-end rectifier. The resulting more compact and higher efficiency implementation is a desirable solution for a wide variety of applications, such as photovoltaic energy generation, motor drives, and energy storage systems.}, number={1}, journal={IEEE POWER ELECTRONICS MAGAZINE}, author={Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish and Agarwal, Aditi and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Kanale, Ajit and Shah, Suyash Sushilkumar and Han, Kijeong}, year={2023}, month={Mar}, pages={20–27} }
 @inproceedings{zaghari_sinha_ryu_franzon_hopkins_2023, title={Thermal Cycling and Fatigue Life Analysis of a Laterally Conducting GaN-based Power Package}, ISSN={["2164-0157"]}, url={http://dx.doi.org/10.1109/3dic57175.2023.10154901}, DOI={10.1109/3dic57175.2023.10154901}, abstractNote={Thermal reliability is a critical factor in ensuring the performance and efficiency of GaN-based electronic devices. In this paper, the fatigue life assessment of a laterally conducting GaN power package that uses a two-solder hierarchy of SAC305 and Sn63/Pb37 on a 120μm thick dielectric for device attach was conducted using an FEA. The double-sided package structure also introduced thick Cu as integrated baseplate layers for mechanical mounting into higher packaging levels while providing surfaces for double-sided cooling. The internal structure varied spacer thicknesses for planarization and inclusion of package-integrated decoupling capacitors. The solder materials were simulated by using the Anand viscoplastic constitutive model. Coffin-Manson, Engelmaier, and Solomon empirical strain-based models were utilized to predict the cyclic life of the package. Based on the results, the critical solder joint location was predicted in the Sn63/Pb37 solder layer between the GaN and Cu spacer, with a strain range of 0.02797. The worst-case life prediction for the module was 150 cycles using the Coffin-Manson model.}, booktitle={2023 IEEE International 3D Systems Integration Conference (3DIC)}, publisher={IEEE}, author={Zaghari, Pouria and Sinha, Sourish S. and Ryu, Jong Eun and Franzon, Paul D. and Hopkins, Douglas C.}, year={2023}, month={May} }
 @misc{kanale_cheng_narwal_agarwal_baliga_bhattacharya_hopkins_2022, title={Design Considerations for Developing 1.2 kV 4H-SiC BiDFET-enabled Power Conversion Systems}, ISSN={["2329-3721"]}, url={http://dx.doi.org/10.1109/ECCE50734.2022.9947715}, DOI={10.1109/ECCE50734.2022.9947715}, abstractNote={Bidirectional switches are essential for cycloconverter and matrix converter applications to facilitate single-stage AC-AC conversion without intermediate energy storage elements. The 1.2 kV 4H-SiC BiDFET was developed as the first monolithic bidirectional SiC power transistor. This paper describes the design considerations taken into account while creating the BiDFET device and developing custom packages for housing the switch in discrete form for low power applications and in module form for high-power applications. The realized switches are characterized for their on-state and switching performance. The versatility of the BiDFET device is demonstrated by operating a single BiDFET H-bridge in voltage-source-inverter and current-source-inverter topologies only by varying the gate bias on the individual BiDFETs and reversing the input-output connections.}, journal={2022 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Narwal, Ramandeep and Agarwal, Aditi and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2022}, month={Oct} }
 @article{sinha_cheng_hopkins_2022, title={Double Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification}, volume={2022}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/001c.74584}, DOI={10.4071/001c.74584}, abstractNote={Wide Bandgap devices (WBG) have led to an era of high speed and high voltage operations that were not previously achievable with silicon devices. However, packaging of these devices in the power module has been a challenge due to higher switching rates which can cause several amperes of displacement current to flow through the parasitic capacitance of the package thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates unlike the traditional inorganic substrates e.g. DBC and thus a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this paper is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and RMS value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.}, number={1}, journal={IMAPSource Proceedings}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Sinha, Sourish S. and Cheng, Tzu-Hsuan and Hopkins, Dr. Douglas C.}, year={2022}, month={May} }
 @inproceedings{hopkins_2022, title={Heterogeneous Integration of Power Electronics (IPE) and the Road Ahead}, booktitle={33rd Annual Electronics Packaging Symposium}, author={Hopkins, Douglas C.}, year={2022}, month={Sep} }
 @article{ke_mehrotra_hopkins_2021, title={3-D Prismatic Packaging Methodologies for Wide Band Gap Power Electronics Modules}, volume={36}, ISSN={["1941-0107"]}, DOI={10.1109/TPEL.2021.3081679}, abstractNote={In a power module the parasitic inductance limits the dynamic high-frequency performance, and the area of the cooling surfaces limits the power capability. This article presents a new 3-D power electronic design methodology based on the concept of mutual inductance cancellation and multisided heat transfer. New 3-D prismatic packaging concepts are proposed for wide band gap power devices, where the devices can be mounted at acute angles to adjacent interconnects or other devices. Discussion is given on electrical and thermal path optimization in a 3-D space. To validate the 3-D prismatic packaging methodology, a 1200 V/50 A SiC half-bridge power module is fabricated and tested for electrical and thermal performance and results are compared with simulations. The power density calculated for the module is 12 kW/in3 (including heatsink) and shows a 31.3% inductance reduction compared to a 2-D planar module. Finally, design guidance suggested for utilizing prismatic structures is provided, together with suggested future work in the area. This article presents the first reported true 3-D power module.}, number={11}, journal={IEEE TRANSACTIONS ON POWER ELECTRONICS}, author={Ke, Haotao and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, month={Nov}, pages={13057–13066} }
 @inproceedings{hopkins_yu_mehrotra_cheng_sinha_maru_mescia_2021, title={A 40kV/mm Organic Substrate for Low Voltage Power SiP and >10kV Power Modules}, author={Hopkins, Douglas C. and Yu, Wensong and Mehrotra, Utkarsh and Cheng, Tzu-Hsuan and Sinha, Sourish Sankar and Maru, Karan and Mescia, Nicholas}, year={2021}, month={Mar} }
 @inproceedings{mehrotra_hopkins_2021, title={A New Cascaded SuperCascode High Voltage Power Switch}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487049}, DOI={10.1109/apec42165.2021.9487049}, abstractNote={Medium Voltage (MV), High Current (HC) switches are growing in demand for MV applications in land, sea and air transport, fast charging, renewable energy, and a host of applications in pulsed power, e.g. solid-state protection. However, widespread adoption of commercially available MV-HC modules is limited due to retracted dynamic performance from paralleling many high voltage, low current semiconductors. The associated cost is relatively high because of low yield, and expensive material and fabrication. An alternative is series connection of Low Voltage (LV)-HC semiconductors to form a SuperCascode (SC) power switch. This paper introduces a Cascaded SuperCascode (CSC) power switch topology that scales to very high voltages (>100 kV) or applied to optimize previously reported MV SCs to achieve higher switching speed, reduced balancing network size and lower switching losses. This paper describes the design of the balancing network for optimized CSC switch switching speed, and provides simulation and test results of a 6.5 kV power switch. The switch simulated to show a 4.5x improvement in switching speed (avg of Ton and Toff), 40% reduction in switching losses, 60% net charge reduction in network capacitors (i.e. size reduction) and superior avalanche energy management for greater short circuit performance compared to other SCs. The switch was fabricated and tested showing 408 mΩ, 0.7 mA @ 4.8 kV and 23ns rise and 50ns fall in current at 4kV for 50A switching from double-pulse testing (DPT).}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, month={Jun}, pages={2251–2257} }
 @inproceedings{maru_hopkins_2021, title={Accessible & Adaptable Approach for Calculating the Thermal Resistance of a Power Package using ParaPower}, author={Maru, Karan and Hopkins, Douglas C.}, year={2021}, month={Mar} }
 @inproceedings{hopkins_cheng_mehrotra_yu_2021, title={Advanced Dual-Sided Half-bridge Packaging with Epoxy Insulated Metal Substrates (eIMS)}, author={Hopkins, Douglas C. and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Yu, Wensong}, year={2021}, month={Jun} }
 @inproceedings{hopkins_cheng_mehrotra_2021, title={Advances in Highly Thermally Conductive Organic Power Packaging}, author={Hopkins, Douglas C. and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh}, year={2021}, month={Apr} }
 @article{mehrotra_hopkins_2021, title={Analytical Method to Optimize the Cascaded SuperCascode Power Switch Balancing Network}, DOI={10.1109/WiPDA49284.2021.9645114}, abstractNote={SuperCascode Power Switches (SCPS) use series-connected Low Voltage (LV)- High Current (HC) devices in a serial string to realize High Voltage (HV) – HC power switches. Cascading of SuperCascodes (CSC) is a modification of the earlier proposed SCPS concept aimed to scale the switching topology to very high (>100kV) levels or applied to optimize previously reported HV SCPSs to achieve higher switching speed, reduced balancing network size and lower switching losses. However, certain practical challenges create engineering constraints in design which will be discussed and highlighted in this paper. Firstly, for a serial string of devices, scaling the devices adds stray inductances which lead to delays in triggering serial devices, de-synchronization of triggering and unexpected overvoltages that limit scalability. This paper provides an analytical model to enable optimization through simulation and provides experimental data verifying the model.}, journal={2021 IEEE 8TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA)}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, pages={107–111} }
 @article{mehrotra_ballard_hopkins_2021, title={Bidirectional Solid-State Circuit Breaker using Super Cascode for MV SST and Energy Storage Systems}, volume={10}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/JESTPE.2021.3081684}, DOI={10.1109/JESTPE.2021.3081684}, abstractNote={Solid-state transformers (SSTs) are developing as highly efficient interfaces in renewable energy, transport, and energy storage systems (ESSs). However, performance limitations, such as overvoltage sensitivity and fault handling capabilities, have slowed widespread adoption. Although SSTs are developing added capabilities for fault management, the required response speed and overdesign introduces added costs, particularly in protection of ultralow inductance systems, such as those sourced by ESSs. With increased use of power electronics, the power distribution systems are speeding up having shorter fault propagation delays and higher fault currents. This creates a need for alternative approaches to MV system protection. This article describes a bidirectional solid-state circuit breaker (BSSCB) based on a new SiC SuperCascode power switch, and a multilayered transient absorption network. This article studies transient heat transfer in the switch and provides a redefinition of the fuse curve as applied to the BSSCB suitable for digital control. This article identifies critical fault issues, discusses the impact on critical design points of the SuperCascode for a BSSCB, and provides design calculations for a complete 10-kV/300-A/3 X breaker, including the SuperCascode module. A scaled 6-kV/10-A/7 X SuperCascode is fabricated and tested to demonstrate switch response of <60 ns with fault isolation in 200 ns.}, number={4}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Mehrotra, Utkarsh and Ballard, Bahji and Hopkins, Douglas C.}, year={2021}, pages={1–1} }
 @inproceedings{kanale_narasimhan_cheng_agarwal_shah_baliga_bhattacharya_hopkins_2021, title={Comparison of the Capacitances and Switching Losses of 1.2 kV Common-Source and Common- Drain Bidirectional Switch Topologies}, ISBN={9781665401821}, url={http://dx.doi.org/10.1109/WiPDA49284.2021.9645130}, DOI={10.1109/WiPDA49284.2021.9645130}, abstractNote={Bidirectional, or four-quadrant switches (FQS) can be designed as back-to-back MOSFETs connected in common-drain (CD) or common-source (CS) topologies. CDFQS and CS-FQS assembled from discrete 1.2 kV commercially available SiC power MOSFETs were characterized to obtain capacitance and switching loss values. The CD-FQS exhibited a 1. 17x larger turn-on loss compared to the CS-FQS, while the CS-FQS exhibited a 1. 52x larger turn-off loss compared to the CD-FQS. The CS-FQS exhibited a lower input capacitance, while the CD-FQS exhibited a lower output and reverse transfer capacitance.}, booktitle={2021 IEEE 8th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Kanale, Ajit and Narasimhan, Sneha and Cheng, Tzu-Hsuan and Agarwal, Aditi and Shah, Suyash Sushilkumar and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2021}, pages={112–117} }
 @inproceedings{mehrotra_morgan_hopkins_2021, title={Design and Characterization of 3.3 kV-15 kV rated DBC Power Modules for Developmental Testing of WBG devices}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487311}, DOI={10.1109/apec42165.2021.9487311}, abstractNote={An increasing number of power circuit designers are moving into designs at the bare die module-level to achieve greater circuit integration for lower inductance and better thermal management. Similarly, those who will use off-the-self modules are looking deeper inside the power modules to understand, discern, and optimize differences that impact gate driver design, power-loop designs and electro-physical layout between bare die. The ability for designers to have a greater understanding of the die-level module further advances adoption of WBG devices. This paper provides a description of open-source designs, fabrication, and test results for two DBC-based power modules. One is a SOT-227 footprint -based 6.5 kV DBC module, while the other is a 15 kV DBC module. The modules are specifically designed for mounting and testing new WBG power semiconductors under development, and as such, are designed for extreme operations under test. The characterization of the two modules and detailed insight into the ‘why’ in the design decisions provides the working engineer a clear understanding of variances in power module parameters and resulting effects on the module performance. The module designs are scalable, house single and multiple diodes and/or MOSFETs, include built-in current-sense and temperature monitoring, have Kelvin drain-source connections to reduce blanking-time, and utilize techniques to reduce stray inductance and resistance. The full designs are available for anyone’s use at www.go.ncsu.edu/prees_open_source}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Morgan, Adam J. and Hopkins, Douglas C.}, year={2021}, month={Jun}, pages={2351–2356} }
 @inproceedings{sinha_hopkins_2021, title={E-Field Reduction Techniques in HV Multi-layered Modules Using New Capacitive Modelling Method}, author={Sinha, Sourish S. and Hopkins, Douglas C.}, year={2021}, month={Mar} }
 @article{mehrotra_morgan_hopkins_2021, title={Optimization of Al Heavy Wire Bonds Bond profile in WBG Power Module Design}, volume={2021}, ISSN={1085-8024}, url={http://dx.doi.org/10.4071/1085-8024-2021.1.000260}, DOI={10.4071/1085-8024-2021.1.000260}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Mehrotra, Utkarsh and Morgan, Adam J. and Hopkins, Douglas C.}, year={2021}, month={Oct}, pages={000260–000264} }
 @inproceedings{shah_bhattacharya_kanale_cheng_mehrotra_agarwal_baliga_hopkins_2021, title={Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for PV Applications}, author={Shah, Suyash Sushilkumar and Bhattacharya, Subhashish and Kanale, Ajit and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Agarwal, Aditi and Baliga, B.Jayant and Hopkins, Douglas C.}, year={2021}, month={Oct} }
 @article{shah_narwal_bhattacharya_kanale_cheng_mehrotra_agarwal_baliga_hopkins_2021, title={Optimized AC/DC Dual Active Bridge Converter using Monolithic SiC Bidirectional FET (BiDFET) for Solar PV Applications}, ISSN={["2329-3721"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-85123361428&partnerID=MN8TOARS}, DOI={10.1109/ECCE47101.2021.9595533}, abstractNote={Grid interface power conversion systems for commercial, industrial and residential solar power generation are becoming ubiquitous due to the competitive cost of solar energy. The AC/DC dual active bridge (DAB) converter is an upcoming topology in industrial PV energy and energy storage applications, providing bidirectional power transfer and galvanic isolation. In this paper, the properties of a DAB-type converter are leveraged to propose a design optimization process. It can optimize the high-frequency RMS current, size of magnetic elements and zero-voltage-switching (ZVS) region of the converter. The resulting design is compared against that derived from a conventional approach. In addition, an algorithm to compute the harmonic currents at the DC and line frequency AC ports of the system is proposed, and the respective filter designs are presented. The optimized design of the AC/DC DAB converter is implemented using the newly developed, 1200 V, $46 \mathrm{m}\Omega$, four quadrant, SiC-based monolithic bidirectional FETs (BiDFET). Experimental results from the 2.3 kW, $400\mathrm{V}/277\mathrm{V}_{{\mathrm {RMS}}}$ hardware prototype are finally presented to verify the design process.}, journal={2021 IEEE ENERGY CONVERSION CONGRESS AND EXPOSITION (ECCE)}, author={Shah, Suyash Sushilkumar and Narwal, Ramandeep and Bhattacharya, Subhashish and Kanale, Ajit and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas C.}, year={2021}, pages={568–575} }
 @inproceedings{mehrotra_hopkins_2021, title={Scalable Cascaded SuperCascode High Voltage Power Switch}, author={Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2021}, month={Mar} }
 @inproceedings{mehrotra_morgan_mckeown_hopkins_2021, title={Study of Al wire bonds to understand cross-talk and current carrying capacity in WBG Power Module Design}, author={Mehrotra, Utkarsh and Morgan, Adam J. and McKeown, Michael and Hopkins, Douglas C.}, year={2021}, month={Apr} }
 @inproceedings{kanale_cheng_shah_han_agarwal_baliga_hopkins_bhattacharya_2021, title={Switching Characteristics of a 1.2 kV, 50 mΩ SiC Monolithic Bidirectional Field Effect Transistor (BiDFET) with Integrated JBS Diodes}, ISBN={9781728189499}, ISSN={["1048-2334"]}, url={http://dx.doi.org/10.1109/apec42165.2021.9487410}, DOI={10.1109/apec42165.2021.9487410}, abstractNote={The switching performance of large area (1cm x 1cm) monolithic 1.2 kV 50 mΩ 4H-SiC bidirectional field effect transistor (BiDFET) with integrated JBS diodes is reported for the first time. The devices were fabricated in a 6-inch commercial foundry and then packaged in a custom-designed four-terminal module. The switching performance of the BiDFET has been observed to be 1.4x better than that of its internal JBSFETs. Dynamic characterization was performed at 800 V with different gate resistances, current levels and case temperatures. An increase in switching losses was observed for the BiDFET with increasing gate resistance and current level as observed for SiC power MOSFETs. The BiDFET showed a 9% reduction in total switching loss from 25 °C to 150 °C with a current of 10 A.}, booktitle={2021 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Shah, Suyash Sushilkumar and Han, Kijeong and Agarwal, Aditi and Baliga, B. Jayant and Hopkins, Douglas and Bhattacharya, Subhashish}, year={2021}, month={Jun}, pages={1267–1274} }
 @inproceedings{cheng_hopkins_2021, title={Thermal Performance Comparison of DBC and ERCD for Single- and Double-Sided Power Modules}, author={Cheng, Tzu-Hsuan and Hopkins, Douglas C}, year={2021}, month={Apr} }
 @article{cheng_nishiguchi_fukawa_baliga_bhattacharya_hopkins_2021, title={Thermal and Reliability Characterization of an Epoxy Resin-Based Double-Side Cooled Power Module}, volume={18}, ISSN={1551-4897}, url={http://dx.doi.org/10.4071/imaps.1427774}, DOI={10.4071/imaps.1427774}, abstractNote={Abstract}, number={3}, journal={Journal of Microelectronics and Electronic Packaging}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Cheng, Tzu-Hsuan and Nishiguchi, Kenji and Fukawa, Yoshi and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2021}, month={Jul}, pages={123–136} }
 @article{kanale_cheng_han_baliga_bhattacharya_hopkins_2020, title={1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop}, volume={1004}, ISSN={1662-9752}, url={http://dx.doi.org/10.4028/www.scientific.net/msf.1004.872}, DOI={10.4028/www.scientific.net/msf.1004.872}, abstractNote={Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.}, journal={Materials Science Forum}, publisher={Trans Tech Publications, Ltd.}, author={Kanale, Ajit and Cheng, Tzu Hsuan and Han, Ki Jeong and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas}, year={2020}, month={Jul}, pages={872–881} }
 @article{cheng_nishiguchi_fukawa_baliga_bhattacharya_hopkins_2020, title={Characterization of Highly Thermally Conductive Organic Substrates for a Double-Sided Cooled Power Module}, volume={2020}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/2380-4505-2020.1.000277}, DOI={10.4071/2380-4505-2020.1.000277}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Cheng, Tzu-Hsuan and Nishiguchi, Kenji and Fukawa, Yoshi and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2020}, month={Sep}, pages={000277–000281} }
 @misc{hopkins_2020, title={Creating a Fast Turn Lab to Package Developmental Power Devices with a Packaging Example}, author={Hopkins, Douglas C.}, year={2020}, month={Aug} }
 @inproceedings{cheng_mehrotra_hopkins_2020, title={Development of 3.3 kV-Capable, Open-Source, Low Cost Packaging Solution for Sic Transistor and Diode Testing}, author={Cheng, Tzu-Hsuan and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2020}, month={Feb} }
 @inproceedings{murthy_mehrotra_yu_hopkins_2020, title={Dynamic and Thermal IOL Test Systems for 3.3kV-6.5kV Die Development}, author={Murthy, Pranav and Mehrotra, Utkarsh and Yu, Wensong and Hopkins, Douglas C.}, year={2020}, month={Feb} }
 @inproceedings{mehrotra_ballard_hopkins_2020, title={High Current Medium Voltage Bidirectional Solid State Circuit Breaker using SiC JFET Super Cascode}, ISBN={9781728158266}, url={http://dx.doi.org/10.1109/ecce44975.2020.9236347}, DOI={10.1109/ecce44975.2020.9236347}, abstractNote={DC power systems found in electric transport, data centers and residential microgrid applications maintain a demand for fast, reliable and efficient power electronics in the Medium Voltage (MV) range. DC systems are inherently more sensitive to faults due to low system impedance and voltage sensitivity of accompanying power electronics creating a need for a fast all Solid State approach to system protection. This paper proposes a Bidirectional Solid State Circuit Breaker (BSSCB) utilizing the SuperCascode topology as the breaking element and has parallel transient energy absorption circuitry comprising of MOVs and snubbers to denergize the line upon fault. The paper discusses critical design points in breaker design, advantages of SuperCascode switch for breaker applications and power stage scaling calculations of the transient absorption circuitry. For packaging, a novel Epoxy Resin Composite Dielectric (ERCD) is considered as an alternative to metal-clad ceramic (DBC) substrate for higher reliability. The paper studies transient heat transfer in the power module using finite element analysis (FEA) and proposes a thermally defined and digitally controlled fuse curve for breakers. A design example of 10kV/100 A BSSCB is provided which holds 10x rated current for a 5ms dwell. A scaled-down 6kV/10A SSCB prototype using TO-247 packaged dies is demonstrated and is capable of withstanding 7x over-current for 1μs and short circuit interruption in approximately 60 ns.}, booktitle={2020 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Ballard, Bahji and Hopkins, Douglas C.}, year={2020}, month={Oct} }
 @article{mehrotra_brazzle_mckeown_hopkins_2020, title={Lithium Battery Cell Level Fusing with Aluminum Heavy Wire Bonds}, volume={2020}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/2380-4505-2020.1.000009}, DOI={10.4071/2380-4505-2020.1.000009}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Mehrotra, Utkarsh and Brazzle, Arthur and McKeown, Michael and Hopkins, Douglas C.}, year={2020}, month={Sep}, pages={000009–000014} }
 @misc{han_agarwal_kanale_baliga_bhattacharya_cheng_hopkins_amarasinghe_ransom_2020, title={Monolithic 4-Terminal 1.2 kV/20 A 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Integrated JBS Diodes}, url={http://dx.doi.org/10.1109/ISPSD46842.2020.9170064}, DOI={10.1109/ISPSD46842.2020.9170064}, abstractNote={In this paper, we report successful fabrication of the first large area, monolithic, 1.2 kV 4H-SiC Bi-Directional FETs (BiDFETs) with integrated JBS diodes in a 6-inch commercial foundry for use in matrix converters. The fabricated BiDFETs support high voltage (>1.2 kV) in the first and third quadrants. They exhibit very low on-resistance of 50 mΩ in the on-state in both quadrants when the 20 V gate bias is applied to both gates, allowing conduction of 20 A with 1 V drop. Fully gate voltage controlled output characteristics are also confirmed in both quadrants.}, journal={2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)}, publisher={IEEE}, author={Han, Kijeong and Agarwal, Aditi and Kanale, Ajit and Baliga, B. Jayant and Bhattacharya, Subhashish and Cheng, Tzu-Hsuan and Hopkins, Douglas and Amarasinghe, Voshadhi and Ransom, John}, year={2020}, month={Sep} }
 @inproceedings{mehrotra_ballard_cheng_baliga_bhattacharya_hopkins_2020, title={Optimized Highly Efficient SSCB Using Organic Substrate Packaging for Electric Vehicle Applications}, ISBN={9781728146294}, url={http://dx.doi.org/10.1109/itec48692.2020.9161539}, DOI={10.1109/itec48692.2020.9161539}, abstractNote={Solid State Circuit Breakers (SSCBs) are an attractive protection solution for their arcless current interruption and fast actuation speeds over mechanical breakers. This paper proposes a Bidirectional SSCB (BSSCB) with a thermally defined and digitally controlled current time profile for fault protection in EV and other low-voltage DC systems. The paper proposes an organic packaging approach utilizing flex circuitry to develop a reliable, cost-effective power module for BSSCBs. The paper studies transient heat transfer in the power modules using finite element analysis (FEA). An RC themal ladder network is extracted to define a fusing curve. To demonstrate and verify the design, a 1kV/50 A SiC MOSFET BSSCB prototype is fabricated and tested, having a power density of 60 $W/cm^{3}$ and 4x reduction in form factor over presently researched breakers. Also, given are results for 750 V/150 A operation showing interruption in 2.4 $\mu$s.}, booktitle={2020 IEEE Transportation Electrification Conference & Expo (ITEC)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Ballard, Bahji and Cheng, Tzu-Hsuan and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2020}, month={Jun} }
 @inproceedings{mehrotra_cheng_kanale_agarwal_han_baliga_bhattacharya_hopkins_2020, title={Packaging Development for a 1200V SiC BiDFET Switch Using Highly Thermally Conductive Organic Epoxy Laminate}, ISBN={9781728148366}, url={http://dx.doi.org/10.1109/ispsd46842.2020.9170116}, DOI={10.1109/ispsd46842.2020.9170116}, abstractNote={A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 μm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates}, booktitle={2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD)}, publisher={IEEE}, author={Mehrotra, Utkarsh and Cheng, Tzu-Hsuan and Kanale, Ajit and Agarwal, Aditi and Han, Kijeong and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2020}, month={Sep} }
 @misc{sinha_hopkins_2020, title={ParaPower – Leveraging Finite Difference Simulator for Quick Thermal Design}, author={Sinha, Sourish Sankar and Hopkins, Douglas C.}, year={2020}, month={Jan} }
 @inproceedings{mehrotra_morgan_hopkins_2020, title={Traditional DBC-Based Power Modules for Test in Developing 3.3kV-15kV WBG Devices}, author={Mehrotra, Utkarsh and Morgan, Adam and Hopkins, Douglas C.}, year={2020}, month={Feb} }
 @inproceedings{hopkins_cheng_mehrotra_2020, title={Ultra-High Density Double-Sided Half Bridge Packaging}, author={Hopkins, Douglas C. and Cheng, Tzu-Hsuan and Mehrotra, Utkarsh}, year={2020}, month={Jul} }
 @inproceedings{kanale_cheng_hanl_baliga_bhattacharya_hopkins_2019, title={1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop}, author={Kanale, Ajit and Cheng, Tzu-Hsuan and Hanl, Kijeong and Baliga, B. Jayant and Bhattacharya, Subhashish and Hopkins, Douglas}, year={2019}, month={Sep} }
 @inproceedings{gao_mehrotra_hopkins_2019, title={A High-Bandwidth Resistive Current Sensing Technology for Breakers and Desaturation Protection}, ISBN={9781728137612}, url={http://dx.doi.org/10.1109/wipda46397.2019.8998767}, DOI={10.1109/wipda46397.2019.8998767}, abstractNote={High switching frequencies, steeper voltage and current slopes make for challenging requirements for real time current sensing, especially due to overshoot from sensing element inductance. High-bandwidth current sensing is required to ensure safe, reliable and efficient operations and to engage protection during critical failures. This paper describes and demonstrates a high bandwidth resistive current sensing technology for solid state circuit protection and diode-less power device desaturation protection. The sensor uses mutual inductance cancellation as well as residual inductive voltage subtraction for ultra-low-overshoot transient response. Full design steps and equations are presented for scaling the design. The demonstration design is fabricated using rigid and flexible PCB technologies. Test results show a 70.5% reduction of insertion inductance for the same power dissipation and sensitivity. VNA and spectrum analyzer measurements are used to characterize the prototypes of the proposed design. The paper also discusses two applications of desaturation protection and overcurrent protection for SiC FETs.}, booktitle={2019 IEEE 7th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Gao, Bo and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2019}, month={Oct} }
 @inproceedings{hopkins_cheng_gao_boteler_2019, title={Advances in Organic Substrate Approaches for High Voltage Power Electronics Packaging}, author={Hopkins, Douglas C. and Cheng, Tzu-Hsuan and Gao, Bo and Boteler, Lauren}, year={2019}, month={Oct} }
 @inproceedings{cheng_gao_boteler_hopkins_2019, title={Advances in Organic Substrate Approaches for High Voltage Power Electronics Packaging}, author={Cheng, Tzu-Hsuan and Gao, Bo and Boteler, Lauren and Hopkins, Douglas}, year={2019}, month={Nov} }
 @inproceedings{ballard_mehrotra_hopkins_2019, title={Bi–Directional Solid-State Circuit Breaker for MV Applications Based on SuperCascode Switching}, author={Ballard, Bahji and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2019}, month={Feb} }
 @inproceedings{cheng_gao_nishiguchi_hopkins_2019, title={Characterization of a Topside Cooled Epoxy-Resin Composite Dielectric (ERCD) Package for Bi-Directional Power Switch}, author={Cheng, Tzu-Hsuan and Gao, Bo and Nishiguchi, Kenji and Hopkins, Douglas}, year={2019}, month={Oct} }
 @inproceedings{hopkins_ballard_mehrotra_2019, title={Design and Integration of WBG Solid State Circuit Protection}, author={Hopkins, Douglas C. and Ballard, Bahji and Mehrotra, Utkarsh}, year={2019}, month={Mar} }
 @inproceedings{ballard_mehrotra_hopkins_2019, title={Designing for Switching Stresses in a Circuit Breaker Application using SiC Semiconductors}, author={Ballard, Bahji and Mehrotra, Utkarsh and Hopkins, Douglas C.}, year={2019}, month={Oct} }
 @inproceedings{guven_gao_hopkins_2019, title={Development of a High Frequency LLC Resonant Converter for Investigation of MLCCs for EV applications}, author={Guven, Musab and Gao, Bo and Hopkins, Douglas C.}, year={2019}, month={Aug} }
 @inproceedings{sinha_ballard_hopkins_2019, title={ERCD Power Stage Characterization for MV SSCB Application}, author={Sinha, Sourish S. and Ballard, Bahji and Hopkins, Douglas C.}, year={2019}, month={Aug} }
 @book{kulick_hopkins_2019, title={Edge Interconnect Packaging of Integrated Circuits for Power Systems}, number={10,325,875B2}, author={Kulick, Jason M. and Hopkins, Douglas}, year={2019}, month={Jun} }
 @inproceedings{morgan_gao_hopkins_2019, title={High Frequency Self-Oscillating WBG-based Power Conversion}, author={Morgan, Adam and Gao, Bo and Hopkins, Douglas C.}, year={2019}, month={Apr} }
 @inproceedings{morgan_kanale_han_baliga_hopkins_2019, title={New Dynamic Power MOSFET Model to Determine Maximum Device Operating Frequency}, ISBN={9781538683309}, url={http://dx.doi.org/10.1109/APEC.2019.8722197}, DOI={10.1109/APEC.2019.8722197}, abstractNote={Improved SiC-MOSFETs with high HF-FOMs are enabling unprecedented high frequency MHz-switching. However, other SiC-MOSFET parameters, such as input capacitance and total gate resistance dictate the "theoretical limit" on the maximum switching frequency, and are often not considered. These latter parameters directly influence the "real-time" dynamic on-resistance when the propagation-time of gate voltage approaches that of the switching time period. To properly characterize MHz-switching performance, minimum switching times are calculated using a modified "input RC time constant" analysis that incorporates a time-dependent active area. An empirical comparison is conducted for several SiC-MOSFETs. A novel, equivalent RC ladder and resistor switch network model is proposed to describe the propagation of gate voltage and dynamic activation of unit-cells composing the SiC-MOSFET channel. A time-dependent effective on-resistance, accounting for transition and steady state conduction on-times, is determined and verified in both simulation and experiment. New high-frequency performance metrics for SiC-MOSFETs are proposed to provide greater insight for design engineers, and provide maximum expected operating limits. This will also help guide semiconductor designers to better match device to application.}, booktitle={2019 IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Morgan, Adam J. and Kanale, Ajit and Han, Kijeong and Baliga, Jayant and Hopkins, Douglas C.}, year={2019}, month={Mar} }
 @inproceedings{morgan_kanale_han_baliga_hopkins_2019, title={New Dynamic Power MOSFET Model to Determine Maximum Device Operating Frequency}, author={Morgan, Adam and Kanale, Ajit and Han, Kijeong and Baliga, Jayant and Hopkins, Douglas C.}, year={2019}, month={Apr} }
 @inproceedings{hopkins_ballard_2019, title={Opportunities in Power Applications using Epoxy Resin Composite Dielectrics}, author={Hopkins, Douglas and Ballard, Bahji}, year={2019}, month={Aug} }
 @inproceedings{hopkins_2019, title={Power Packaging Assembly Challenges}, author={Hopkins, Douglas C.}, year={2019}, month={Mar} }
 @inproceedings{jorgensen_cheng_hopkins_beczkowski_uhrenfeldt_munk-nielsen_2019, title={Thermal Characteristics and Simulation of an Integrated GaN eHEMT Power Module}, ISBN={9789075815313}, url={http://dx.doi.org/10.23919/epe.2019.8915012}, DOI={10.23919/epe.2019.8915012}, abstractNote={Compact power modules are emerging which combine both direct bonded copper (DBC) and printed circuit boards (PCB) in integrated structures to achieve fast switching of wide bandgap semiconductors. The literature presenting the new integrated structures only include the DBC in their thermal analysis, and thus the influence of the PCB is often disregarded. In this paper the thermal characteristics of a new integrated GaN eHEMT power module are obtained experimentally. A simulation workflow to extract the thermal characteristics of the integrated module structure using finite element method software is presented and verified. The results predict an error of up to 13% in thermal impedance if the PCB board is not included in the simulation model.}, booktitle={2019 21st European Conference on Power Electronics and Applications (EPE '19 ECCE Europe)}, publisher={IEEE}, author={Jorgensen, Asger Bjorn and Cheng, Tzu-Hsuan and Hopkins, Douglas and Beczkowski, Szymon and Uhrenfeldt, Christian and Munk-Nielsen, Stig}, year={2019}, month={Sep} }
 @inproceedings{hopkins_2019, title={Trends in Power Electronics Packaging}, author={Hopkins, Douglas C.}, year={2019}, month={Apr} }
 @inproceedings{mehrotra_hopkins_2019, title={WBG Solid State Circuit Protection using 10kV/200 A Super Cascode power module}, author={Mehrotra, Utkarsh and Hopkins, Douglas}, year={2019}, month={Aug} }
 @inproceedings{gao_morgan_xu_zhao_hopkins_2018, title={6.0kV, 100A, 175kHz super cascode power module for medium voltage, high power applications}, url={https://www.lens.org/131-133-888-704-704}, DOI={10.1109/apec.2018.8341182}, abstractNote={A new 6.0kV/100A Super Cascode Power Module (SCPM) topology is proposed using dual serial strings of six SiC-JFETs with a common balancing circuit, and extendable to 8.0kV/200A for high-frequency, medium-voltage applications. Electrical and multi-physics simulations show improvements in dynamic response, and improved electro-thermal performance that exceed state-of-the-art Si-IGBT power module technology. The SCPM is fabricated and tested. Results are reported showing 47.8mΩ dynamic response, and ≤50ns rise and fall in current at 4kV for 110A switching from double-pulse testing (DPT).}, note={\urlhttps://ieeexplore.ieee.org/document/8341182}, booktitle={Thirty-third annual ieee applied power electronics conference and exposition (apec 2018)}, author={Gao, B. and Morgan, A. J. and Xu, Y. and Zhao, X. and Hopkins, Douglas C}, year={2018}, pages={1288–1293} }
 @inproceedings{gao_morgan_xu_zhao_ballard_hopkins_2018, title={6.5kV SiC JFET-based Super Cascode Power Module with High Avalanche Energy Handling Capability}, ISBN={9781538659090}, url={http://dx.doi.org/10.1109/wipda.2018.8569146}, DOI={10.1109/wipda.2018.8569146}, abstractNote={A new Super Cascode Power Module (SCPM) topology was designed, and a 6.5kV/100A implementation was fabricated and tested. Simulation and test results show 175kHz switching with 28ns switching time. Vulnerability to avalanche energy was observed, and a solution was proposed and verified with simulation. Simulation shows more than 99% of the avalanche energy is diverted to the power devices from balancing diodes, which have much smaller die size compared with the power device.}, booktitle={2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Gao, Bo and Morgan, Adam and Xu, Yang and Zhao, Xin and Ballard, Bahji and Hopkins, Douglas C.}, year={2018}, month={Oct} }
 @inproceedings{gao_morgan_xu_zhao_hopkins_2018, title={6.5kV, 100A, 175kHz Super Cascode Power Module (SCPM)}, author={Gao, Bo and Morgan, Adam and Xu, Yang and Zhao, Xin and Hopkins, Douglas C.}, year={2018}, month={Feb} }
 @inproceedings{chen_hopkins_2018, title={Comparing Power Packaging Through A Thermal Resistance Circle Based on Finite Element Analysis}, author={Chen, Timothy and Hopkins, Douglas C.}, year={2018}, month={Feb} }
 @article{de_morgan_mahadeva iyer_ke_zhao_vechalapu_bhattacharya_hopkins_2018, title={Design, Package, and Hardware Verification of a High-Voltage Current Switch}, volume={6}, ISSN={2168-6777 2168-6785}, url={http://dx.doi.org/10.1109/JESTPE.2017.2727051}, DOI={10.1109/jestpe.2017.2727051}, abstractNote={In this paper, an attempt has been made to demonstrate various package design considerations to accommodate series connection of high voltage Si-IGBT (6500V/25A die) and SiC-Diode (6500V/25A die). The effects of connecting the cathode of the series diode to the collector of the IGBT versus connecting the emitter of the IGBT to the anode of the series diode have been analyzed in regards to parasitic line inductance of the structure. Various simulation results have then been used to redesign and justify the optimized package structure for the final current switch design. The package is fabricated using the optimized parameters. A double pulse test-circuit has been assembled. Initial hardware results have been shown to verify functioning. The main motivation of this work is to enumerate detailed design considerations for packing a high voltage current switch package.}, note={\urlhttps://ieeexplore.ieee.org/document/7981339/}, number={1}, journal={IEEE Journal of Emerging and Selected Topics in Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={De, Ankan and Morgan, Adam J. and Mahadeva Iyer, Vishnu and Ke, Haotao and Zhao, Xin and Vechalapu, Kasunaidu and Bhattacharya, Subhashish and Hopkins, Douglas C.}, year={2018}, month={Mar}, pages={441–450} }
 @inproceedings{golding_hopkins_2018, title={Development of De-encapsulation Process for WBG Semiconductor Packaging Rework and Failure Analysis}, author={Golding, Caitlin and Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{hopkins_2018, title={Heterogeneous Integration Roadmap Update-integrated power electronics (IPE)}, author={Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{gao_zhao_hopkins_2018, title={Increasing Electrical and Thermal Performances of VRMs by Using Folded Flexible Substrate}, ISBN={9781538660171}, url={http://dx.doi.org/10.1109/3dpeim.2018.8525238}, DOI={10.1109/3dpeim.2018.8525238}, abstractNote={Electrical and thermal performance of rigid PCB based voltage regulator modules (VRMs) are modeled and simulated with FEA Multiphysics simulation tool. Then, a new concept of building power converters on folded flexible substrates is proposed to solve the issues existing in previous solutions. The newly proposed concept is then analyzed, simulated and compared with previous ones. A converter phase block implements the proposed concept was designed, built and tested. Test result shows at 2.5MHz, 12V to 1.2V 40A operation, the proposed converter can achieve 62.5A/cm2 planar power density and the measured module temperature is only 3.06°C above heat sink temperature.}, booktitle={2018 Second International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)}, publisher={IEEE}, author={Gao, Bo and Zhao, Xin and Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{han_kanale_baliga_ballard_morgan_hopkins_2018, title={New Short Circuit Failure Mechanism for 1.2kV 4H-SiC MOSFETs and JBSFETs}, ISBN={9781538659090}, url={http://dx.doi.org/10.1109/wipda.2018.8569178}, DOI={10.1109/wipda.2018.8569178}, abstractNote={The short circuit (SC-SOA) capability of power devices is crucial for power systems. In this paper, 1.2 kV SiC MOSFETs and JBSFETs are characterized, and their SC-SOA behavior was tested and analyzed. Due to the lower saturated drain current, the JBSFETs were found to have superior SC-SOA compared with MOSFETs despite the integrated Schottky contact. A new short circuit failure mechanism related to melting of the top Al metallization is proposed based up on non-isothermal TCAD numerical simulations supported with SEM measurements of failed die using Energy Dispersive X-ray Spectroscopy (EDS) analysis.}, booktitle={2018 IEEE 6th Workshop on Wide Bandgap Power Devices and Applications (WiPDA)}, publisher={IEEE}, author={Han, Kijeong and Kanale, Ajit and Baliga, B. J. and Ballard, Bahji and Morgan, Adam and Hopkins, Douglas C.}, year={2018}, month={Oct} }
 @inproceedings{guven_hopkins_2018, title={Parasitic Integration for 500kHz ZVS DC-DC Converter Using New Polymer Material in IMS Module}, author={Guven, Musab and Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{zhao_gao_zhang_hopkins_huang_2018, title={Performance optimization of A 1.2kV SiC high density half bridge power module in 3D package}, url={https://www.lens.org/153-777-952-057-428}, DOI={10.1109/apec.2018.8341179}, abstractNote={Wide bandgap power semiconductor devices show significantly superior performance than Si power devices, power module solutions are being investigated trying to improve system-level performance by applying SiC and GaN power devices in various applications. This paper introduces the design of a 1.2kV high density SiC half bridge intelligent power module based on 3-dimensional package concept, also addressed is the performance optimization of the proposed power module design. In the designed module, SiC MOSFETs and corresponding gate driver circuits in half bridge are interconnected vertically with high interconnection density and low power loop profile. Ultra-low parasitic inductance, 1.3nH, is introduced from DC+ to DC-. Isolation function blocks and bootstrap power supplies are also integrated in the 3D package. An ultra-thin dielectric substrate, with good thermal and breakdown performance, is applied to further decrease the power module weight and volume. The entire 3-dimentional 1.2kV SiC power module are within 35mm × 15mm × 7mm space. Through optimization, the design can achieve 8ns turn-on transient with limited switching loss at up to 700V / 60A. Thermal performance of the designed module is also evaluated through simulations.}, note={\urlhttp://xplorestaging.ieee.org/ielx7/8336027/8340970/08341179.pdf?arnumber=8341179 ; \urlhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=8341179}, booktitle={Thirty-third annual ieee applied power electronics conference and exposition (apec 2018)}, author={Zhao, X. and Gao, B. and Zhang, L. Q. and Hopkins, Douglas C and Huang, A. Q.}, year={2018}, pages={1266–1271} }
 @inproceedings{gao_morgan_hopkins_2018, title={Scalable MV/HV Super Cascode Power Module}, author={Gao, Bo and Morgan, Adam and Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{morgan_hopkins_2018, title={Self-Oscillating WBG-based VHF Power Conversion for FREEDM Applications}, author={Morgan, Adam and Hopkins, Douglas C.}, year={2018}, month={Jun} }
 @inproceedings{hopkins_2017, title={3D Printing Power Supply in Package Power Supply on Chip versus Discrete Packaging}, author={Hopkins, Douglas C.}, year={2017} }
 @inproceedings{hopkins_zhao_jagannadham_reainthippayasakul_lanagan_jiang_gao_nishiguchi_fukawa_2017, title={Characterization of Novel Materials for Thin Flexible Power Substrates for High-Density Power Electronics}, author={Hopkins, Douglas C. and Zhao, Xin and Jagannadham, K. and Reainthippayasakul, Wuttichai and Lanagan, Michael T. and Jiang, Yifan and Gao, Bo and Nishiguchi, Kenji and Fukawa, Yoshi}, year={2017}, month={Aug} }
 @article{morgan_zhao_rouse_hopkins_2017, title={Characterization of Silicone Gel for High Temperature Encapsulation in High Voltage WBG Power Modules}, volume={2017}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2017-wa54_099}, DOI={10.4071/isom-2017-wa54_099}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Morgan, Adam and Zhao, Xin and Rouse, Jason and Hopkins, Douglas}, year={2017}, month={Oct}, pages={000312–000317} }
 @article{zhao_jagannadham_reainthippayasakul_lanagan_hopkins_2017, title={Characterization of Ultra-Thin Epoxy-Resin Based Dielectric Substrate for Flexible Power Electronics Applications}, volume={2017}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2017-tp55_094}, DOI={10.4071/isom-2017-tp55_094}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Zhao, Xin and Jagannadham, K. and Reainthippayasakul, Wuttichai and Lanagan, Michael T. and Hopkins, Douglas C.}, year={2017}, month={Oct}, pages={000151–000156} }
 @misc{zhao_gao_jiang_zhang_wang_xu_nishiguchi_fukawa_hopkins_2017, title={Flexible epoxy-resin substrate based 1.2 kV SiC half bridge module with ultra-low parasitics and high functionality}, url={http://dx.doi.org/10.1109/ecce.2017.8096700}, DOI={10.1109/ecce.2017.8096700}, abstractNote={To take full advantages of Wide Bandgap power semiconductor devices, breakthroughs on power module development are heavily explored nowadays. This paper introduces a 1.2kV SiC half bridge intelligent power module utilizing 80μm flexible epoxy-resin as substrates instead of traditional Direct-bonded Copper, for better thermal-stress management and lower cost. The investigation on the flexible epoxy-resin material indicates that it has low leakage current even at 250 °C, and high thermal conductivity up to 8 W/mK. No bonding wires are applied in the half bridge power module, instead, double-side solderable SiC MOSFET and diodes are fabricated and utilized for low parasitics and double-side cooling function. To further decrease the entire parasitic inductance on the power loop, a “Stack Structure” is proposed in this work to vertically connect highside and lowside switches with lower interconnection path than traditional power module technology. Simulation indicates that the parasitic inductance on the power loop is less than 1.5 nH. More functionality is achieved by integrating the main power stage with gate driver circuits. Digital isolations are also included in the half bridge module, together with a Low Dropout regulator to eliminate the numbers of auxiliary power supply required by the power module. The size of the entire module is about 35mm × 15mm ×7mm. Electrical simulations and measurements, including leakage current, parasitic extractions, device characteristics, verified that the designed module can work properly with no degradation on the SiC devices, with 12ns turn-off and 48ns turn-on at 800V bus voltage, and 0.63 mJ, 0.23 mJ as turn-on and turn-off loss, respectively.}, note={\urlhttps://ieeexplore.ieee.org/document/8096700/}, journal={2017 IEEE Energy Conversion Congress and Exposition (ECCE)}, publisher={IEEE}, author={Zhao, Xin and Gao, Bo and Jiang, Yifan and Zhang, Liqi and Wang, Sizhen and Xu, Yang and Nishiguchi, Kenji and Fukawa, Yoshi and Hopkins, Douglas C.}, year={2017}, month={Oct}, pages={4011–4018} }
 @misc{hopkins_2017, title={Grid Modernization – FREEDM Systems Center}, author={Hopkins, Douglas C.}, year={2017} }
 @inproceedings{hopkins_2017, title={Heterogeneous Integration Integrated Power Devices Roadmap}, author={Hopkins, Douglas C.}, year={2017} }
 @article{ke_jiang_morgan_hopkins_2017, title={Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors}, volume={2017}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2017-wa32_092}, DOI={10.4071/isom-2017-wa32_092}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Ke, Haotao and Jiang, Yifan and Morgan, Adam J. and Hopkins, Douglas C.}, year={2017}, month={Oct}, pages={000224–000230} }
 @article{zhao_jagannadham_hopkins_2017, title={Multiphysics Performance Evaluation of Flexible Substrate Based 1.2kV SiC Half Bridge Intelligent Power Module with Stacked Dies}, volume={2017}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2017-wp22_095}, DOI={10.4071/isom-2017-wp22_095}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Zhao, Xin and Jagannadham, K. and Hopkins, Douglas C.}, year={2017}, month={Oct}, pages={000353–000359} }
 @article{zhao_jiang_gao_nishiguchi_fukawa_hopkins_2017, title={Novel Polymer Substrate-Based 1.2 kV/40 A Double-Sided Intelligent Power Module}, ISSN={["0569-5503"]}, url={https://www.lens.org/011-940-927-881-704}, DOI={10.1109/ectc.2017.285}, abstractNote={Advanced power module packaging technology is currently being heavily investigated to take full advantage of Wide Band Gap (WBG) power semiconductor devices. As one of most widely applied power module technologies, intelligent power modules, typically for automotive industries, work well to achieve higher operating frequencies with lower losses by integrating gate driver circuits with power semiconductor devices. In this paper, a novel flexible polymer substrate-based intelligent power module is developed and characterized. By applying 80 µm-thick epoxy-resin based flexible dielectric as a substrate, the overall weight and volume of the power module is reduced, as well as the cost, compared with traditional direct bonded copper ceramic-based modules. The performance of the epoxy-resin based dielectric is investigated, and shows that the leakage current of the dielectric at >1.5 kV is less than 20 µA at 250 oC. Double-sided solderable 1.2 kV SiC MOSFETs and Schottky diodes are fabricated and applied in the module without bonding wires, significantly reducing the overall parasitic inductance to}, note={\urlhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7999873 ; \urlhttp://xplorestaging.ieee.org/ielx7/7998598/7999654/07999873.pdf?arnumber=7999873}, journal={2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017)}, author={Zhao, Xin and Jiang, Yifan and Gao, Bo and Nishiguchi, Kenji and Fukawa, Yoshi and Hopkins, Douglas C.}, year={2017}, pages={1461–1467} }
 @inproceedings{morgan_choobineh_fresne_hopkins_2017, title={Numerical and Experimental Determination of Temperature Distribution in 3D Stacked Power Devices}, url={http://dx.doi.org/10.1115/IPACK2017-74222}, DOI={10.1115/ipack2017-74222}, abstractNote={During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.}, note={\urlhttps://proceedings.asmedigitalcollection.asme.org/proceeding.aspx?articleid=2660938 ; \urlhttp://proceedings.asmedigitalcollection.asme.org/proceeding.aspx?articleid=2660938 ; \urlhttps://asmedigitalcollection.asme.org/InterPACK/proceedings/InterPACK2017/58097/V001T01A002/266226}, booktitle={ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems}, publisher={American Society of Mechanical Engineers}, author={Morgan, Adam and Choobineh, Leila and Fresne, David and Hopkins, Douglas C.}, year={2017}, month={Aug} }
 @inproceedings{hopkins_ke_2017, title={True 3D Power Packaging - Higher Densities Through Orthogonality}, author={Hopkins, Douglas C. and Ke, Haotao}, year={2017} }
 @article{zhao_ke_jiang_morgan_xu_hopkins_2016, title={A High Performance Power Module with >10kV capability to Characterize and Test In Situ SiC Devices at >200°C Ambient}, volume={2016}, ISSN={2380-4491}, url={http://dx.doi.org/10.4071/2016-hitec-149}, DOI={10.4071/2016-hitec-149}, abstractNote={Abstract}, number={HiTEC}, journal={Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Zhao, Xin and Ke, Haotao and Jiang, Yifan and Morgan, Adam and Xu, Yang and Hopkins, Douglas C.}, year={2016}, month={Jan}, pages={000149–000158} }
 @inproceedings{hopkins_xu_ke_morgan_2016, title={A New Power Module Design Resource – Laboratory for Packaging Research in Electronic Energy Systems (PREES)}, author={Hopkins, Douglas C. and Xu, Yang and Ke, Haotao and Morgan, Adam}, year={2016} }
 @inproceedings{gao_hopkins_2016, title={A folded GaN VRM with high electrical and thermal performance}, ISBN={9781509029402}, url={http://dx.doi.org/10.1109/3dpeim.2016.7570564}, DOI={10.1109/3dpeim.2016.7570564}, abstractNote={A concept of using folded flexible PCB as substrate for high density power converter modules was proposed in this paper. Then, a 10MHz VRM based on this concept and GaN technology was used to demonstrate electrical and thermal properties of this concept. Finally, the design proposed here was compared with previous GaN power converters.}, booktitle={2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)}, publisher={IEEE}, author={Gao, Bo and Hopkins, D. C.}, year={2016}, month={Jun} }
 @misc{hopkins_2016, title={Additive Manufacturing – 3D Printing of Electronic Energy Systems and Beyond}, author={Hopkins, D.C.}, year={2016} }
 @inproceedings{zhao_xu_hopkins_2016, title={Advanced multi-physics simulation for high performance power electronic packaging design}, ISBN={9781509029402}, url={http://dx.doi.org/10.1109/3dpeim.2016.8048203}, DOI={10.1109/3dpeim.2016.8048203}, abstractNote={Multiphysics simulation is a powerful tool to investigate interactions between thermal, electrical, mechanical aspects in power electronics packaging . Layout design and components selections were verified for 10 kV power module applications . Parasitics on 50kWEV motor drive busbar was extracted. Fringing effects and pre-stress of ZBC substrate were investigated.}, booktitle={2016 International Symposium on 3D Power Electronics Integration and Manufacturing (3D-PEIM)}, publisher={IEEE}, author={Zhao, Xin and Xu, Yang and Hopkins, Douglas C.}, year={2016}, month={Jun} }
 @inproceedings{xu_hopkins_2016, title={Application of 3D Printing for Rapid Prototyping of Advanced Power Electronic Modules}, author={Xu, Yang and Hopkins, Douglas C.}, year={2016} }
 @inproceedings{zhao_gao_hopkins_2016, title={Characterization of Ultra-Thin Flexible Ceramics for High-Density, 3D-Stackable Substrates for Wearable Power Electronics}, author={Zhao, Xin and Gao, Bo and Hopkins, Douglas C.}, year={2016} }
 @inproceedings{morgan_xu_hopkins_husain_yu_2016, title={Decomposition and electro-physical model creation of the CREE 1200V, 50A 3-Ph SiC module}, url={https://www.lens.org/005-651-099-193-878}, DOI={10.1109/apec.2016.7468163}, abstractNote={The CREE 1200V/50A, 25mΩ 6-Pack SiC MOSFET module (CCS050M12CM2) is decomposed into a full 3D CAD model, and materials identified, for use in electrical circuit and multi-physics simulations. A reverse engineering technique is first developed, outlined, and then demonstrated on the CREE module. The ANSYS Q3D Extractor is applied to the 3D CAD model where electrical, lumped parameter, parasitic circuit elements are determined. The model is also analyzed with a multi-physics simulator to provide in-situ thermal maps of the baseplate surface for application scenarios, e.g. with a thermal interface material and pin fin heat sink to capture the thermal spreading from junction to case. The complete model is made open source and freely distributed for use by the reader.}, note={\urlhttps://ieeexplore.ieee.org/document/7468163 ; \urlhttps://works.bepress.com/kang-peng/10/download/ ; \urlhttps://works.bepress.com/kang-peng/10/}, booktitle={Apec 2016 31st annual ieee applied power electronics conference and exposition}, author={Morgan, A. J. and Xu, Y. and Hopkins, Douglas C and Husain, I. and Yu, W. S.}, year={2016}, pages={2141–2146} }
 @inproceedings{rahman_morgans_xu_gao_yu_hopkins_husain_2016, title={Design methodology for a planarized high power density EV/HEV traction drive using SiC power modules}, url={https://www.lens.org/036-754-675-774-950}, DOI={10.1109/ecce.2016.7855018}, abstractNote={This paper provides a methodology for overall system level design of a high-power density inverter to be used for EV/HEV traction drive applications. The system design is guided to accommodate off-the-shelf SiC power modules in a planar architecture that ensures proper electrical, thermal, and mechanical performances. Bi-directional interleaved DC-DC boost structure and a three-phase voltage source inverter (VSI) have been utilized with the primary focus on the size, weight and loss reduction of passive components. A stacked layer approach has been used for a unique PCB-based busbar, ultra-low profile gate driver, and controller board. This holistic design approach results in a highly compact traction drive inverter with power density of 12.1 kW/L that has lower volume and weight compared to the commercially available state-of-the-art power converter systems.}, note={\urlhttps://ieeexplore.ieee.org/document/7855018/}, booktitle={2016 ieee energy conversion congress and exposition (ecce)}, author={Rahman, D. and Morgans, A. J. and Xu, Y. and Gao, R. and Yu, W. S. and Hopkins, Douglas C and Husain, I.}, year={2016} }
 @inproceedings{de_morgan_iyer_ke_zhao_vechalapu_bhattacharya_hopkins_2016, title={Design, package, and hardware verification of a high voltage current switch}, volume={2016-May}, url={https://www.lens.org/076-025-685-154-254}, DOI={10.1109/apec.2016.7467887}, abstractNote={This paper demonstrates various electrical and package design considerations in series connecting a high-voltage (HV) silicon (Si)-IGBT (6500-V/25-A die) and a silicon carbide-junction barrier Schottky diode (6500-V/25-A die) to form an HV current switch. The effects of connecting the cathode of the series diode to an IGBT collector, versus connecting the IGBT emitter to the anode of the series diode, are analyzed in regards to minimizing the parasitic inductance. An optimized package structure is discussed and an HV current switch module is custom fabricated in the laboratory. An HV double pulse test circuit is used to verify the switching performance of the current switch module. Low-voltage and HV converter prototypes are developed and tested to ensure thermal stability of the same. The main motivation of this paper is to enumerate detailed design considerations for packaging an HV current switch.}, note={\urlhttps://ieeexplore.ieee.org/document/7467887/}, booktitle={Apec 2016 31st annual ieee applied power electronics conference and exposition}, author={De, A. and Morgan, A. and Iyer, V. M. and Ke, H. and Zhao, X. and Vechalapu, K. and Bhattacharya, Subhashish and Hopkins, Douglas C}, year={2016}, pages={295–302} }
 @inproceedings{xu_husain_west_yu_hopkins_2016, title={Development of an ultra-high density power chip on bus (PCoB) module}, url={https://www.lens.org/092-761-376-063-354}, DOI={10.1109/ecce.2016.7855040}, abstractNote={A traditional power module uses metal clad ceramic (e.g. DBC or DBA) bonded to a baseplate that creates a highly thermally resistive path, and wire bond interconnect that introduces substantial inductance and limits thermal management to single-sided cooling. This paper introduces a Power Chip on Bus (PCoB) power module approach that reduces parasitic inductance through an integrated power interconnect structure. The PCoB maximizes thermal performance by direct attaching power chips to the busbar, integrating the heatsink and busbar as one, and uses a dielectric fluid, such as air, for electrical isolation. This new power module topology features all planar interconnects and double-sided air cooling. Performance evaluations are carried out through comprehensive electrical and multi-physics simulation and thermal testing for a 1200V, 100A rated single-switch PCoB design. Fabrication and assembly processes are included. For the developed double-sided air-cooled module, 0.5°C/w thermal resistance and 8nH power loop parasitic inductance are achieved.}, note={\urlhttp://ieeexplore.ieee.org/document/7855040/}, booktitle={2016 ieee energy conversion congress and exposition (ecce)}, author={Xu, Y. and Husain, I. and West, H. and Yu, W. S. and Hopkins, Douglas C}, year={2016} }
 @inproceedings{xu_hopkins_2016, title={FEA-based thermal-mechanical optimization for DBC based power modules}, booktitle={2016 International Symposium on 3d Power Electronics Integration and Manufacturing (3d-PEIM)}, author={Xu, Y. and Hopkins, D.}, year={2016} }
 @misc{hopkins_2016, title={Misconception of Thermal Spreading Angle and Misapplication to PCB & Power Modules}, author={Hopkins, Douglas C.}, year={2016} }
 @article{zhao_jagannadham_reainthippayasakul_lanagan_hopkins_2016, title={Thermal and Electrical Characterizations of Ultra-Thin Flexible 3YSZ Ceramic for Electronic Packaging Applications}, volume={2016}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2016-tha13}, DOI={10.4071/isom-2016-tha13}, abstractNote={Abstract}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Zhao, Xin and Jagannadham, K. and Reainthippayasakul, Wuttichai and Lanagan, Michael. T. and Hopkins, Douglas C.}, year={2016}, month={Oct}, pages={000391–000396} }
 @inproceedings{zhao_ke_jiang_morgan_xu_hopkins_2016, title={Ultra Low Leakage Module for 12kV-225 ̊C SiC Semiconductor Testing}, author={Zhao, Xin and Ke, Haotao and Jiang, Yifan and Morgan, Adam and Xu, Yang and Hopkins, Douglas C.}, year={2016}, month={Oct} }
 @inproceedings{hopkins_2015, title={3D Packaging for High Density And High Performance GaN-Based Circuits}, booktitle={2015 IEEE Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2015} }
 @inproceedings{hopkins_2015, title={3D Power Electronics Packaging and Additive Manufacturing}, author={Hopkins, D.C.}, year={2015}, month={Nov} }
 @article{morgan_de_ke_zhao_vechalapu_hopkins_bhattacharya_2015, title={A Robust, Composite Packaging Approach for a High Voltage 6.5kV IGBT and Series Diode}, volume={2015}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2015-wp17}, DOI={10.4071/isom-2015-wp17}, abstractNote={The main motivation of this work is to design, fabricate, test, and compare an alternative, robust packaging approach for a power semiconductor current switch. Packaging a high voltage power semiconductor current switch into a single power module, compared to using separate power modules, offers cost, performance, and reliability advantages. With the advent of Wide-Bandgap (WBG) semiconductors, such as Silicon-Carbide, singular power electronic devices, where a device is denoted as a single transistor or rectifier unit on a chip, can now operate beyond 10kV–15kV levels and switch at frequencies within the kHz range. The improved voltage blocking capability reduces the number of series connected devices within the circuit, but challenges power module designers to create packages capable of managing the electrical, mechanical, and thermal stresses produced during operation. The non-sinusoidal nature of this stress punctuated with extremely fast changes in voltage and current, with respect to time, leads to non-ideal electrical and thermal performance. An optimized power semiconductor series current switch is fabricated using an IGBT (6500V/25A die) and SiC JBS Diode (6000V/10A), packaged into a 3D printed housing, to create a composite series current switch package (CSCSP). The final chosen device configuration was simulated and verified in an ANSYS software package. Also, the thermal behavior of such a composite package was simulated and verified using COMSOL. The simulated results were then compared with empirically obtained data, in order to ensure that the thermal ratings of the power devices were not exceeded; directly affecting the maximum attainable frequency of operation for the CSCSP. Both power semiconductor series current switch designs are tested and characterized under hard switching conditions. Special attention is given to ensure the voltage stress across the devices is significantly reduced.}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Morgan, Adam and De, Ankan and Ke, Haotao and Zhao, Xin and Vechalapu, Kasunaidu and Hopkins, Douglas C. and Bhattacharya, Subhashish}, year={2015}, month={Oct}, pages={000359–000364} }
 @inproceedings{hopkins_2015, title={Additive Manufacturing (a.k.a. 3D Printing) for Designing Power Electronic Systems}, author={Hopkins, D.C.}, year={2015}, month={Oct} }
 @inproceedings{hopkins_ke_2015, title={Additive Manufacturing In Power Electronics Packaging}, author={Hopkins, D.C. and Ke, H.}, year={2015} }
 @inproceedings{de_morgan_bhattacharya_hopkins_2015, title={Design considerations of packaging a high voltage current switch}, booktitle={International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, 2015, vol 3}, author={De, A. and Morgan, A. and Bhattacharya, S. and Hopkins, D. C.}, year={2015} }
 @inproceedings{morgan_hopkins_mckeown_2015, title={Physical Rf Circuit Techniques And The Implications On Future Power Module Design}, author={Morgan, A.J. and Hopkins, D.C. and McKeown, M.}, year={2015}, month={May} }
 @inproceedings{lawrence_hopkins_2015, title={The Evolution and Future Development of Power Electronics as an Essential Element of Power Generation/Delivery, Energy Efficiency, and Industrial Automation}, author={Lawrence, R. and Hopkins, D.C.}, year={2015}, month={Dec} }
 @inproceedings{sung_huang_baliga_ji_ke_hopkins_2015, title={The first demonstration of symmetric blocking SiC gate turn-off (GTO) thyristor}, ISBN={9781479962594 9781479962617}, url={http://dx.doi.org/10.1109/ISPSD.2015.7123438}, DOI={10.1109/ispsd.2015.7123438}, abstractNote={This paper reports the development of symmetric blocking SiC p-GTO thyristors. The proposed thyristor structure features a positive bevel edge termination implemented by orthogonal dicing technique. In this paper, a detailed design of the device structure, forward current-voltage characteristics, and symmetric blocking capabilities are discussed.}, note={\urlhttps://ieeexplore.ieee.org/document/7123438/}, booktitle={2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD)}, publisher={IEEE}, author={Sung, Woongje and Huang, Alex Q. and Baliga, B. J. and Ji, Inhwan and Ke, Haotao and Hopkins, Douglas C.}, year={2015}, month={May}, pages={257–260} }
 @misc{ke_morgan_aman_hopkins_2014, title={3D Printing in the Micro- & Power-Electronics Packaging World}, author={Ke, H. and Morgan, A. and Aman, R. and Hopkins, D.C.}, year={2014} }
 @inproceedings{hopkins_2014, title={Introduction to 3D Printed Power Electronics & Wide Bandgap Power Semiconductor Packaging}, url={http://w.gmsystems.com/uploads/3/1/4/3/3143302/imaps2014.pdf}, booktitle={47th Symposium on Microelectronics (IMAPS 2014)}, author={Hopkins, Douglas C.}, year={2014}, month={Oct} }
 @article{ke_morgan_aman_hopkins_2014, title={Investigation of Rapid-Prototyping Methods for 3D Printed Power Electronic Module Development}, volume={2014}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-thp52}, DOI={10.4071/isom-thp52}, abstractNote={The recent research in wide-bandgap (WBG) power electronic semiconductors has produced a wide variety of device and combinational topologies, such as HFETS, MOSHFETS, and the Cascode Pair. Each variation needs to be tested with certain package criteria (e.g. high voltage SiC devices up to 15kV, high current GaN devices up to 300A, or unprecedented high frequencies). Having a common package is costly and cannot provide an investigation of optimized performance. Hence, use of a rapid prototyping method to print power electronic packages and modules is needed. Also, the continual move to higher frequencies will require greater integration of packaging into the end application, as is presently done with point-of-load converters. The future modules will take on more functional integration, including more mechanical features, which further supports use of printed fabrication technologies. It is not reasonable to assume that a complete module can be directly printed, though most would be; some assembly is required. This paper discusses partitioning of a module process, and identifying key elements that can be combined for optimum power package production.}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Ke, Haotao and Morgan, Adam and Aman, Ronald and Hopkins, Douglas C}, year={2014}, month={Oct}, pages={000887–000892} }
 @inproceedings{xu_hopkins_2014, title={Misconception of thermal spreading angle and misapplication to IGBT power modules}, url={https://www.lens.org/136-404-571-880-535}, DOI={10.1109/apec.2014.6803362}, abstractNote={This paper analyzes the widely used 45 degrees thermal spreading model in IGBT package design and quantifies error in application to both single and multilayered package structures. The results are compared with finite element analysis (FEA). For single-layer heat transfer problem, the spreading angle model with a 45 degrees assumption provides a less than 20% conservative error of thermal resistance for a certain substrate layer thickness range, but is not applicable to multi-layered structures. For two or more layered structures, as commonly found in direct bonded copper (DBC) substrates and used in multiple-chip power modules (MCPMs), the 45 degrees fixed-angle method cannot capture the behavior of the heat transfer problem nor accurately predict the temperature of critical points for design. The method introduces substantial underestimation of junction temperature dependent on layer thickness ratios. An in-depth literature review was conducted and little, if any, concrete basis for the 45 degree assumption was found. Guidelines for using more accurate spreading-angle calculations are provided for the practice engineer.}, note={\urlhttps://ieeexplore.ieee.org/document/6803362}, booktitle={2014 twenty-ninth annual ieee applied power electronics conference and exposition (apec)}, author={Xu, Y. and Hopkins, Douglas C}, year={2014}, pages={545–551} }
 @inproceedings{hopkins_xu_ke_2014, title={Printed Interfacial Interconnects in High Power Module}, author={Hopkins, D.C. and Xu, Y. and Ke, H.}, year={2014} }
 @book{xu_hopkins_2014, title={Thermal-mechanical design and optimization for DBC based power modules}, author={Xu, Yang and Hopkins, D.C.}, year={2014} }
 @article{ke_xu_hopkins_2013, title={Conceptual Development Using 3D Printing Technologies for 8kV SiC Power Module Package}, volume={2013}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2013-wp62}, DOI={10.4071/isom-2013-wp62}, abstractNote={Post-silicon power devices, SiC or GaN for example, have many advantages over traditional silicon devices, particularly for smaller size and higher thermal densities. Although these devices are in the early stage of development, many applications have been identified, such as hybrid vehicles and the smart grid. For power packaging, there is now a greater challenge of much higher voltage, faster switching speed and much smaller package size (higher density). All of these issues call for newer approaches in power packaging.}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Ke, Haotao and Xu, Yang and Hopkins, Douglas C}, year={2013}, month={Jan}, pages={000758–000763} }
 @article{bhat_oh_hopkins_2013, title={Feasibility of a MEMS Sensor for Gas Detection in HV Oil-Insulated Transformer}, volume={49}, ISSN={0093-9994 1939-9367}, url={http://dx.doi.org/10.1109/TIA.2012.2229681}, DOI={10.1109/tia.2012.2229681}, abstractNote={This paper addresses protection of oil-insulated transformers, using a microelectromechanical systems (MEMS) sensor system to augment or replace existing protection techniques. Traditional technologies used for protection and analysis involve pressure and temperature sensing, gas chromatography, and/or a Buchholz relay. The proposed MEMS device is immersed within the insulating fluid, e.g., oil, and primarily consists of multiple microscale turbines centrally shafted to a MEMS generator. The device utilizes relative differences in the velocity, pressure, and flow rate of fluid caused by electric faults. A differential electrical output is produced, which can be coupled to a remote recorder.}, note={\urlhttps://ieeexplore.ieee.org/document/6361292/ ; \urlhttps://www.researchgate.net/profile/DC_Hopkins/publication/260706240_Feasibility_of_a_MEMS_Sensor_for_Gas_Detection_in_HV_Oil-Insulated_Transformer/links/54170b2f0cf2218008bec49d.pdf}, number={1}, journal={IEEE Transactions on Industry Applications}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Bhat, Krishna Prasad and Oh, Kwang W. and Hopkins, Douglas C.}, year={2013}, month={Jan}, pages={316–321} }
 @inproceedings{hopkins_2013, title={Understanding Impact of New Additive Manufacturing Techniques on Power Electronics Design}, author={Hopkins, D.C.}, year={2013}, month={Mar} }
 @inproceedings{hopkins_2012, title={Advanced Bus Bar System Design}, booktitle={IEEE Energy Conversion Congress and Exposition, ECCE}, author={Hopkins, Douglas C.}, year={2012}, month={Sep} }
 @inproceedings{hopkins_2012, place={Orlando, FL, Feb}, title={Bus Bars – Slap Them Together and They Ought to Work}, booktitle={27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE Applied Power Electronics Conf}, author={Hopkins, Douglas C.}, year={2012}, month={Feb} }
 @article{ke_hopkins_2012, title={Development of Printed Power Packaging for a High Voltage SiC Module}, volume={2012}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2012-wp55}, DOI={10.4071/isom-2012-wp55}, abstractNote={Due to rapidly developing post silicon power devices, in particular SiC and GaN, three primary parameters in power packaging: temperature, voltage and current, are much more difficult to manage. The SiC devices are being developed for high voltage (>15kV). The GaN devices will have extremely low internal resistance, operate at extreme current densities (≫10A/mm2), and can account for <50% of the resistance in a power module. Both devices can operate at high temperatures (>300°C) and >10-times frequency compared to Si. The traditional power electronics packaging approaches need augmentation or replacement. Most technologies used in packaging of power electronic systems, or more generally Electronic Energy Systems, are ported from microelectronics. The recent development of printable 3D circuit techniques, e.g. jetting and dispensing, provide additional major approaches applicable to power packaging. Some printing techniques are already applied to solar cells and batteries. This paper explores the printable electronics technologies for application to power.}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Ke, Haotao and Hopkins, Douglas C}, year={2012}, month={Jan}, pages={000955–000960} }
 @article{hopkins_baltis_pitaress_hazelmyer_2012, title={Extreme Thermal Transient Stress Analysis with Pre-Stress in a Metal Matrix Composite Power Package}, volume={2012}, ISSN={2380-4491}, url={http://dx.doi.org/10.4071/hitec-2012-tha25}, DOI={10.4071/hitec-2012-tha25}, abstractNote={This paper culminates several years of development of a SiC MOSFET-based solid-state circuit breaker power module designed and fabricated for aluminum-based composite metal-ceramic packaging. The aluminum composite structure was used for high temperature thermal management >350°C and high reliability. Testing of the final module surpassed 750 total cycles.}, number={HITEC}, journal={Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Hopkins, Douglas C. and Baltis, Theodore and Pitaress, James M and Hazelmyer, Donald R.}, year={2012}, month={Jan}, pages={000361–000372} }
 @inproceedings{basaran_li_hopkins_yao_2012, title={Mean time to failure of SnAgCuNi solder joints under DC}, ISBN={9781424495320 9781424495337 9781424495313}, url={http://dx.doi.org/10.1109/itherm.2012.6231474}, DOI={10.1109/itherm.2012.6231474}, abstractNote={Electromigration time to failure and electrical resistivity of 95.5%Sn-1.5%Ag-0.5%Cu-0.03W%Ni (SACN) microelectronics solder joints have been investigated experimentally. A Black's type electromigration time to failure equation is developed to describe the time to failure versus current density and temperature. The activation energy over the range of 83°C~174°C is measured to be 0.77±0.12eV, and the current density exponent is found to be (8.60±1.65). It is also shown that the most commonly used Black's electromigration time to failure equation cannot be used for solder joints.}, booktitle={13th InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems}, publisher={IEEE}, author={Basaran, Cemal and Li, Shidong and Hopkins, Douglas C. and Yao, Wei}, year={2012}, month={May} }
 @inproceedings{hopkins_2012, title={Point Source Thermal Management in Dense Power Modules and Systems}, author={Hopkins, D.C.}, year={2012} }
 @inproceedings{hopkins_2012, title={Printable Packaging for High Power, High Temperature Power Module}, author={Hopkins, D.C.}, year={2012} }
 @inproceedings{bhat_guo_xu_baltis_hazelmyer_hopkins_2012, title={Results for an Al/AlN composite 350°C SiC solid-state circuit breaker module}, ISBN={9781457712166 9781457712159 9781457712142}, url={http://dx.doi.org/10.1109/apec.2012.6166172}, DOI={10.1109/apec.2012.6166172}, abstractNote={This paper describes final results for the verification and testing of a SiC MOSFET-based solid-state circuit breaker power module for ultra-fast current interruption. The module exhibited a single-die (4.1mm × 4.1 mm) 48 A, 5 ms trip point from a 300 V bus with a di/dt of 2.1 kA/us (23 ns opening time). An internal snubber increased the response to 390 ns. The die absorbed ~4.6 J causing a transient junction temperature increase of ~245 °C. Ambient was set at 25 °C and 105 °C. Hence, maximum junction temperature was conservatively projected to reach 350 °C during the 5 ms pulse. An Aluminum composite structure was used for high temperature thermal management and high reliability. Testing of the final module surpassed 750 total cycles. Electrical, thermal and mechanical design and testing results are presented.}, booktitle={2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Bhat, Krishna P. and Guo, Yuan-Bo and Xu, Yang and Baltis, Theodore and Hazelmyer, Donald R. and Hopkins, Douglas C.}, year={2012}, month={Feb} }
 @inproceedings{hopkins_2011, title={Ground Rules for Designing Power Electronics into Evolving MicroGrid Applications}, booktitle={26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2011}, month={Mar} }
 @article{baltis_hopkins_pitaressi_hazelmyer_2011, title={High Thermal-Transient Packaging for a SiC-Based Solid State Circuit Breaker}, volume={2011}, ISSN={2380-4505}, url={http://dx.doi.org/10.4071/isom-2011-wa5-paper2}, DOI={10.4071/isom-2011-wa5-paper2}, abstractNote={Solid-State Circuit Breakers (SSCBs), or Contactors, are critical components in next generation electric aircraft, and must be small in size, fast in response, and have high reliability. Silicon Carbide (SiC) semiconductor switches provide a series of improvements over traditional silicon-based breakers in both electrical and thermal performances. The reported SSCB uses SiC MOSFETs mounted on cast-aluminum traces, cast onto an aluminum nitride (AlN) ceramic co-captured in an aluminum composite baseplate. The system is similar to an AlSiC and Direct-Bonded-Aluminum (DBA) approach.}, number={1}, journal={International Symposium on Microelectronics}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Baltis, Theodore and Hopkins, Douglas C and Pitaressi, James M and Hazelmyer, Donald R}, year={2011}, month={Jan}, pages={000608–000618} }
 @inproceedings{guo_bhat_aravamudhan_hopkins_hazelmyer_2011, title={High current and thermal transient design of a SiC SSPC for aircraft application}, ISBN={9781424480845}, url={http://dx.doi.org/10.1109/apec.2011.5744759}, DOI={10.1109/apec.2011.5744759}, abstractNote={Solid-State Power Controllers (SSPCs) are critical components in the development of electric aircraft and must be small in size, fast in response, and have high reliability. The development of Silicon Carbide (SiC) semiconductor switches provides a series of improvements for the SSPCs in both electrical and thermal performances. In the proposed SSPC design, SiC MOSFETs die are mounted on cast-aluminum traces, under which are an aluminum nitride (AlN) layer and an aluminum composite baseplate. The concept of i2t and its application in solid state protection is discussed. Transient thermal characterizations of SiC MOSFETs are provided on this nearly-all-aluminum package by Finite Element Analysis (FEA). Electrical experiments are combined to demonstrate critical transient thermal performance of a 120A-nominal/1200A-fault, 320Vdc SSPC designed for 350˚C SiC transient junction temperature.}, booktitle={2011 Twenty-Sixth Annual IEEE Applied Power Electronics Conference and Exposition (APEC)}, publisher={IEEE}, author={Guo, Yuan-Bo and Bhat, Krishna P. and Aravamudhan, Arunkumar and Hopkins, Douglas C. and Hazelmyer, Donald R.}, year={2011}, month={Mar} }
 @inbook{hopkins_2011, place={Burlington, MA}, edition={3rd}, title={Packaging and Smart Power Systems}, ISBN={9780123820365}, url={http://dx.doi.org/10.1016/b978-0-12-382036-5.00044-6}, DOI={10.1016/b978-0-12-382036-5.00044-6}, abstractNote={This chapter provides background information, framework, and procedures to produce guide and system partitioning and functional integration. Circuits are typically designed based upon a pre-determined set of packaging technologies ranging from silicon integration of sub-circuit functions to multiple boards in a rack. Partitioning a circuit for packaging in one technology, such as all silicon, is straightforward. A first step to partitioning is creation of a comprehensive categorized list of electrical, mechanical, and thermal, technical user requirements. The second step is creation of a simple component characterization map that identifies dominant attributes of the components. A high-frequency magnetic core couples the radiated field into a copper conductor on a printed wiring board (PWB) and causes eddy current heating, increasing the skin-effect resistance. Higher resistance loss further increases conductor heating which increases the mechanical stresses between the conductor and PWB leading to early failure. Limitation of the dielectric isolation process is the higher cost. However, dielectric isolation does provide for more reliable isolation with greater circuit flexibility.}, booktitle={Power Electronics Handbook}, publisher={Butterworth-Heinemann/Elsevier}, author={Hopkins, Douglas C.}, editor={Rashid, Muhammad H.Editor}, year={2011}, pages={1275–1286} }
 @inproceedings{bhat_oh_hopkins_2010, title={A MEMS Sensor for Gas Detection in High Voltage Oil Filled Equipment}, ISBN={9781424463930}, url={http://dx.doi.org/10.1109/ias.2010.5615297}, DOI={10.1109/ias.2010.5615297}, abstractNote={Abstract - This paper addresses protection of oil insulated power equipment, e.g. transformers, using a MEMS sensor system to augment or replace existing protection techniques. Traditional technologies used for protection and analysis involve pressure and temperature sensing, gas chromatography and/or a Buchholz relay. A MEMS sensor is described to augment or replace such sensors. The proposed device is immersed within the insulating fluid, e.g. oil, and primarily consists of multiple micro scale turbines centrally shafted to a MEMS generator. The device utilizes relative differences in velocity, pressure and flow rate, of gas emanating from stressed or degrading insulation. A differential electrical output is produced which can be RF or photon coupled to a user interface.}, booktitle={2010 IEEE Industry Applications Society Annual Meeting}, publisher={IEEE}, author={Bhat, Krishna Prasad and Oh, Kwang W. and Hopkins, Douglas C.}, year={2010}, month={Oct} }
 @inproceedings{bhat_hopkins_2010, title={Augmenting Bucholz Relay Using Embedded Mems Gas Sensor}, author={Bhat, K.P. and Hopkins, D.C.}, year={2010} }
 @inproceedings{hopkins_guo_aravamudhan_scofield_2010, title={Development and Testing of a 350 ̊C SiC MCPM with Cast Metal Matrix Composites}, author={Hopkins, D.C. and Guo, Y.B. and Aravamudhan, A. and Scofield, J.D.}, year={2010} }
 @article{hopkins_guo_dwyer_scofield_2010, title={Development of a SiC SSPC Module with Advanced High Temperature Packaging}, volume={2010}, ISSN={2380-4491}, url={http://dx.doi.org/10.4071/hitec-dhopkins-wp25}, DOI={10.4071/hitec-dhopkins-wp25}, abstractNote={Development of a multi-chip power module (MCPM) is reported that uses advanced metal-matrix composite aluminum packaging to manage high thermally induced stresses in devices that incur 350°C transients. The MCPM uses parallel SiC devices to control 120A DC nominal, 1200A fault in a 270V DC system. Electrical system modeling is presented to characterize electrical fault transients that induce electrical and thermal stresses in the semiconductors and packaging. The characterization of the advanced aluminum-based packaging system, which uses composites, such as AlSiC, and direct bonded aluminum (DBA), is discussed to manage the thermal stresses and transient heat flow.}, number={HITEC}, journal={Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT)}, publisher={IMAPS - International Microelectronics Assembly and Packaging Society}, author={Hopkins, Douglas C and Guo, Yuan-Bo and Dwyer, Herbert E and Scofield, James D.}, year={2010}, month={Jan}, pages={000310–000315} }
 @inproceedings{hopkins_2010, title={Power Electronics in a Smart-Grid Distribution System}, booktitle={25th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2010}, month={Feb} }
 @inproceedings{hopkins_2010, title={Solid-State Protection: Dual-use for Microgrids}, author={Hopkins, D.C.}, year={2010} }
 @inproceedings{wang_du_guo_hopkins_bhattacharya_huang_2009, title={A 6.5kV IGBT Development Module for Renewable Energy Systems}, author={Wang, G. and Du, Y. and Guo, Y. and Hopkins, D.C. and Bhattacharya, S. and Huang, A.}, year={2009} }
 @article{hosny_hopkins_gay_safiuddin_2009, title={A Dynamic Model for a Gas-Liquid Corona Discharge Using Neural Networks}, volume={24}, ISSN={0885-8977 1937-4208}, url={http://dx.doi.org/10.1109/tpwrd.2008.2005880}, DOI={10.1109/tpwrd.2008.2005880}, abstractNote={This paper presents a novel dynamic nonlinear model for pulsed corona discharge using backpropagation neural networks. The Levenberg-Marquardt training algorithm, which is perfectly suitable for fitting functions, is employed. The developed model is based on the voltage-current characteristics of an actual hybrid-series reactor and takes the practical constrains associated with a real system into account. The validity and accuracy of the model have been tested in the Electromagnetic Transients Program, using MODELS language and a TACS-91 time-variant controlled resistor. The results clearly demonstrate that the BPNN-based model is very robust and effective in emulating the chaotic performance for pulsed corona discharge using backpropagation neural networks.}, number={3}, journal={IEEE Transactions on Power Delivery}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hosny, A.A. and Hopkins, D.C. and Gay, Z.B. and Safiuddin, M.}, year={2009}, month={Jul}, pages={1234–1239} }
 @inproceedings{hopkins_2009, title={Advanced Packaging for Power and Energy}, booktitle={42nd Symposium on Microelectronics (IMAPS 2009)}, author={Hopkins, Douglas C.}, year={2009}, month={Nov} }
 @inproceedings{hopkins_guo_jao_2009, title={Assessment of Critical Issues for High Temperature, High Voltage Power Modules}, author={Hopkins, D.C. and Guo, Y.B. and Jao, P.F.}, year={2009} }
 @inproceedings{basaran_li_hopkins_veychard_2009, title={Electromigration Time to Failure of SnAgCuNi Solder Joints}, author={Basaran, Cemal and Li, Shidong and Hopkins, Douglas C. and Veychard, Damien}, year={2009} }
 @article{basaran_li_hopkins_veychard_2009, title={Electromigration time to failure of SnAgCuNi solder joints}, volume={106}, ISSN={0021-8979 1089-7550}, url={http://dx.doi.org/10.1063/1.3159012}, DOI={10.1063/1.3159012}, abstractNote={Electromigration time to failure and electrical resistivity of 95.5%Sn–1.5%Ag–0.5%Cu–0.03W%Ni microelectronics solder joints have been investigated experimentally. A Black-type electromigration time to failure equation is developed to describe the time to failure versus current density and temperature. It is observed that resistance of a solder joint is not just a function of the temperature but also a function of the current density. The activation energy over the range of 83–174°C is measured to be 0.77±0.12eV, and the current density exponent is found to be (8.60±1.65). It is also shown that the most commonly used Black’s electromigration time to failure equation cannot be used for solder joints.}, number={1}, journal={Journal of Applied Physics}, publisher={AIP Publishing}, author={Basaran, Cemal and Li, Shidong and Hopkins, Douglas C. and Veychard, Damien}, year={2009}, month={Jul}, pages={013707} }
 @inproceedings{hopkins_2009, title={Integrated Packaging Techniques}, booktitle={24th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2009}, month={Feb} }
 @inproceedings{guo_jao_hopkins_2009, title={Investigation of High Electrical Gradients in High Voltage Power Modules}, author={Guo, Y.B. and Jao, P.F. and Hopkins, D.C.}, year={2009} }
 @inproceedings{guo_jao_wang_du_bhattacharya_hopkins_2009, title={Investigation of SiC Power Module Requirement for Smart Grid Applications}, author={Guo, Y. and Jao, P.F. and Wang, G. and Du, Y. and Bhattacharya, S. and Hopkins, D.C.}, year={2009} }
 @inproceedings{hopkins_2008, title={Advanced Energy Packaging Techniques}, booktitle={23rd Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2008}, month={Feb} }
 @inproceedings{hopkins_2008, title={Advanced Power Packaging for Higher Temperatures and Harsh Environments}, booktitle={41st International Symposium on Microelectronics}, author={Hopkins, Douglas C.}, year={2008}, month={Nov} }
 @inproceedings{abdulhamid_hopkins_basaran_2008, title={Low Temperature Electromigration and Thermomigration in Lead-Free Solder Joints}, author={Abdulhamid, M. and Hopkins, D.C. and Basaran, C.}, year={2008} }
 @inproceedings{hopkins_kellerman_2008, title={Stress Management in a High Temperature Multilayered Composite Structure}, author={Hopkins, D.C. and Kellerman, D.W.}, year={2008} }
 @inproceedings{enser_hopkins_basaran_2007, title={A Review of Electromigration Under Time Varying Current Stressing}, author={Enser, Kevin E. and Hopkins, Douglas C. and Basaran, Cernal}, year={2007}, month={Apr} }
 @inproceedings{hopkins_2007, place={San Jose, CA}, title={Advanced Power Packaging for High Reliability and Higher Temperatures}, booktitle={40th International Symposium on Microelectronics}, author={Hopkins, Douglas C.}, year={2007}, month={Nov} }
 @inproceedings{mckay_hopkins_basaran_abdulhamid_2007, title={Harsh Environment Thermal Management Using Aluminum-Based Packaging}, author={McKay, T. and Hopkins, D.C. and Basaran, C. and Abdulhamid, M.F.}, year={2007} }
 @inproceedings{abdulhamid_hopkins_basaran_2007, title={IMC Effects in Solder from High Thermal Gradients Management}, author={Abdulhamid, M.F. and Hopkins, D.C. and Basaran, C.}, year={2007} }
 @inproceedings{hopkins_2007, place={Anaheim}, title={Introduction to Power Packaging Techniques}, booktitle={22nd Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2007}, month={Feb} }
 @inbook{hopkins_2007, place={Burlington, MA}, edition={2nd}, title={Packaging and Smart Power Systems}, ISBN={9780120884797}, url={http://dx.doi.org/10.1016/b978-012088479-7/50060-2}, DOI={10.1016/b978-012088479-7/50060-2}, booktitle={Power Electronics Handbook}, publisher={Academic Press/Elsevier}, author={Hopkins, Douglas C.}, editor={Rashid, Muhammad H.Editor}, year={2007}, pages={1147–1158} }
 @inproceedings{enser_hopkins_basaran_2007, place={Washington, D.C.}, title={Solder Interconnect Electromigration Due to Time Varying Current Stressing}, volume={10}, booktitle={Proceedings of the 2007 International Symposium on Microelectronics : November 11-15, 2007, San Jose Convention Center, San Jose, California, USA}, publisher={IMAPS}, author={Enser, K.E. and Hopkins, D.C. and Basaran, C.}, year={2007} }
 @inproceedings{mckay_hopkins_basaran_2007, place={Washington, D.C.}, title={The effect of layer thickness variation on the thermo-mechanical properties of direct aluminum bonded substrates on AlSiC}, booktitle={Proceedings of the 2007 International Symposium on Microelectronics : November 11-15, 2007, San Jose Convention Center, san Jose, California, USA}, publisher={IMAPS}, author={McKay, T. and Hopkins, D.C. and Basaran, C.}, year={2007} }
 @inproceedings{hopkins_2006, title={Advanced Power Electronics Packaging High-Current High Temperature Applications}, booktitle={21st Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2006}, month={Mar} }
 @inproceedings{hopkins_kellerman_basaran_gomez_2006, place={Washington, D.C.}, title={Aluminum-Based High-Temperature (>200°C) Packaging for SiC Power Converters}, booktitle={Proceedings 2006 International Symposium on Microelectronics : October 8-12, 2006 : San Diego Convention Center, San Diego, Calif.}, publisher={IMAPS}, author={Hopkins, D.C. and Kellerman, D.W. and Basaran, C. and Gomez, J.}, year={2006}, pages={734–741} }
 @article{ye_basaran_hopkins_2006, title={Experimental Damage Mechanics of Micro/Power Electronics Solder Joints under                 Electric Current Stresses}, volume={15}, ISSN={1056-7895 1530-7921}, url={http://dx.doi.org/10.1177/1056789506054311}, DOI={10.1177/1056789506054311}, abstractNote={ Experimental damage mechanics of flip chip solder joints under current stressing is studied using 20 test vehicle flip chip modules. Three different failure modes are observed. The dominant damage mechanism is caused by the combined effect of electromigration and thermomigration, where void nucleation and growth lead to the ultimate failure of the module. It is observed that thermomigration driving forces are stronger than electromigration; as a result thermomigration, not electromigration, determines the site of void nucleation. The void nucleation and growth modes and their preferred sites are also observed and discussed in detail. The interface between the Ni barrier layer and the solder joint is found to be the favorite site of void nucleation and growth. The effect of pre-existing voids on the failure process of a solder joint is also studied. It is observed that Black’s time to failure law for thin films is unreliable for solder joints. }, number={1}, journal={International Journal of Damage Mechanics}, publisher={SAGE Publications}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2006}, month={Jan}, pages={41–67} }
 @inproceedings{abdulhamid_basaran_hopkins_2006, title={Experimental Study of Thermomigration in Lead-Free Nanoelectronics Solder Joints}, ISBN={0791847691}, url={http://dx.doi.org/10.1115/imece2006-13119}, DOI={10.1115/imece2006-13119}, abstractNote={The study of thermomigration on Sn-Ag-Cu solder sphere subjected to a high thermal gradient of 1100°C/cm is presented. After 286 hours, the hot end showed a thin and flat intermetallic compound (IMC) while the cold side showed a scallop-like Cu6Sn5 IMC. Small voids can be seen within the Cu6Sn5 IMC after 712 hours on the cold side, while the IMC on the opposite side showed no observable changes.}, booktitle={Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology}, publisher={ASMEDC}, author={Abdulhamid, Mohd F. and Basaran, Cemal and Hopkins, Douglas C.}, year={2006}, month={Jan} }
 @inproceedings{hopkins_kellerman_wunderlich_basaran_gomez_2006, title={High-temperature, high-density packaging of a 60kW converter for >200/spl deg/C embedded operation}, ISBN={0780395476}, url={http://dx.doi.org/10.1109/apec.2006.1620641}, DOI={10.1109/apec.2006.1620641}, abstractNote={This paper describes the design of a 60kW, actuator motor drive using high temperature SiC devices. Power JFET devices are selected for high-frequency performance and high density. High-density packaging uses an aluminum conductor, AlN substrate and AlSiC combination to minimize dissimilar interfaces. The forced air-cooled design provides >1.1kW/cu.in.}, booktitle={Twenty-First Annual IEEE Applied Power Electronics Conference and Exposition, 2006. APEC '06.}, publisher={IEEE}, author={Hopkins, D.C. and Kellerman, D.W. and Wunderlich, R.A. and Basaran, C. and Gomez, J.}, year={2006}, month={Apr} }
 @article{basaran_ye_hopkins_frear_lin_2005, title={Flip chip solder joint failure modes}, volume={14}, number={10}, journal={Advanced Packaging}, author={Basaran, C. and Ye, H. and Hopkins, D.C. and Frear, D. and Lin, J.K.}, year={2005}, month={Oct}, pages={14–19} }
 @inproceedings{thondapu_hopkins_holguin_2005, title={Implementing Digital Power Control In Automotive Alternators}, author={Thondapu, C. and Hopkins, D.C. and Holguin, G.}, year={2005} }
 @inproceedings{ye_basaran_hopkins_lin_2005, title={Modeling deformation in microelectronics BGA solder joints under high current density. Part I. Simulation and testing}, ISBN={0780389069}, url={http://dx.doi.org/10.1109/ectc.2005.1441975}, DOI={10.1109/ectc.2005.1441975}, abstractNote={In this paper, Moire interferometry technique is used to measure the in-situ displacement evolution of lead-free solder joint under electric current stressing. Large deformation was observed in solder joint under high density (10/sup 4/A/cm/sup 2/) current stressing. The deformation was found to be due to electromigration in the solder joint. An electromigration constitutive model is developed to simulate deformation of lead-free solder joint under current stressing. The simulation predicts reasonably close displacements results to Moire interferometry experimental results in both spatial distribution and time history evolution, which indicates that the electromigration model is reasonably good for predicting the mechanical behavior of lead-free solder alloy under electric current stressing. This is the first part of the papers reporting the deformation of solder joint under current stressing. More experimental results are reported in the second paper.}, booktitle={Proceedings Electronic Components and Technology, 2005. ECTC '05.}, publisher={IEEE}, author={Ye, Hua and Basaran, C. and Hopkins, D.C. and Lin, Minghui}, year={2005}, month={Jul} }
 @inproceedings{ye_basaran_hopkins_frear_lin_2004, title={Damage mechanics of microelectronics solder joints under high current densities}, ISBN={0780383656}, url={http://dx.doi.org/10.1109/ectc.2004.1319460}, DOI={10.1109/ectc.2004.1319460}, abstractNote={The electromigration damage in flip chip solder joints of eutectic Sn/Pb was studied under current stressing. The height of the solder joints was 100 /spl mu/m. The mass accumulation near anode side and void nucleation near cathode were observed during current stressing. Surface marker movement technique is used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity, D/spl times/Z*, of the solder. Subsequent experiments reveal that the presence of thermomigration due to joule heating makes the extraction of the product of effective charge number and diffusivity erroneous when using marker movement technique. Pb Phase growth is observed under different current density and temperature. Higher current density leads to faster grain coarsening. Based on the test results, a grain coarsening equation including the influence of current density is proposed, d/sup n/ - d/sup n//sub 0/ = Kj/sup m/t. The current density exponent m is found to be 3, and phase growth exponent n is found to be 5.5. Within our test temperature range, electric current seems to have greater influences on phase growth of solder joint than temperature or thermomigration caused by the temperature gradient due to joule heating during current stressing. Nano indentation tests suggest that mechanical property, e.g. Young's modulus, degrades in the localized area where void nucleates during current stressing.}, booktitle={2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546)}, publisher={IEEE}, author={Ye, Hua and Basaran, C. and Hopkins, D.C. and Frear, D. and Lin, Jong-Kai}, year={2004}, month={Sep} }
 @inproceedings{basaran_ye_hopkins_2004, title={Deformation of Solder Joints Under Current Stressing: Experimental Measurement and Numerical Simulation}, author={Basaran, C. and Ye, H. and Hopkins, D.C.}, year={2004} }
 @article{ye_basaran_hopkins_2004, title={Deformation of solder joint under current stressing and numerical simulation––I}, volume={41}, ISSN={0020-7683}, url={http://dx.doi.org/10.1016/j.ijsolstr.2004.04.002}, DOI={10.1016/j.ijsolstr.2004.04.002}, abstractNote={In this paper, Moiré interferometry technique is used to measure the in situ displacement evolution of lead-free solder joint under electric current stressing. Large deformation was observed in solder joint under high density (104 A/cm2) current stressing. The deformation was found to be due to electromigration in the solder joint. An electromigration constitutive model is applied to simulate deformation of lead-free solder joint under current stressing. The simulation predicts reasonably close displacements results to Moiré interferometry experimental results in both spatial distribution and time history evolution, which indicates that the electromigration model is reasonably good for predicting the mechanical behavior of lead-free solder alloy under electric current stressing. This is the first part of the papers reporting the deformation of solder joint under current stressing. More experimental results are reported in the second paper.}, number={18-19}, journal={International Journal of Solids and Structures}, publisher={Elsevier BV}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2004}, month={Sep}, pages={4939–4958} }
 @article{ye_basaran_hopkins_2004, title={Deformation of solder joint under current stressing and numerical simulation––II}, volume={41}, ISSN={0020-7683}, url={http://dx.doi.org/10.1016/j.ijsolstr.2004.04.003}, DOI={10.1016/j.ijsolstr.2004.04.003}, abstractNote={In this paper, the Moiré interferometry technique is used to measure the in situ displacement evolution of lead-free solder joint under electric current stressing. Large amounts of deformation were observed in the solder joint under high density (above 5000 A/cm2) current stressing. The deformation was found to be due to electromigration in the solder joint and an electromigration constitutive model was applied to simulate the deformation. Both the experimental observations and finite element method (FEM) simulation results indicate that, in addition to the current density level, the current density distribution within the solder joint has a great effect on the displacement development in the solder joint under current stressing. Specifically, greater non-uniformity in current density leads to greater normal deformations within the solder joint in this test module. This is the second part of a series of papers reporting on the deformation of solder joints under current stressing.}, number={18-19}, journal={International Journal of Solids and Structures}, publisher={Elsevier BV}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C}, year={2004}, month={Sep}, pages={4959–4973} }
 @article{basaran_ye_hopkins_frear_lin_2004, title={Failure Modes of Flip Chip Solder Joints Under High Electric Current Density}, volume={127}, ISSN={1043-7398 1528-9044}, url={http://dx.doi.org/10.1115/1.1898338}, DOI={10.1115/1.1898338}, abstractNote={The failure modes of flip chip solder joints under high electrical current density are studied experimentally. Three different failure modes are reported. Only one of the failure modes is caused by the combined effect of electromigration and thermomigration, where void nucleation and growth contribute to the ultimate failure of the module. The Ni under bump metallization–solder joint interface is found to be the favorite site for void nucleation and growth. The effect of pre-existing voids on the failure mechanism of a solder joint is also investigated}, number={2}, journal={Journal of Electronic Packaging}, publisher={ASME International}, author={Basaran, C. and Ye, H. and Hopkins, D. C. and Frear, D. and Lin, J. K.}, year={2004}, month={Sep}, pages={157–163} }
 @article{ye_basaran_hopkins_2004, title={Mechanical Implications of High Current Densities in Flip-chip Solder Joints}, volume={13}, ISSN={1056-7895 1530-7921}, url={http://dx.doi.org/10.1177/1056789504044282}, DOI={10.1177/1056789504044282}, abstractNote={ We studied the electromigration damage to flip-chip solder joints of eutectic Sn/Pb under current stressing at room temperature with a current density of 1.3 × 104 A/cm2. The height of the solder joints was 100 μm. The mass accumulation near the anode side and the void nucleation near the cathode were observed during current stressing. In the preliminary experiment, the surface marker movement technique was used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity (D × Z*) of the solder. Subsequent experiments revealed that the presence of thermomigration due to joule heating makes the extraction of the product of effective charge number and diffusivity erroneous when using marker movement technique. }, number={4}, journal={International Journal of Damage Mechanics}, publisher={SAGE Publications}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2004}, month={Oct}, pages={335–345} }
 @article{ye_basaran_hopkins_2004, title={Pb phase coarsening in eutectic Pb/Sn flip chip solder joints under electric current stressing}, volume={41}, ISSN={0020-7683}, url={http://dx.doi.org/10.1016/j.ijsolstr.2003.12.001}, DOI={10.1016/j.ijsolstr.2003.12.001}, abstractNote={Experimental research on the Pb phase coarsening of eutectic Pb/Sn flip chip solder joint under current stressing is reported. Phase growth is observed under different current densities and temperatures. Higher current density leads to faster grain coarsening. Based on the test results, a grain coarsening equation including the influence of current density is proposed, dn−d0n=Kjmt. The current density exponent m is found to be 3, and phase growth exponent n is 5.5. Within our test temperature range, electric current seems to have a greater influence on Pb phase growth of the solder joint than temperature or thermomigration caused by the temperature gradient due to Joule heating during current stressing.}, number={9-10}, journal={International Journal of Solids and Structures}, publisher={Elsevier BV}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2004}, month={May}, pages={2743–2755} }
 @inproceedings{hopkins_2004, title={Power Packaging Techniques and High Current Applications}, booktitle={19th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2004}, month={Feb} }
 @article{ye_basaran_hopkins_2003, title={Damage mechanics of microelectronics solder joints under high current densities}, volume={40}, ISSN={0020-7683}, url={http://dx.doi.org/10.1016/s0020-7683(03)00175-6}, DOI={10.1016/s0020-7683(03)00175-6}, abstractNote={The electromigration damage in flip chip solder joints of eutectic SnPb was studied under current stressing at room temperature with a current density of 1.3 × 104 A/cm2. The height of the solder joints was 100 μm. The mass accumulation near anode side and void nucleation near cathode were observed during current stressing. The nano-indentation test was performed on solder joints for electromigration test. Surface marker movement was used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity, D×Z∗, of the solder at room temperature. The effective charge number can be extracted with the solder diffusivity at room temperature known. Pb phase coarsening was observed during current stressing.}, number={15}, journal={International Journal of Solids and Structures}, publisher={Elsevier BV}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2003}, month={Jul}, pages={4021–4032} }
 @article{ye_basaran_hopkins_liu_cartright_2003, title={Flip Chip and BGA Solder Joint Reliability}, volume={12}, number={5}, journal={Advanced Packaging}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C. and Liu, Heng and Cartright, Alexander}, year={2003}, month={May}, pages={17–19} }
 @article{ye_hopkins_basaran_2003, title={Measurement of Electrical Current Density Effects in Solder Joints}, volume={30}, number={5}, journal={Advancing Microelectronics}, author={Ye, Hua and Hopkins, Douglas C. and Basaran, Cemal}, year={2003}, month={Sep} }
 @article{ye_hopkins_basaran_2003, title={Measurement of high electrical current density effects in solder joints}, volume={43}, ISSN={0026-2714}, url={http://dx.doi.org/10.1016/s0026-2714(03)00131-8}, DOI={10.1016/s0026-2714(03)00131-8}, abstractNote={Measuring mechanical implications of high current densities in microelectronic packaging interconnects has always been a challenging goal. Due to small interconnect size this task has typically been accomplished by measuring the change in electrical resistance of the joint. This measurement parameter is global and does not give local mechanical state information. Also, understanding strain evolution in the solder over time is an important step toward developing a damage mechanics model. The real-time, full-field, strain displacement in a eutectic Sn/Pb solder joint during electrical current stressing was measured with Moiré interferometry (Post et al., High sensitivity Moire, Springer, New York, 1994) under in situ conditions. A finite element model simulation for thermal stressing was performed and compared with measured strain. The initial results show that the measured strain was largely due to thermal stressing versus the current density of 1.8 × 102 A/cm2. A second Moiré interferometry experiment with thermal control distinguishes deformation of solder joint due to pure current stressing above 5000 A/cm2.}, number={12}, journal={Microelectronics Reliability}, publisher={Elsevier BV}, author={Ye, Hua and Hopkins, Douglas C. and Basaran, Cemal}, year={2003}, month={Dec}, pages={2021–2029} }
 @article{ye_basaran_hopkins_2003, title={Measuring Joint Reliability: Applying the Moire Interferometry Technique}, volume={12}, number={5}, journal={Advanced Microelectronics Magazine}, author={Ye, H. and Basaran, C. and Hopkins, D.C.}, year={2003}, month={May}, pages={17–20} }
 @article{ye_basaran_hopkins_2003, title={Mechanical degradation of microelectronics solder joints under current stressing}, volume={40}, ISSN={0020-7683}, url={http://dx.doi.org/10.1016/j.ijsolstr.2003.08.019}, DOI={10.1016/j.ijsolstr.2003.08.019}, abstractNote={Understanding the mechanical degradation of microelectronic solder joints under high electric current stressing is an important step to develop a damage mechanics model in order to predict the reliability of a solder joint under such loading. In this paper, the experiment results for flip chip solder joints under high current stressing are reported. Nano-indentation tests suggest that mechanical property, e.g. Young’s modulus, degrades in the localized area where void nucleates during current stressing. The experiments also show that thermomigration due to the thermal gradient within solder joint caused by joule heating is significant during current stressing. A three-dimensional coupled thermal electrical finite element analysis shows the existence of a significant thermal gradient in solder joint during current stressing.}, number={26}, journal={International Journal of Solids and Structures}, publisher={Elsevier BV}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas C.}, year={2003}, month={Dec}, pages={7269–7284} }
 @article{ye_basaran_hopkins_2003, title={Numerical simulation of stress evolution during electromigration in IC interconnect lines}, volume={26}, ISSN={1521-3331}, url={http://dx.doi.org/10.1109/tcapt.2003.817877}, DOI={10.1109/tcapt.2003.817877}, abstractNote={A finite element simulation of stress evolution in thin metal film during electromigration is reported in this paper. The electromigration process is modeled by a coupled diffusion- mechanical partial differential equations (PDEs). The PDEs are implemented with a plane strain formulation and numerically solved with the finite element (FE) method. The evolutions of hydrostatic stress, each component of the deviatoric stress tensor, and Von Mises' stress were simulated for several cases with different line lengths and current densities. Two types of displacement boundary conditions are considered. The simulation results are compared with Korhonen's analytical model and Black and Blech's experimentalesults.}, number={3}, journal={IEEE Transactions on Components and Packaging Technologies}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Ye, Hua and Basaran, C. and Hopkins, D.C.}, year={2003}, month={Sep}, pages={673–681} }
 @inproceedings{hopkins_moronski_2003, title={Partitioning digitally programmable power-control for applications to ballasts}, ISBN={0780374045}, url={http://dx.doi.org/10.1109/apec.2002.989356}, DOI={10.1109/apec.2002.989356}, abstractNote={The move to full digital control of power electronic circuits has been mixed. This paper describes the procession of technology to embed digital power control in power supply circuits, with particular attention to dimmable fluorescent lighting ballasts. Partitioning of power circuits shows a near optimum match with the evolving system on chip (SoC) approach taken for microcontrollers to provide an integrated digital power control. A performance description of several approaches is given with performance bounds.}, booktitle={APEC. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.02CH37335)}, publisher={IEEE}, author={Hopkins, D.C. and Moronski, J.}, year={2003}, month={Jun} }
 @inproceedings{hopkins_2003, place={Miami, Beach, FL}, title={Power Packaging Techniques with Emphasis on High Current Applications}, booktitle={18th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={2003}, month={Feb} }
 @inproceedings{ye_basaran_hopkins_cartwright_2003, title={Reliability of solder joints under electrical stressing - strain evolution of solder joints}, ISBN={0780371526}, url={http://dx.doi.org/10.1109/itherm.2002.1012558}, DOI={10.1109/itherm.2002.1012558}, abstractNote={Damage mechanics of solder interconnects under electrical stressing is an important reliability issue for next generation power electronic packaging as well as for future IC packaging. The high electrical stressing in solder joints leads to electromigration and thus could not be ignored. In this paper, the state-of-the-art research on electromigration in solder joints is reviewed. An experimental electromigration study on solder joints is conducted and results are reported in this paper. The strain field in the solder joints under electrical stressing is measured with Moire Interferometry technique.}, booktitle={ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)}, publisher={IEEE}, author={Ye, Hua and Basaran, C. and Hopkins, D. and Cartwright, A.}, year={2003}, month={Jun} }
 @article{ye_basaran_hopkins_2003, title={Thermomigration in Pb–Sn solder joints under joule heating during electric current stressing}, volume={82}, ISSN={0003-6951 1077-3118}, url={http://dx.doi.org/10.1063/1.1554775}, DOI={10.1063/1.1554775}, abstractNote={Electromigration of solder joint under high dc current density is known as a reliability concern for the future high-density flip chip packaging and power packaging. Biased mass diffusion within solder joint from cathode to anode under high dc current density is observed in these experiments. In this letter, the experiments on flip chip solder joints under dc current stressing are conducted and thermomigration due to the thermal gradient in the solder joint caused by joule heating is reported. A three-dimensional coupled electric thermal finite-element (FE) simulation of a realistic flip chip module shows the existence of thermal gradient in the solder joint which is high enough to trigger thermomigration.}, number={7}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas}, year={2003}, month={Feb}, pages={1045–1047} }
 @inproceedings{52nd electronic components and technology conference 2002. (cat. no.02ch37345)_2002, url={http://dx.doi.org/10.1109/ECTC.2002.1008063}, DOI={10.1109/ECTC.2002.1008063}, abstractNote={The following topics are dealt with: Ethernet and WDM technology; package electrical characterization; flip chip packaging; solder technology; reliability and test; modules; materials, transceivers and interconnects; power and EM modeling; flip-chip underfills; reliability and stress; integrated and on-chip passives; reliability and integration; package assembly modeling; process development and characterization for high density interconnects; packaging education; low cost optical packaging; dielectric, adhesive and underfill delamination and modeling; wire bonding and interconnections; substrates and dielectrics; failure analysis; RF devices and RF MEMS; interconnect modeling and characterization; electrically conductive adhesives; wafer level processing and test; Pb-free flip chip; Pb-free solder reliability; failure prediction and modeling; chip-scale and wafer-level packaging; high density and 3D interconnects; array interconnect manufacturing technology; Web-based packaging education.}, booktitle={52nd Electronic Components and Technology Conference 2002 (Cat No 02CH37345) ECTC-02}, publisher={IEEE}, year={2002} }
 @inproceedings{hopkins_mathuna_alderman_flannery_2002, title={A framework for developing power electronics packaging}, ISBN={0780343409}, url={http://dx.doi.org/10.1109/apec.1998.647663}, DOI={10.1109/apec.1998.647663}, abstractNote={As the integration of electro-physical circuits increases, many physical components and topologies are either directly or indirectly determined by the electrical designer. This paper presents a packaging technology framework for designers to better understand, evaluate and communicate the technical needs for a 'physical circuit'. The framework goes further in proposing a systematic method to link technical power packaging issues to user requirements as the basis for developing a power electronics technology roadmap. This paper presents the framework as a three-dimensional coordinate of user requirements, levels of packaging and interfaces and pathways, cross-cut by a fourth dimension of energy forms. Examples assist the reader in understanding the framework and appreciating the potential for application of the framework in the future developments of power electronics packaging.}, booktitle={APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition}, publisher={IEEE}, author={Hopkins, D.C. and Mathuna, S.C.O. and Alderman, A.N. and Flannery, J.}, year={2002}, month={Nov} }
 @inproceedings{craig_hopkins_driscoll_2002, title={A high speed pulser thyristor}, ISBN={0780343409}, url={http://dx.doi.org/10.1109/apec.1998.653980}, DOI={10.1109/apec.1998.653980}, abstractNote={A pulse power thyristor (PPT), has features optimized for pulse power applications: high di/dt, compact size and high current densities >10/sup 4/ A/cm/sup 2/. These features are enabled by enhancing the turn-on mechanism through field aided drift and a very high level of gate-cathode interdigitation. The technology allows high blocking voltage >5 kV in small, low cost packages. The device described in this paper is optimized for turn-on and, as such, is labeled a pulse power closing switch thyristor (PPCST). The device structure is briefly discussed along with details of field aided drift as a critical dynamic mechanism. A trade-off for fast turn-on shows that the dynamic resistance and leakage currents are higher than typical thyristors. A major attribute of the device design is to self limit the anode di/dt without self-destruction or having the requirement for series inductors. A dynamic test circuit was developed with the potential of greater than 110 kA//spl mu/s. Test results show that the di/dt is limited by the PPCST and not inductance. The current rise from 10% to 90% occurs within 260 ns to a peak current of 4.85 kA to yield a di/dt of 14.9 kA//spl mu/s. The 10% to 70% rise yields better than 20 kA//spl mu/s. During rapid di/dt of anode current the gate-to-cathode voltage became excessive. There, also, was an indication of possible current flow out of the gate during the same interval. Thus, an ultra-fast constant-current gate drive circuit was developed. The drive delivered 0 to 30 A in <400 ns and maintained the 30 A during the entire turn on interval. The excessive voltage was due to 5 nH of internal package inductance.}, booktitle={APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition}, publisher={IEEE}, author={Craig, A.H. and Hopkins, D.C. and Driscoll, J.C.}, year={2002}, month={Nov} }
 @inproceedings{hopkins_bowers_2002, title={Characterization of advanced materials for high voltage/high temperature power electronics packaging}, ISBN={0780366182}, url={http://dx.doi.org/10.1109/apec.2001.912498}, DOI={10.1109/apec.2001.912498}, abstractNote={To achieve high reliability in next generation dense, high voltage (>1 kV DC), high temperature (200/spl deg/C to 400/spl deg/C) power electronic circuits, packaging techniques from higher voltage systems (5 kV-50 kV) need to be introduced. This paper describes advanced materials, measurement and characterization techniques for this class of systems. These systems are being developed for commercial, industrial and military applications that include supplies, drives and actuators. The results are applicable to 1200 V+IGBT based module designs.}, booktitle={APEC 2001. Sixteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.01CH37181)}, publisher={IEEE}, author={Hopkins, D.C. and Bowers, J.S.}, year={2002}, month={Nov} }
 @inproceedings{ye_basaran_hopkins_2002, place={SPIE}, title={Experimental Study on Reliability of Solder Joints under Electrical Stressing -Nano-indentation, Atomic Flux Measurement}, volume={4828}, booktitle={SPIE proceedings series}, publisher={Bellingham, Washington}, author={Ye, H. and Basaran, C. and Hopkins, D.}, year={2002}, pages={231–236} }
 @inproceedings{ye_hopkins_basaran_2002, title={Measurement and Effects of High Electrical Current Stress in Solder Joints}, booktitle={Proceedings of the 35th International Symposium on Microelectronics}, author={Ye, H. and Hopkins, D.C. and Basaran, C.}, year={2002}, pages={427–432} }
 @inproceedings{ye_basaran_hopkins_2002, title={Mechanical Implications of High Current Densities in Flip Chip Solder Joints}, ISBN={0791836487}, url={http://dx.doi.org/10.1115/imece2002-33650}, DOI={10.1115/imece2002-33650}, abstractNote={The electromigration damage in flip chip solder joints of eutectic SnPb was studied under current stressing at room temperature with the current density about 1.3×104A/cm2. The diameter of the solder joints was about 140μm. The mass accumulation near anode side and void nucleation near cathode were observed during current stressing. The nano-indentation test was first time done on solder joints for electromigration test. Surface marker movement was used to measure the atomic flux driven by electromigration and to calculate the product of effective charge number and diffusivity, DxZ*, of the solder at room temperature. The effective charge number can be extracted with the solder diffusivity at room temperature known.}, booktitle={Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology}, publisher={ASMEDC}, author={Ye, Hua and Basaran, Cemal and Hopkins, Douglas}, year={2002}, month={Jan} }
 @inproceedings{jacobsen_hopkins_2002, title={Optimally selecting packaging technologies and circuit partitions based on cost and performance}, ISBN={0780358643}, url={http://dx.doi.org/10.1109/apec.2000.826079}, DOI={10.1109/apec.2000.826079}, abstractNote={Most power electronics circuits are packaged using two or more power electronics packaging technologies. To optimally select and use several technologies that meet performance requirements at minimum cost requires a strategic partitioning of the circuit. Presented is a structured technique for optimally selecting technologies based on a relative cost diagram. Other factors, such as performance, product volume and modularity are included.}, booktitle={APEC 2000. Fifteenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.00CH37058)}, publisher={IEEE}, author={Jacobsen, J.B. and Hopkins, D.C.}, year={2002}, month={Nov} }
 @inproceedings{bowers_hopkins_sarjeant_2002, title={Packaging issues for next generation high voltage, high temperature power electronic modules}, ISBN={0780337042}, url={http://dx.doi.org/10.1109/apec.1997.581483}, DOI={10.1109/apec.1997.581483}, abstractNote={This paper describes packaging issues related to the next generation of high voltage (>2 kV), high temperature (200/spl deg/C to 400/spl deg/C) power electronic modules that are being developed for military, commercial and industrial applications. These applications include space, nuclear power and down-hole systems. Components, materials and processes are considered. Effects due to variations in thickness of the copper interconnect, ceramic substrate and heat spreader (baseplate) are investigated to predict the effects of thermally induced stresses. Thinner ceramic layers provide a significant increase in the thermal conductance and lower thermally induced stresses during system operation.}, booktitle={Proceedings of APEC 97 - Applied Power Electronics Conference}, publisher={IEEE}, author={Bowers, J.S. and Hopkins, D.C. and Sarjeant, W.J.}, year={2002}, month={Nov} }
 @inproceedings{hopkins_bowers_2002, title={Power Packaging Techniques for Low and Higher Voltage Systems}, booktitle={17th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C. and Bowers, John S.}, year={2002}, month={Mar} }
 @inproceedings{bowers_hopkins_sarjeant_2002, title={Power packaging of a 12 kV, 240°C passive electronic module}, ISBN={0780343409}, url={http://dx.doi.org/10.1109/apec.1998.647736}, DOI={10.1109/apec.1998.647736}, abstractNote={This paper describes packaging design issues related to a high voltage (12 kV), high temperature (240/spl deg/C) power electronic module developed for military, commercial, and industrial applications. Designs guides are given for materials and qualification of components.}, booktitle={APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition}, publisher={IEEE}, author={Bowers, J.S. and Hopkins, D.C. and Sarjeant, W.J.}, year={2002}, month={Nov} }
 @inproceedings{hopkins_root_2002, title={Synthesis of a new class of converters that utilize energy recirculation}, ISBN={0780318595}, url={http://dx.doi.org/10.1109/pesc.1994.373830}, DOI={10.1109/pesc.1994.373830}, abstractNote={A new class of switchmode power electronic circuit topologies, named energy recirculation and storage circuits (ERSCs), are described which have the characteristic of storing and recirculating energy in a return path to augment the source. A port reduction technique is developed which connects output to input and is applied to buck and boost derived converters. A description of circuit operation is given for an ideal boost/buck ERSC. Two possible applications for ERSCs are for in-situ testing of power devices and for power factor correction. The second utilizes a cascaded boost/buck ERSC as an output-regulated power-factor correction (PFC) circuit. The PFC-ERSC is evaluated and a detailed description with key equations included.<<ETX>>}, booktitle={Proceedings of 1994 Power Electronics Specialist Conference - PESC'94}, publisher={IEEE}, author={Hopkins, D.C. and Root, D.W.}, year={2002}, month={Dec} }
 @inbook{hopkins_2001, place={San Diego, CA}, title={Packaging and Smart Power Systems}, booktitle={Power electronics handbook}, publisher={Academic Press}, author={Hopkins, D.C.}, editor={Rashid, M.H.Editor}, year={2001} }
 @inproceedings{hopkins_bowers_2001, title={Power Packaging Techniques for Low and Higher Voltage Systems}, booktitle={16th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C. and Bowers, John S.}, year={2001}, month={Mar} }
 @inproceedings{bowers_hopkins_sarjeant_2000, title={Packaging Factors for Next Generation High Voltage, High Temperature Power Electrons Modules}, author={Bowers, J.S. and Hopkins, D.C. and Sarjeant, W.J.}, year={2000}, month={Jul} }
 @inproceedings{hopkins_1999, title={Power Electronics Packaging}, booktitle={14th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={1999}, month={Mar} }
 @inproceedings{hopkins_o’mathuna_alderman_1998, title={A Four-Dimensional Road-Mapping Framework for Power Packaging Technology}, booktitle={Proceedings of the 1998 IMAPS International Symposium on Microelectronics}, author={Hopkins, D. C. and O’Mathuna, S. C. and Alderman, A.N.}, year={1998} }
 @article{hopkins_pitarressi_karker_1998, title={Systems Design Considerations for Using a Direct-Attached-Ceramic MMC Power Package}, journal={international journal on microelectronics reliability}, author={Hopkins, D.C. and Pitarressi, J.M. and Karker, J.A.}, year={1998} }
 @article{hopkins_pitarressi_1998, title={Thermal Impedance and Induced Stress in a Power Package Due to Variation in Layer Thickness}, journal={International Journal of Microcircuits and Electronic Packaging}, author={Hopkins, D.C. and Pitarressi, J.M.}, year={1998} }
 @article{hopkins_1997, place={Reston, VA}, title={Power Electronics Packaging}, volume={24}, number={1}, journal={Advancing Microelectronics Magazine}, publisher={International Microelectronics and Packaging Society}, author={Hopkins, D.C.}, year={1997}, month={Jan}, pages={10} }
 @inproceedings{hopkins_1997, title={Power Electronics Packaging - A Circuit Design Approach}, booktitle={12th Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)}, author={Hopkins, Douglas C.}, year={1997}, month={Feb} }
 @inproceedings{hopkins_pitarressi_karker_1997, place={SPIE}, title={Thermal Impedance and Stress in a Power Package Due to Variations in Layer Thickness}, volume={3235}, booktitle={SPIE Proceedings Series}, publisher={Bellingham, Washington}, author={Hopkins, D.C. and Pitarressi, J.M. and Karker, J.A.}, year={1997}, month={Oct}, pages={72–77} }
 @book{hopkins_1996, title={High Temperature Capacitors}, institution={Custom Electronics Inc}, author={Hopkins, D.C.}, year={1996}, month={Apr} }
 @book{hopkins_1996, title={Investigation of a Power Package Incorporating a Direct Attached Ceramic/AlSiC Structure}, institution={BrushWellman Incorporated}, author={Hopkins, D.C.}, year={1996}, month={Jan} }
 @inproceedings{hopkins_pitarressi_fridline_karker_1996, title={System Design Considerations for using a Direct–Attached–Ceramic MMC Power Package}, booktitle={Proceedings of 32nd International Power Conversion Conference}, author={Hopkins, D.C. and Pitarressi, J.M. and Fridline, D.R. and Karker, J.A.}, year={1996}, pages={683–690} }
 @book{hopkins_1995, title={Assessment of the Power Conversion Thrust Area}, institution={Lawrence Livermore National Laboratory}, author={Hopkins, D.C.}, year={1995}, month={Jul} }
 @book{hopkins_1995, title={Cost Estimate for the ARM Electronic Circuit Cards}, institution={Lawrence Livermore National Laboratory}, author={Hopkins, D.C.}, year={1995}, month={Nov} }
 @inproceedings{hopkins_sarkar_1994, title={A mathematical approach to minimize the total mass of a space based power system by using multivariable non-linear optimization}, url={http://dx.doi.org/10.2514/6.1994-3807}, DOI={10.2514/6.1994-3807}, abstractNote={Many space-based and aircraft-based electrical power systems must share electrical sources either for redundancy or because of excessive scheduled load capacity. The design of these shared resource systems, particularly in early design phases, is very difficult. A tool to assist designers in a what-if evaluation of an optimum system design which matches multiple sources to multiple loads for a given bus architecture would be very valuable. The optimization would minimize monetary cost which includes minimizing mass. The work reported here describes the approach to developing a proof-ofconcept of such a tool and focuses on possible optimization algorithms.}, booktitle={Intersociety Energy Conversion Engineering Conference}, publisher={American Institute of Aeronautics and Astronautics}, author={Hopkins, Douglas and Sarkar, Madhushree}, year={1994}, month={Aug} }
 @inproceedings{hopkins_revis_1994, title={Development of a Three Dimensional Power Circuit Package for Aircraft Applications}, booktitle={1994 Proceedings: International Symposium on Microelectronics}, author={Hopkins, D.C. and Revis, R.}, year={1994}, pages={124–128} }
 @article{hopkins_bhavnani_1994, title={Optimizing Conductor Thickness in Power Hybrid Circuits}, number={3rd Quarter}, journal={International Journal of Microcircuits and Electronic Packaging}, author={Hopkins, D.C. and Bhavnani, S.H.}, year={1994}, pages={293–301} }
 @inproceedings{hopkins_bhavnani_1993, title={Determining Conductor Thickness in Power Circuits that Operate at Long Wavelength Frequencies}, booktitle={Proceedings of the 1993 ISHM Intternational Symposium on Microelectronics}, author={Hopkins, D.C. and Bhavnani, S.H.}, year={1993}, pages={656–661} }
 @article{hopkins_mosling_hung_1993, title={Dynamic equalization during charging of serial energy storage elements}, volume={29}, ISSN={0093-9994}, url={http://dx.doi.org/10.1109/28.216545}, DOI={10.1109/28.216545}, abstractNote={A technique is described that equalizes the amount of charge in a serial string of energy-storage cells during charging by using DC-to-DC converters to divert portions of the charging current past selected cells (or groups of cells). When no converters are operating, the charging current through the string is equal to that of the charging source. As the string charges, one cell eventually reaches a threshold voltage V/sub A/. At threshold, a shunt converter is activated to divert current around the cell, thus maintaining it at V/sub A/. The diverted current extracts energy, which is returned to the charging bus and appears as an additional charging current to the source. This positive feedback increases the current available for charging the string and allows the least charged cells, or cells of larger capacity, to be charged at higher rates than available directly from the source. During discharging, the converters across the remaining cells supply energy to the bus, while the converter across the open cell maintains a constant terminal voltage. The maximum current gain of the system is equal to the number of converters used in the system. >}, number={2}, journal={IEEE Transactions on Industry Applications}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hopkins, D.C. and Mosling, C.R. and Hung, S.T.}, year={1993}, pages={363–368} }
 @article{hopkins_bhavnani_dalal_1993, title={Effect of Metallization Thickness on Thermal Conductance of a First-Level Power Hybrid Structure}, number={2nd Quarter}, journal={International Journal of Microcircuits and Electronic Packaging}, author={Hopkins, D.C. and Bhavnani, S.H. and Dalal, K.H.}, year={1993}, pages={189–193} }
 @article{hung_hopkins_mosling_1993, title={Extension of battery life via charge equalization control}, volume={40}, ISSN={0278-0046}, url={http://dx.doi.org/10.1109/41.184826}, DOI={10.1109/41.184826}, abstractNote={The primary difficulty in charging storage batteries is in attaining process regulation that allows fast charging while avoiding destructive overcharging. A two-level approach to controlling the charging process is presented. A general background discussion of batteries and charging problems is followed by the presentation of a novel recirculating charge equalization technique that enhances the uniformity of batteries made up from long serial strings of cells. A straightforward means of embedding equalization within an outer-loop supervisory control that maintains a fast charging rate while providing overall protection against overcharging is briefly described. Simulation and experimental results confirm the applicability of the equalization control technique. >}, number={1}, journal={IEEE Transactions on Industrial Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hung, S.T. and Hopkins, D.C. and Mosling, C.R.}, year={1993}, pages={96–104} }
 @book{hopkins_1993, title={High Density Shunt Regulator Development}, institution={Martin Marietta Corporation}, author={Hopkins, D.C.}, year={1993}, month={Dec} }
 @book{hopkins_1993, title={Investigation of High Frequency Resonant Effects in Batteries}, institution={NASA Lewis Research Center}, author={Hopkins, D.C.}, year={1993}, month={Aug} }
 @book{hopkins_1993, title={Systems Engineering of Shared Resources: Decision Support System for the Concept Definition Phases}, journal={NASA-OAI Collaborative Aerospace Research and Fellowship Program at Lewis Research Center}, institution={Lewis Research Center}, author={Hopkins, D.C.}, year={1993}, pages={25–26} }
 @book{systems engineering of shared resources: decision support for the concept design phase – modeling development_1993, institution={NASA Lewis Research Center}, year={1993}, month={Dec} }
 @book{hopkins_1992, title={Materials Support for the Investigation of Charge Equalization in Serial Batteries}, number={NAG8-123}, author={Hopkins, D.C.}, year={1992}, pages={VII–1 – VII-21} }
 @inproceedings{hopkins_bhavnani_dalal_1992, title={Numerical Modeling and Experimental Comparison of Copper Bonded AlN, Al2O3 and BeO Power Hybrid Structures}, booktitle={Proceedings of the 1992 International Electronics Packaging Conference}, author={Hopkins, D.C. and Bhavnani, S.H. and Dalal, K.H.}, year={1992} }
 @book{hopkins_1992, title={Power Measurement in Converters}, institution={NASA Lewis Research Center}, author={Hopkins, D.C.}, year={1992}, month={Aug} }
 @inproceedings{hopkins_bhavnani_dalal_1992, title={Thermal Performance Comparison and Metallurgy of Direct Copper Bonded AlN, Al2O3 and BeO Assemblies}, booktitle={Proceedings of the 1992 ISHM International Symposium on Microelectronics}, author={Hopkins, D.C. and Bhavnani, S.H. and Dalal, K.H.}, year={1992}, pages={577–583} }
 @book{hopkins_1991, title={Optimum Operating Temperature for a Minimum Mass Space Power System}, institution={NASA Lewis Research Center}, author={Hopkins, D.C.}, year={1991}, month={Aug} }
 @inproceedings{hopkins_mosling_hung_1991, title={The use of equalizing converters for serial charging of long battery strings}, ISBN={0780300246}, url={http://dx.doi.org/10.1109/apec.1991.146221}, DOI={10.1109/apec.1991.146221}, abstractNote={The authors present a technique that uses DC-DC converters to shunt energy from cells (or groups of cells) while the entire string of cells is being charged. The amount of charging of each cell can be controlled by varying the amount of diverted energy. The technique does not exclude the use of different capacity cells within the string nor exclude the use of different types of energy storage elements. If a cell fails, the converter across it will automatically regulate the voltage across the failed cell during charging and allow current to flow in the whole battery string. For energy discharge, the converters across the functional cells can be used in the traditional fashion with their outputs in parallel while the open-cell voltage is still maintained.<<ETX>>}, booktitle={[Proceedings] APEC '91: Sixth Annual Applied Power Electronics Conference and Exhibition}, publisher={IEEE}, author={Hopkins, D.C. and Mosling, C.R. and Hung, S.T.}, year={1991} }
 @book{hopkins_1990, title={Current Limiting Remote Power Control Module}, number={NGT-01-002-009}, institution={NASA Marshal Space Flight Center}, author={Hopkins, D.C.}, year={1990}, month={Sep} }
 @article{hopkins_1989, title={Designing Hybrid Power Supplies}, volume={5}, number={6}, journal={Powertechnics Magazine}, author={Hopkins, D.C.}, year={1989}, month={Jun}, pages={31–34} }
 @article{jovanovic_hopkins_lee_1989, title={Evaluation and design of megahertz-frequency off-line zero-current-switched quasi-resonant converters}, volume={4}, ISSN={0885-8993 1941-0107}, url={http://dx.doi.org/10.1109/63.21882}, DOI={10.1109/63.21882}, abstractNote={A performance comparison of flyback, forward, and half-bridge zero-current-switched quasi-resonant converter topologies for high-frequency offline applications is presented. It is shown that the half-bridge topology with secondary side resonance operating in half-wave mode is most suitable. A complete design procedure for the half-bridge power stage and the voltage-feedback control is presented together with experimental results for a 300 V DC hybridized converter which operates with conversion frequencies from 400 kHz to 2 MHz and delivers 1.5-16 A at 5 V DC. >}, number={1}, journal={IEEE Transactions on Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Jovanovic, M.M. and Hopkins, D.C. and Lee, F.C.Y.}, year={1989}, month={Jan}, pages={136–146} }
 @book{hopkins_1989, title={High Density Power Transformer}, institution={Unisys Corporation}, author={Hopkins, D.C.}, year={1989}, month={Dec} }
 @book{hopkins_lee_1989, title={High-Performance, High-Frequency, Distributed, Computer Power Supply Technology}, institution={Digital Equipment Corporation}, author={Hopkins, D.C. and Lee, F.C.}, year={1989}, month={Jun} }
 @article{hopkins_jovanovic_lee_stephenson_1989, title={Hybridized off-line 2-MHz zero-current-switched quasi-resonant converter}, volume={4}, ISSN={0885-8993 1941-0107}, url={http://dx.doi.org/10.1109/63.21883}, DOI={10.1109/63.21883}, abstractNote={Thick-film hybrid technology is used to develop a half-bridge, half-wave, zero-current-switched quasi-resonant converter for 300 V DC offline application. With a conversion frequency of 2 MHz the converter delivers 80 W at 78% efficiency with a power density, excluding heat sink, of 21 W/in/sup 3/. The operation and detailed electrical and hybrid design of the circuit are described. Also described is a 2 MHz hybridized gate drive. >}, number={1}, journal={IEEE Transactions on Power Electronics}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Hopkins, D.C. and Jovanovic, M.M. and Lee, F.C.Y. and Stephenson, F.W.}, year={1989}, month={Jan}, pages={147–154} }
 @article{johnson_weeks_hopkins_muir_williams_1989, title={Plated copper on ceramic substrates for power hybrid circuits}, volume={12}, ISSN={0148-6411}, url={http://dx.doi.org/10.1109/33.49011}, DOI={10.1109/33.49011}, abstractNote={Plated copper on ceramic has been evaluated for fabrication of power hybrid circuits. The copper is plated using a semiadditive process that yields rectangular conductor cross sections. Copper thicknesses can be varied from 12 to 150 mu m depending on electrical current requirements. Typically, a 2.5- mu m nickel barrier layer and a 1.25- mu m gold layer are plated onto the copper metallization. The soldered adhesion (62Sn/36Pb/2Ag) of the metallization has been studied. No adhesion degradation was observed after storage for 1000 h at 150 degrees C or after 118 thermal cycles between -65 degrees C and 125 degrees C. The bonding of small-diameter gold-wire bonding to the Au/Ni/Cu metallization was evaluated. No reduction in bond strength ( approximately=7.5 gf) was observed after 1000 h of storage at 150 degrees C. The bonding of large-diameter aluminium wire to the Au/Ni/Cu metallization was also studied. The average initial pull strength was 560 gf. After 2050 h at 150 degrees C, the average pull strength was 499 gf, while the average after 2050 h at 200 degrees C was 438 gf. Screen printable polyimide encapsulants were used for solder masking and high voltage insulation. Electrical properties were measured. To demonstrate the use of plated copper on ceramic, the power section of a 100-W DC-DC converter was fabricated. >}, number={4}, journal={IEEE Transactions on Components, Hybrids, and Manufacturing Technology}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Johnson, R.W. and Weeks, R. and Hopkins, D.C. and Muir, J. and Williams, J.R.}, year={1989}, pages={530–536} }
 @inproceedings{hopkins_jovanovic_lee_stephenson_1989, title={Power-Hybrid Design of a High-Frequency ZCS-QRC}, booktitle={Proceedings of the Fourth Annual High Frequency Power Conversion Conference}, author={Hopkins, D.C. and Jovanovic, M.M. and Lee, F.C. and Stephenson, F.W.}, year={1989}, pages={304–317} }
 @book{hopkins_1989, title={Testing of High Power Devices}, number={LABCOM-ETDL, DAAL03-86-D-001, DO 1576}, institution={U.S. Army}, author={Hopkins, D.C.}, year={1989}, month={Sep} }
 @inproceedings{hopkins_1989, title={The Effects of Power Hybridization on Power Electronic Circuits}, booktitle={ISHM International Symposium on Microelectronics Proceedings}, author={Hopkins, D.C.}, year={1989}, month={Oct}, pages={647–654} }
 @inproceedings{johnson_hopkins_jaeger_1989, title={The Microelectronics Program at Auburn University}, booktitle={ISHM International Symposium on Microelectronics Proceedings}, author={Johnson, R.W. and Hopkins, D.C. and Jaeger, R.C.}, year={1989}, month={Oct}, pages={367–375} }
 @article{hopkins_1989, title={Thick-Film Technique Helps Hybridized, 2 MHz ZC-QR Converter Achieve 78% Efficiency}, volume={15}, number={7}, journal={Power Conversion & Intelligent Motion}, author={Hopkins, D.C.}, year={1989}, month={Jul}, pages={57–66} }
 @inproceedings{hopkins_1989, title={Thick-film power hybridization of switchmode power circuits}, url={http://dx.doi.org/10.1109/apec.1989.36977}, DOI={10.1109/apec.1989.36977}, abstractNote={To help the electrical circuit designer better understand what is involved in a hybrid circuit design and to aid the designer hybrid-compatible circuits, the author presents a tutorial on the design of a power hybrid circuit. The structure of a power hybrid circuit is given along with the device's material properties and dimensions. Thick film and copper-on-ceramic techniques are presented. The designer can use the information to understand both the electrical and thermal limitations of such circuits. An example of a 2 MHz, off-line, thick-film-hybrid DC-DC-converter is provided.<<ETX>>}, booktitle={Proceedings, Fourth Annual IEEE Applied Power Electronics Conference and Exposition}, publisher={IEEE}, author={Hopkins, D.C.}, year={1989} }
 @inproceedings{hopkins_stephenson_lee_1988, title={Determination of Conductor Thickness and Width for Power-Hybrid Circuits}, booktitle={Proceedings of the Sixth Annual Power Electronics Seminar}, author={Hopkins, D.C. and Stephenson, F.W. and Lee, F.C.}, year={1988}, pages={71–83} }
 @phdthesis{hopkins_1988, title={Development of a High-Density, Off-Line, Quasi-Resonant Converter Using Hybrid Techniques}, school={Virginia Polytechnic Institute and State University}, author={Hopkins, D.C.}, year={1988} }
 @book{hopkins_lee_1988, title={High-Performance, High-Frequency, Distributed, Computer Power Supply Technology}, institution={Digital Equipment Corporation}, author={Hopkins, D.C. and Lee, F.C.}, year={1988}, month={Feb} }
 @inproceedings{hopkins_stephenson_lee_1988, title={Off-Line ZCS-QRC Thick-Film Hybrid Circuit}, booktitle={Proceedings of the Sixth Annual Power Electronics Seminar}, author={Hopkins, D.C. and Stephenson, F.W. and Lee, F.C.}, year={1988}, pages={71–83} }
 @inproceedings{hopkins_stephenson_lee_1988, title={Printing of Thick Thick-Film Conductors for Power Hybrid Circuits}, booktitle={ISHM International Symposium on Microelectronics Proceedings}, author={Hopkins, D.C. and Stephenson, F.W. and Lee, F.C.}, year={1988}, month={Oct}, pages={95–101} }
 @inproceedings{jovanovic_hopkins_lee_1987, title={Design Aspects for High-Frequency Off-Line Quasi-Resonant Converter}, booktitle={Proceedings of the Second Annual High Frequency Power Conversion Conference}, author={Jovanovic, M.M. and Hopkins, D.C. and Lee, F.C.}, year={1987}, month={Apr}, pages={83–97} }
 @book{hopkins_lee_1987, title={High-Performance, High-Frequency, Distributed, Computer Power Supply Technology}, institution={Digital Equipment Corporation}, author={Hopkins, D.C. and Lee, F.C.}, year={1987}, month={Feb} }
 @inproceedings{hopkins_jovanovicm_lee_stephenson_1987, title={Two-megahertz off-line hybridized quasi-resonant converter}, url={http://dx.doi.org/10.1109/apec.1987.7067139}, DOI={10.1109/apec.1987.7067139}, abstractNote={Thick-film hybrid technology is employed to fabricate a zero-current-switched, half-bridge, quasi-resonant converter for 300V dc off-line application. With a conversion frequency of 2MHz the converter delivers 80W at a power density of 21W/cu.in. This paper describes the theory of operation, detailed design rules and benefits of hybridization. Also described is a 2MHz hybridized gate drive.}, booktitle={1987 IEEE Applied Power Electronics conference and Exposition}, publisher={IEEE}, author={Hopkins, D.C. and Jovanovicm, M.M. and Lee, F.C. and Stephenson, F.W.}, year={1987}, month={Mar} }
 @inproceedings{hopkins_jovanovic_stephenson_lee_1986, title={One-Megahertz, Off-Line Converter Hybridization}, booktitle={Proceedings of the Fourth Annual Power Electronics Seminar}, author={Hopkins, D.C. and Jovanovic, M.M. and Stephenson, F.W. and Lee, F.C.}, year={1986}, pages={134–148} }
 @book{hopkins_lee_1985, title={Evaluation of Semiconductor Devices for Electric and Hybrid Vehicles (EHV) AC-Drive Applications,}, number={JPL9950-1038}, institution={Department of Energy and Jet Propulsion Laboratory}, author={Hopkins, D.C. and Lee, F.C.}, year={1985}, month={May} }
 @book{hopkins_lee_1985, title={Very High Frequency Quasi-Resonant Converters for Use in High Density Power Supplies for Military Applications}, institution={Texas Instruments Inc}, author={Hopkins, D.C. and Lee, F.C.}, year={1985}, month={Dec} }
 @inproceedings{hopkins_1984, title={Status of Power Devices, IC's and Support Chips}, booktitle={Proceedings of the Second Annual Power Electronics Seminar}, author={Hopkins, D.C.}, year={1984}, pages={2–9} }
 @inproceedings{hopkins_1983, title={Status of Semiconductor Power Switching Devices}, booktitle={Proceedings of the First Annual Power Electronics Seminar}, author={Hopkins, D.C.}, year={1983}, pages={82–91} }
 @article{steigerwald_hopkins_1981, title={Characteristic Input Harmonics of DC-DC Converters and their Effect on Input Filter Design}, volume={IECI-28}, ISSN={0018-9421}, url={http://dx.doi.org/10.1109/tieci.1981.351029}, DOI={10.1109/tieci.1981.351029}, abstractNote={Design curves are presented from which the individual harmonics generated at the input to a dc-dc chopper can be determined. The effect of the chopper output ripple current on the input harmonics is included. These generalized curves can be used to determine the input filter component ratings as well as to compute the harmonics injected into the source. Using harmonic superposition, the input current and voltage waveforms as a function of time are determined and thus the peak voltages and current stresses are obtained. A practical example illustrates the use of the curves and serves to verify the analysis.}, number={2}, journal={IEEE Transactions on Industrial Electronics and Control Instrumentation}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Steigerwald, Robert L. and Hopkins, Douglas C.}, year={1981}, month={May}, pages={73–82} }
 @inproceedings{weeks_johnson_hopkins_muir_williams_1969, title={Plated copper on ceramic for power hybrid applications}, url={http://dx.doi.org/10.1109/ecc.1989.77803}, DOI={10.1109/ecc.1989.77803}, abstractNote={A technique for plating copper onto ceramic with top layers of nickel, gold, and/or solder is described. The adhesion mechanism of the copper is an interlocking of the film and ceramic surface to form a mechanical bond. Soldered adhesion of the copper did not degrade during high-temperature storage or thermal cycling. A nickel barrier between the plated copper and solder inhibits diffusion and intermetallic formation. Testing of small-diameter gold and large-diameter aluminum wire bonds after high-temperature storage demonstrated the reliability of wire bonding to the Cu/Ni/Au metallization. While a small percentage of bond lifts occurred among the aluminum-wire-bond samples stored at 200 degrees C, the bond strengths were high and there was no increase in series bond resistance. Preliminary evaluation of a screen-printable polyimide encapsulant revealed pinholes in the cured film. Alternate polyimide formulations are being evaluated. A 2-MHz, 100-W DC-DC converter was fabricated to demonstrate the use of plated copper on ceramic substrate technology.<<ETX>>}, booktitle={Proceedings., 39th Electronic Components Conference}, publisher={IEEE}, author={Weeks, R. and Johnson, R.W. and Hopkins, D. and Muir, J. and Williams, J.R.}, year={1969} }
 @inproceedings{ye_basaran_hopkins, title={Experimental Study on Reliability of Solder Joints under Electrical Stressing -Nano-indentation, Atomic Flux Measurement}, booktitle={IMAPS International Conference on Advanced Packaging Systems}, author={Ye, H. and Basaran, C. and Hopkins, Douglas C.} }
 @inproceedings{hopkins, place={Orlando, FL}, title={Introduction to 3D Power Electronics & Post-Silicon Device Packaging}, url={https://meridian.allenpress.com/imaps-am/article-pdf/40/4/1/2068365/amim-40-4.pdf}, booktitle={46th Symposium on Microelectronics (IMAPS 2013)}, author={Hopkins, Douglas C.} }
 @inproceedings{ye_basaran_hopkins, title={Pb Phase Growth in Eutectic Pb/Sn Flip Chip Solder Joint under Current Stressing”}, booktitle={Proceedings of 2003 Mechanics and Materials Conference}, author={Ye, H. and Basaran, C. and Hopkins, D.C.} }