@article{ouyang_tahir_lichtenwalner_yellen_2012, title={Origin of multiplexing capabilities of multifrequency magnetic ratchets}, volume={85}, number={4}, journal={Physical Review. E, Statistical, Nonlinear, and Soft Matter Physics}, author={Ouyang, Y. Y. and Tahir, M. A. and Lichtenwalner, D. J. and Yellen, B. B.}, year={2012} }
 @article{jur_wheeler_lichtenwalner_maria_johnson_2011, title={Epitaxial growth of lanthanide oxides La2O3 and Sc2O3 on GaN}, volume={98}, ISSN={["0003-6951"]}, DOI={10.1063/1.3541883}, abstractNote={Deposition of lanthanide oxides on GaN is investigated as a means to produce stable dielectric with good interface quality. Epitaxial growth of cubic ⟨111⟩-oriented Sc2O3 is observed on GaN [0001] with a lattice mismatch of 7.2%, whereas La2O3 growth, with a lattice mismatch of ∼21%, results in a mixed phase epitaxial film comprised of the bixbyite and hexagonal allotropes. Substantial roughening accompanies this mixed phase film. By inserting a thin Sc2O3 interfacial layer between La2O3 and GaN and a Sc2O3 capping layer, the crystal quality of the predominantly La2O3 layer is improved and the stack is stabilized against hydroxide formation under ambient conditions.}, number={4}, journal={APPLIED PHYSICS LETTERS}, author={Jur, Jesse S. and Wheeler, Virginia D. and Lichtenwalner, Daniel J. and Maria, Jon-Paul and Johnson, Mark A. L.}, year={2011}, month={Jan} }
 @article{lee_lichtenwalner_novak_misra_2011, title={Impact of AlTaO Dielectric Capping on Device Performance and Reliability for Advanced Metal Gate/High-k PMOS Application}, volume={58}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2011.2160064}, abstractNote={We have investigated the effect of ultrathin Al-Ta-based capping layers on HfO2 and experimentally demonstrated that, with proper Al and Ta composition, an AlTaO capping layer is a good candidate dielectric for PMOSFET devices. Lower threshold voltage and significantly improved mobility were observed with AlTaO capping without degrading the dielectric properties. The addition of Ta in an AlTaO structure produces d-states in the Al2O3 matrix, resulting in an additional VT shift toward the PMOS band edge. This AlTaO capping layer not only modulates the device VT suitably for PMOS applications but also retards Al diffusion through the HfO2 layer, preventing Al-caused mobility degradation. Furthermore, the incorporation of a capping layer can improve reliability characteristics during the negative bias stress.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Lee, Bongmook and Lichtenwalner, Daniel J. and Novak, Steven R. and Misra, Veena}, year={2011}, month={Sep}, pages={2928–2935} }
 @article{lee_novak_lichtenwalner_yang_misra_2011, title={Investigation of the Origin of V-T/V-FB Modulation by La2O3 Capping Layer Approaches for NMOS Application: Role of La Diffusion, Effect of Host High-k Layer, and Interface Properties}, volume={58}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2011.2159306}, abstractNote={The role of La<sub>2</sub>O<sub>3</sub> capping in the <i>VT</i>/<i>V</i><sub>FB</sub> shift with various high- <i>k</i> and metal gate electrodes was systematically investigated. It was found that the La concentration at the high-<i>k</i>/SiO<sub>2</sub> interface is mainly responsible for the <i>VT</i>/<i>V</i><sub>FB</sub> modulation in NMOS devices, whereas the effect of the host high-<i>k</i> and gate electrodes on <i>VT</i>/<i>V</i><sub>FB</sub> is minimal. A 400-mV shift in <i>VT</i> from the control HfO<sub>2</sub> device with minimal degradation in mobility was obtained when a La<sub>2</sub>O<sub>3</sub> layer was inserted between the high-<i>k</i> and SiO<sub>2</sub> layers. It was also found that the incorporation of La<sub>2</sub>O<sub>3</sub> in the dielectric stack improves device reliability in terms of breakdown and positive-bias temperature instability characteristics. The main key for the <i>V</i><sub>FB</sub> shift is the ability of La diffusion through the host high-<i>k</i> material.}, number={9}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Lee, Bongmook and Novak, Steven R. and Lichtenwalner, Daniel J. and Yang, Xiangyu and Misra, Veena}, year={2011}, month={Sep}, pages={3106–3115} }
 @article{yang_hoffmann_lichtenwalner_krim_kingon_2011, title={Resolution of the transfer direction of field-evaporated gold atoms for nanofabrication and microelectromechanical system applications}, volume={98}, number={4}, journal={Applied Physics Letters}, author={Yang, Z. and Hoffmann, S. and Lichtenwalner, D. J. and Krim, J. and Kingon, A. I.}, year={2011} }
 @article{suri_lichtenwalner_misra_2010, title={Interfacial self cleaning during atomic layer deposition and annealing of HfO2 films on native (100)-GaAs substrates}, volume={96}, ISSN={["0003-6951"]}, DOI={10.1063/1.3357422}, abstractNote={The reduction in native oxides on GaAs surface during atomic layer deposition (ALD) of HfO2 using tetrakis-dimethylamino-hafnium precursor was investigated using x-ray photoelectron spectroscopy. The role of the ALD growth temperature on the reaction between surface oxides and precursor was studied. Interfacial oxide reduction was found to be insignificant for ALD at 200 °C, while nearly complete for growth at 300 °C. During postdeposition annealing at 400 °C, any arsenic oxides present were found to decompose, resulting in an increase in the interfacial gallium oxides. Thus, control of the ALD process plays a large role in determining interface properties.}, number={11}, journal={APPLIED PHYSICS LETTERS}, author={Suri, Rahul and Lichtenwalner, Daniel J. and Misra, Veena}, year={2010}, month={Mar} }
 @article{jayanti_yang_lichtenwalner_misra_2010, title={Technique to improve performance of Al2O3 interpoly dielectric using a La2O3 interface scavenging layer for floating gate memory structures}, volume={96}, ISSN={["0003-6951"]}, DOI={10.1063/1.3355547}, abstractNote={A technique of scavenging the SiO2 interfacial layer (IL) to improve the electrical performance of Al2O3 as the interpoly dielectric for flash memories has been studied. Scavenging was performed by the reaction of a thin La2O3 layer with the native oxide to form a high-κ lanthanum silicate. Significant improvement in the charge trapping and leakage characteristics were obtained. Transmission electron microscopy analysis was done to corroborate the electrical results. Results show that seven orders of magnitude leakage reduction was achieved by the replacement of the SiO2 IL with a higher-κ dielectric LaSiO at the Si interface.}, number={9}, journal={APPLIED PHYSICS LETTERS}, author={Jayanti, Srikant and Yang, Xiangyu and Lichtenwalner, Daniel J. and Misra, Veena}, year={2010}, month={Mar} }
 @article{yang_lichtenwalner_morris_krim_kingon_2009, title={Comparison of Au and Au-Ni Alloys as Contact Materials for MEMS Switches}, volume={18}, ISSN={["1941-0158"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-67349128609&partnerID=MN8TOARS}, DOI={10.1109/JMEMS.2008.2010850}, abstractNote={This paper reports on a comparison of gold and gold-nickel alloys as contact materials for microelectromechanical systems (MEMS) switches. Pure gold is commonly used as the contact material in low-force metal-contact MEMS switches. The top two failure mechanisms of these switches are wear and stiction, which may be related to the material softness and the relatively high surface adhesion, respectively. Alloying gold with another metal introduces new processing options to strengthen the material against wear and reduce surface adhesion. In this paper, the properties of Au-Ni alloys were investigated as the lower contact electrode was controlled by adjusting the nickel content and thermal processing conditions. A unique and efficient switching degradation test was conducted on the alloy samples, using pure gold upper microcontacts. Solid-solution Au-Ni samples showed reduced wear rate but increased contact resistance, while two-phase Au-Ni (20 at.% Ni) showed a substantial improvement of switching reliability with only a small increase of contact resistance. Discussion of the effects of phase separation, surface topography, hardness, and electrical resistivity on contact resistance and switch degradation is also included.}, number={2}, journal={JOURNAL OF MICROELECTROMECHANICAL SYSTEMS}, author={Yang, Zhenyin and Lichtenwalner, Daniel J. and Morris, Arthur S., III and Krim, Jacqueline and Kingon, Angus I.}, year={2009}, month={Apr}, pages={287–295} }
 @article{lichtenwalner_misra_dhar_ryu_agarwal_2009, title={High-mobility enhancement-mode 4H-SiC lateral field-effect transistors utilizing atomic layer deposited Al2O3 gate dielectric}, volume={95}, ISSN={["1077-3118"]}, DOI={10.1063/1.3251076}, abstractNote={Lateral metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. The bilayer dielectric consists of thin nitrided SiO2 covered by 25 nm of Al2O3 deposited using atomic layer deposition. Field-effect mobility and threshold voltage (VT) vary with SiC nitric oxide (NO) anneal temperature. Peak mobility of 106 cm2/V⋅s was obtained with corresponding VT of 0.8 V. The peak mobility decreases to 61 cm2/V⋅s with a lower temperature NO anneal, while the VT increased to 1.4 V. Thus with proper gate engineering, high-mobility normally off MOSFET devices can be obtained, leading to higher-performance gate-controlled power devices.}, number={15}, journal={APPLIED PHYSICS LETTERS}, author={Lichtenwalner, Daniel J. and Misra, Veena and Dhar, Sarit and Ryu, Sei-Hyung and Agarwal, Anant}, year={2009}, month={Oct} }
 @inproceedings{lee_lee_kim_lichtenwalner_kingon_2009, title={Zn-Sn co-doping effect on crystallization and texturing characteristics of indium oxide thin films}, volume={10}, booktitle={Journal of Ceramic Processing Research}, author={Lee, H. Y. and Lee, J. H. and Kim, J. J. and Lichtenwalner, D. J. and Kingon, A. I.}, year={2009}, pages={S116–119} }
 @article{kirsch_sivasubramani_huang_young_quevedo-lopez_wen_alshareef_choi_park_freeman_et al._2008, title={Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning}, volume={92}, ISSN={["1077-3118"]}, DOI={10.1063/1.2890056}, abstractNote={An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).}, number={9}, journal={APPLIED PHYSICS LETTERS}, author={Kirsch, P. D. and Sivasubramani, P. and Huang, J. and Young, C. D. and Quevedo-Lopez, M. A. and Wen, H. C. and Alshareef, H. and Choi, K. and Park, C. S. and Freeman, K. and et al.}, year={2008}, month={Mar} }
 @article{lebeau_jur_lichtenwalner_craft_maria_kingon_klenov_cagnon_stemmer_2008, title={High temperature stability of Hf-based gate dielectric stacks with rare-earth oxide layers for threshold voltage control}, volume={92}, ISSN={0003-6951 1077-3118}, url={http://dx.doi.org/10.1063/1.2901036}, DOI={10.1063/1.2901036}, abstractNote={The thermal stability of DyOx∕HfSiON and HoOx∕HfSiON gate dielectric stacks on silicon was studied by scanning transmission electron microscopy techniques and correlated with their electrical characteristics. Intermixing of the rare-earth elements with the HfSiON was observed, but there was no diffusion into the interfacial SiO2. Rapid thermal annealing (1000°C) produced little detectable change in the concentration profile of the rare-earth elements but caused thinning of the interfacial SiO2 layer along with a corresponding increase in the rare-earth oxide layer thickness. These reactions could be explained with oxygen deficiency in the rare-earth oxide layer and its greater thermodynamic stability relative to SiO2. Negative flat band voltage shifts were observed relative to a control sample with no DyOx or HoOx. Mechanisms by which the observed microstructure changes could give rise to negative flatband voltage shifts are discussed.}, number={11}, journal={Applied Physics Letters}, publisher={AIP Publishing}, author={LeBeau, James M. and Jur, Jesse S. and Lichtenwalner, Daniel J. and Craft, H. Spalding and Maria, Jon-Paul and Kingon, Angus I. and Klenov, Dmitri O. and Cagnon, Joël and Stemmer, Susanne}, year={2008}, month={Mar}, pages={112912} }
 @article{suri_lichtenwalner_misra_2008, title={Impact of elemental arsenic on electrical characteristics of metal-oxide-semiconductor capacitors on GaAs using atomic-layer deposited HfO2 gate dielectric}, volume={92}, ISSN={["1077-3118"]}, DOI={10.1063/1.2949079}, abstractNote={The interface between HfO2 and sulfur-passivated GaAs was analyzed after atomic-layer deposition (ALD) and postdeposition annealing (PDA) using x-ray photoelectron spectroscopy. The HfO2 ALD process resulted in elemental arsenic buildup at the interface. Electrical measurements confirmed that the elemental arsenic caused anomalously large values for equivalent oxide thickness (EOT), hysteresis, and frequency dispersion in accumulation. Arsenic outdiffusion after PDA lowered the EOT but increased the gate leakage. Annealing the (NH4)2S-treated GaAs prior to ALD yielded an EOT of 1.85nm and leakage of 6.6×10−4A∕cm2 at Vg=Vfb−1V. This modified passivation scheme looks promising for achieving a high-quality HfO2∕GaAs interface.}, number={24}, journal={APPLIED PHYSICS LETTERS}, author={Suri, Rahul and Lichtenwalner, Daniel J. and Misra, Veena}, year={2008}, month={Jun} }
 @article{yang_lichtenwalner_morris_menzel_nauenheim_gruverman_krim_kingon_2007, title={A new test facility for efficient evaluation of MEMS contact materials}, volume={17}, ISSN={["1361-6439"]}, url={http://www.scopus.com/inward/record.url?eid=2-s2.0-51649090154&partnerID=MN8TOARS}, DOI={10.1088/0960-1317/17/9/006}, abstractNote={A novel test facility for the efficient evaluation of microelectromechanical system (MEMS) switches and the development of alternative contact materials is described. The facility utilizes the upper cantilever from commercial MEMS contact switches, and tests these against alternative bottom contact materials within a modified atomic force microscope (AFM). The test closely approximates the real switch, but can accommodate a wider range of test conditions and contact materials. The facility allows alternative contact materials to be easily and quickly incorporated, and therefore evaluated by measuring the number of cycles to failure. The evolution of the wear surfaces of the switch contact materials under test can also be easily examined. In order to demonstrate the facility, the evolution of the contact resistance and wear of a commercial RF MEMS cantilever with Au contacts was monitored under accelerated test conditions, comparing the behavior of Au bottom contacts to an alternative Au–Ni alloy contact material. The Au–Ni (20 at.%) alloy displayed reduced wear rates and improved switch cycle lifetimes compared to pure Au, while retaining acceptable values of contact resistance.}, number={9}, journal={JOURNAL OF MICROMECHANICS AND MICROENGINEERING}, author={Yang, Z. and Lichtenwalner, D. and Morris, A. and Menzel, S. and Nauenheim, C. and Gruverman, A. and Krim, J. and Kingon, A. I.}, year={2007}, month={Sep}, pages={1788–1795} }
 @article{inoue_lichtenwalner_jur_kingon_2007, title={Analysis of interface states in LaSixOy metal-insulator-semiconductor structures}, volume={46}, ISSN={["0021-4922"]}, DOI={10.1143/jjap.46.6480}, abstractNote={Using a comprehensive model to simulate interface state effects on metal–insulator–semiconductor (MIS) device in capacitance–voltage (C–V) behavior, interface properties of LaSixOy gate dielectric MIS structures were analyzed. Under low temperature (400 °C) processing conditions amenable to low (0.6 nm) equivalent oxide thickness (EOT), LaSiO-based MIS capacitors on n- and p-type substrates have a high density localized interface state. The peak densities of this localized state for MIS devices on n- and p-type substrates are (2.0–2.5)×1013 and 2.5×1012 cm-2 eV-1, respectively, lying deep in the Si bandgap (within 0.1 eV of midgap). Positive fixed charge density is derived as in the range of 1013 cm-2 and is found to be distributed close to the interface region. In the case of the p-type MIS capacitor, positive fixed charge and positively charged interface states shift the C–V curve in the negative direction. Interface states in the n-type MOS capacitor capture electrons, compensating for the positive fixed charge and positively charged interface states. Thus less shift of the C–V curve is observed, compared to the p-type case. Interface state and fixed charge densities drastically reduce by raising post annealing temperature, to <1012 cm-2 eV-1 on n-type Si, but with concurrent EOT increase. Forming gas annealing (FGA) is effective for reducing the localized interface state density, but only when the temperature is 600 °C or higher. Results point to a need to minimize defect densities during or immediately after dielectric deposition. The high levels of positive defect states warrant further detailed investigation of the charge trapping characteristics of these dielectrics, as La-containing dielectrics are important for threshold voltage control for metal–oxide–semiconductor field effect transistor (MOSFET) devices.}, number={10A}, journal={JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS}, author={Inoue, Naoya and Lichtenwalner, Daniel J. and Jur, Jesse S. and Kingon, Angus I.}, year={2007}, month={Oct}, pages={6480–6488} }
 @article{lichtenwalner_hydrick_kingon_2007, title={Flexible thin film temperature and strain sensor array utilizing a novel sensing concept}, volume={135}, ISSN={["0924-4247"]}, DOI={10.1016/j.sna.2006.07.019}, abstractNote={Flexible arrays of resistive temperature and strain sensors have been designed, and fabricated on polyimide sheets. We describe a novel sensor design concept, utilizing materials selection combined with specific device layout design, such that both temperature and strain values can be determined from resistance values of parallel sensor pairs, regardless of complex strain fields or temperature distribution. Fabrication of thin film Pt and NiCr resistive sensor arrays, with Cu conducting lines, on polyimide demonstrates the sensing concept. Temperature and strain sensing capabilities are demonstrated for temperatures up to 200 °C and up to 2% tensile strain.}, number={2}, journal={SENSORS AND ACTUATORS A-PHYSICAL}, author={Lichtenwalner, Daniel J. and Hydrick, Aaron E. and Kingon, Angus I.}, year={2007}, month={Apr}, pages={593–597} }
 @article{jur_lichtenwalner_kingon_2007, title={High temperature stability of lanthanum silicate dielectric on Si (001)}, volume={90}, ISSN={["0003-6951"]}, DOI={10.1063/1.2712805}, abstractNote={Integration of a high-κ dielectric into complementary metal-oxide-semiconductor devices requires thermal stability of the amorphous dielectric phase and chemical compatibility with silicon. The stability of amorphous lanthanum silicate on Si (001) is investigated by means of metal-insulator-semiconductor capacitor measurements, back side secondary ion mass spectrometry (SIMS) depth profiling, and high-resolution transmission electron microscopy (HRTEM) after a 1000°C, 10s anneal in nitrogen ambient. Back side SIMS depth profiling of the TaN∕LaSiOx∕Si gate stack reveals no detectable lanthanum in the silicon substrate, and HRTEM shows stability of the amorphous LaSiOx. An effective work function near 4.0eV is obtained for these gate stacks, making the stack design ideal for n-type metal-oxide-semiconductor device fabrication.}, number={10}, journal={APPLIED PHYSICS LETTERS}, author={Jur, J. S. and Lichtenwalner, D. J. and Kingon, A. I.}, year={2007}, month={Mar} }
 @article{lichtenwalner_jur_jha_inoue_chen_misra_kingon_2006, title={High-temperature stability of lanthanum silicate gate dielectric MIS devices with Ta and TaN electrodes}, volume={153}, ISSN={["1945-7111"]}, DOI={10.1149/1.2218757}, abstractNote={The high-temperature stability of lanthanum silicate gate dielectric metal-insulator-semiconductor (MIS) devices with either Ta or TaN electrodes has been studied. After a 1000°C, 10 s rapid thermal annealing (RTA) treatment, devices with Ta gate metal undergo an equivalent oxide thickness (EOT) increase from 0.62 to 1.57 nm or higher, while devices with TaN as the gate electrode experience an EOT increase from 0.62 to only 1.12 nm. An EOT less than 1.0 nm is achieved after a 5 s 1000°C RTA, with a corresponding gate leakage of 0.1 A/cm 2 . Medium-energy ion scattering and X-ray diffraction (XRD) analysis reveal that the Ta gate metal undergoes a phase change due to reaction with N 2 above 800°C, while for TaN no change in the XRD spectrum is detected. Interface state defect densities and leakage currents are reduced after the high-temperature processing. Results reveal the importance of the entire gate stack design and processing in obtaining good device properties.}, number={9}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Lichtenwalner, Daniel J. and Jur, Jesse S. and Jha, Rashmi and Inoue, Naoya and Chen, Bei and Misra, Veena and Kingon, Angus I.}, year={2006}, pages={F210–F214} }
 @article{alshareef_quevedo-lopez_wen_harris_kirsch_majhi_lee_jammy_lichtenwalner_jur_et al._2006, title={Work function engineering using lanthanum oxide interfacial layers}, volume={89}, ISSN={["1077-3118"]}, DOI={10.1063/1.2396918}, abstractNote={A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function.}, number={23}, journal={APPLIED PHYSICS LETTERS}, author={Alshareef, H. N. and Quevedo-Lopez, M. and Wen, H. C. and Harris, R. and Kirsch, P. and Majhi, P. and Lee, B. H. and Jammy, R. and Lichtenwalner, D. J. and Jur, J. S. and et al.}, year={2006}, month={Dec} }
 @article{lichtenwalner_jur_kingon_agustin_yang_stemmer_goncharova_gustafsson_garfunkel_2005, title={Lanthanum silicate gate dielectric stacks with subnanometer equivalent oxide thickness utilizing an interfacial silica consumption reaction}, volume={98}, ISSN={["1089-7550"]}, DOI={10.1063/1.1988967}, abstractNote={A silicate reaction between lanthana and silica layers has been utilized to eliminate interfacial silica in metal-insulator-semiconductor devices and to obtain devices with very low equivalent oxide thickness (EOT). This provides a simple process route to interface elimination, while producing a silicate dielectric with a higher temperature stability of the amorphous phase. The La2O3 layers in this study are deposited by reactive evaporation on (001) Si covered by a ∼0.8–1.0-nm-thick SiO2 chemical oxide, and are capped in situ with a Ta gate, followed by a reaction anneal, which lowers the EOT from greater than 1.5 nm for the as-deposited bilayer stack to as low as 0.5 nm. Electron energy-loss spectroscopy and medium-energy ion scattering are used to show that a temperature of 400 °C is sufficient for the formation of the silicate gate dielectric. Gate leakage currents as low as 0.06A∕cm2 are obtained for stacks having an EOT of 0.63 nm, orders of magnitude below that of SiO2 having the same EOT value. Electrical breakdown is observed at applied fields above 16MV∕cm.}, number={2}, journal={JOURNAL OF APPLIED PHYSICS}, author={Lichtenwalner, DJ and Jur, JS and Kingon, AI and Agustin, MP and Yang, Y and Stemmer, S and Goncharova, LV and Gustafsson, T and Garfunkel, E}, year={2005}, month={Jul} }
 @misc{kingon_al-shareef_auciello_gifford_lichtenwalner_dat_1996, title={Hybrid metal/metal oxide electrodes for ferroelectric capacitors}, volume={5,555,486}, number={1996 Sep. 10}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Kingon, A. I. and Al-Shareef, H. N. and Auciello, O. H. and Gifford, K. D. and Lichtenwalner, D. J. and Dat, R.}, year={1996} }