@article{gupta_zhang_liu_isukapati_ashik_morgan_lee_sung_agarwal_fayed_2024, title={A 400 V Buck Converter integrated with Gate-Drivers and low-voltage Controller in a 25-600 V mixed-mode SiC CMOS technology}, ISSN={["1573-1979"]}, DOI={10.1007/s10470-024-02270-3}, journal={ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING}, author={Gupta, Utsav and Zhang, Hua and Liu, Tianshi and Isukapati, Sundar and Ashik, Emran and Morgan, Adam and Lee, Bongmook and Sung, Woongje and Agarwal, Anant and Fayed, Ayman}, year={2024}, month={Apr} }
 @article{isukapati_zhang_liu_gupta_ashik_morgan_jang_lee_sung_fayed_et al._2024, title={Design and experimental demonstration of high-voltage lateral nMOSFETs and high-temperature CMOS ICs*}, volume={169}, ISSN={["1873-4081"]}, DOI={10.1016/j.mssp.2023.107921}, abstractNote={This paper reports the design and experimental demonstration of the HV Lateral nMOSFETs along with Low-Voltage CMOS ICs for the advancement of Power IC technology in 4H–SiC. The HV nMOSFETs discussed in this study are designed for operation within the 400–600V range exhibiting the best-in-class trade-off performance in terms of breakdown voltage – specific on-resistance (BV-Ron,sp). The process technology employed in this work was developed with an objective to monolithically integrate the LV CMOS control circuity with the HV nMOSFET. This work wraps around reporting the design and module process developments accompanied by on-wafer characterizations of the HV nMOSFETs and CMOS respectively. Several P-Well and N-Wells were designed for NMOS and PMOS to target the current and voltage requirements. Attempts have been dedicated to accomplishing lower n-type and p-type contact resistances with diverse ohmic stacks along with well-established Ni as the primary ohmic metal. Finally, to validate the potential of the demonstrated CMOS designs, digital CMOS ICs have been demonstrated and characterized under harsh thermal conditions of up to 450 °C.}, journal={MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING}, author={Isukapati, Sundar Babu and Zhang, Hua and Liu, Tianshi and Gupta, Utsav and Ashik, Emran and Morgan, Adam J. and Jang, Seung Yup and Lee, Bongmook and Sung, Woongje and Fayed, Ayman and et al.}, year={2024}, month={Jan} }
 @article{zhang_liu_gupta_isukapati_ashik_morgan_lee_sung_agarwal_fayed_2022, title={A 600V Half-Bridge Power Stage Fully Integrated with 25V Gate-Drivers in SiC CMOS Technology}, DOI={10.1109/MWSCAS54063.2022.9859305}, abstractNote={A 600V half-bridge power stage fully integrated with 25V gate-drivers is presented to demonstrate a new $0.5 \mu \mathrm{m}$ Silicon Carbide (SiC) CMOS technology. The technology allows for integrating low-voltage CMOS devices with multiple lateral high-voltage NMOS devices. Thus, multi-switch power converters or multiple power converters can be integrated along with their gate-drivers and low-voltage control circuits in the same SiC chip. The half-bridge power stage has two power switches with $500\mathrm{m} \Omega$ ON resistance, and it operates from a 600V input with up to 1A load and a switching frequency of 1MHz. The gate-drivers employ a capacitive level shifter and a bootstrap circuit to convert the PWM control signal from the 25V control domain to the 600V power domain. The gate-driver has a total delay of 36ns and provides a gate-driver signal with a slew rate of 23V/ns.}, journal={2022 IEEE 65TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS 2022)}, author={Zhang, Hua and Liu, Tianshi and Gupta, Utsav and Isukapati, Sundar Babu and Ashik, Emran and Morgan, Adam J. and Lee, Bongmook and Sung, Woongje and Agarwal, Anant K. and Fayed, Ayman}, year={2022} }
 @article{ashik_isukapati_zhang_liu_gupta_morgan_misra_sung_fayed_agarwal_et al._2022, title={Bias Temperature Instability on SiC n- and p-MOSFETs for High Temperature CMOS Applications}, ISSN={["1541-7026"]}, DOI={10.1109/IRPS48227.2022.9764565}, abstractNote={The circuit functionalities of Complementary Metal-Oxide-Semiconductor (CMOS) devices on 4H-SiC for digital and analog circuit applications beyond 200°C have been extensively studied, however, the reliability of the devices on SiC needs to be demonstrated due to the traps at/near the dielectric interface. In this report, the reliability of n- and p- Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied on three different gate oxide conditions – thick thermally grown, ultrathin thermal + thick CVD oxide and ultrathin thermal + thin CVD oxide in terms of their bias temperature instability (BTI) measurement. The MOSFETs were stressed at various constant bias voltages at 150°C and up to 105s. The threshold voltage shift due to positive bias on n-MOSFET is <0.5V after 105s at +25Vwhile p-MOSFET shows a larger shift of -1.9V shift after 105s at -25V and 150°C for ultrathin + thick CVD oxide. The report also establishes improvement in reliability of p-MOSFETs with ultrathin + CVD oxides over thermally grown oxides.}, journal={2022 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)}, author={Ashik, Emran K. and Isukapati, Sundar B. and Zhang, Hua and Liu, Tianshi and Gupta, Utsav and Morgan, Adam J. and Misra, Veena and Sung, Woongje and Fayed, Ayman and Agarwal, Anant K. and et al.}, year={2022} }
 @article{liu_zhang_isukapati_ashik_morgan_lee_sung_fayed_white_agarwal_2022, title={SPICE Modeling and Circuit Demonstration of a SiC Power IC Technology}, volume={10}, ISSN={["2168-6734"]}, DOI={10.1109/JEDS.2022.3150364}, abstractNote={Silicon carbide (SiC) power integrated circuit (IC) technology allows monolithic integration of 600V lateral SiC power MOSFETs and low-voltage SiC CMOS devices. It enables application-specific SiC ICs with high power output and work under harsh (high-temperature and radioactive) environments compared to Si power ICs. This work presents the device characteristics, SPICE modeling, and SiC CMOS circuit demonstrations of the first two lots of the proposed SiC power IC technology. Level 3 SPICE models are created for the high-voltage lateral power MOSFETs and low-voltage CMOS devices. SiC ICs, such as the SiC CMOS inverter and ring oscillator, have been designed, packaged, and characterized. Proper operations of the circuits are demonstrated. The effects of the trapped interface charges on the characteristics of SiC MOSFETs and SiC ICs are also discussed.}, journal={IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY}, author={Liu, Tianshi and Zhang, Hua and Isukapati, Sundar Babu and Ashik, Emran and Morgan, Adam J. and Lee, Bongmook and Sung, Woongje and Fayed, Ayman and White, Marvin H. and Agarwal, Anant K.}, year={2022}, pages={129–138} }
 @article{isukapati_morgan_sung_zhang_liu_fayed_agarwal_ashik_lee_2021, title={Development of Isolated CMOS and HV MOSFET on an N- epi/P- epi/4H-SiC N+ Substrate for Power IC Applications}, DOI={10.1109/WiPDA49284.2021.9645134}, abstractNote={This paper reports the design and process flow of a fully integrated yet isolated low-voltage (LV) CMOS with high voltage (HV) lateral power MOSFET on a 6-inch 4H-SiC substrate for the development of HV SiC power ICs. The epi stack (N- epi/P- epi on N+ substrate) for the development of the power ICs was optimized to accommodate and isolate the HV devices and circuits from their LV counterparts. The devices reported in this work were fabricated at 150mm, production grade-Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose, CA. The HV lateral NMOSFET from this work demonstrated a breakdown voltage (BV) of 620V and a specific on-resistance (Ron,sp) of 9.73 mΩ·cm2 at gate-source voltage (Vgs) of 25V. A single gate oxide and ohmic process were used to fabricate the HV NMOS and LV CMOS devices and circuits. Junction isolation was implemented for isolating the HV and the LV blocks for the design of HV Power ICs. Finally, this work executed an HV capable three-metal layered back-end-of-the-line (BEOL) process, an imperative provision for developing reliable and robust power ICs. For future high-temperature applications, the static performances of the devices are characterized and are reported up to 200°C.}, journal={2021 IEEE 8TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA)}, author={Isukapati, Sundar Babu and Morgan, Adam J. and Sung, Woongje and Zhang, Hua and Liu, Tianshi and Fayed, Ayman and Agarwal, Anant K. and Ashik, Emran and Lee, Bongmook}, year={2021}, pages={118–122} }
 @article{liu_zhang_isukapati_ashik_morgan_lee_sung_white_fayed_agarwal_2021, title={SPICE Modeling and CMOS Circuit Development of a SiC Power IC Technology}, ISSN={["1558-3899"]}, DOI={10.1109/MWSCAS47672.2021.9531903}, abstractNote={This paper presents the SPICE modeling and circuit development of a SiC power integrated circuit (IC) technology that offers monolithic integration of high-voltage lateral n-type SiC power metal-oxide-semiconductor field-effect transistors (MOSFETs) and low-voltage SiC complementary-MOS (CMOS) devices. The SPICE models are based on two-dimensional device simulations with the Sentaurus TCAD device simulator. With the developed SPICE models, this technology enables the design of application specific integrated circuits (ASICs) in SiC, such as fully integrated high-voltage SiC power converters, that can work in high temperature and radioactive environments. Circuit simulations of a SiC CMOS inverter and a SiC ring oscillator are included to demonstrate the technology.}, journal={2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS)}, author={Liu, Tianshi and Zhang, Hua and Isukapati, Sundar Babu and Ashik, Emaran and Morgan, Adam J. and Lee, Bongmook and Sung, Woongje and White, Marvin H. and Fayed, Ayman and Agarwal, Anant K.}, year={2021}, pages={966–969} }