Eric Rotenberg

Design for 3D Stacked Circuits

2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM).

Post-Silicon Microarchitecture

IEEE COMPUTER ARCHITECTURE LETTERS, 19(1), 26–29.

Slipstream Processors Revisited: Exploiting Branch Sets

2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 105–117.

A case for standard-cell based RAMs in highly-ported superscalar processor structures

Proceedings of the eighteenth international symposium on quality electronic design (isqed), 131–137.

H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor

2017 IEEE International Conference on Computer Design (ICCD), 145–152.

AnyCore-1: A comprehensively adaptive 4-way superscalar processor

2016 ieee hot chips 28 symposium (hcs).

AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores

Ieee international symposium on performance analysis of systems and, 214–224.

Fast register consolidation and migration for heterogeneous multi-core processors

Proceedings of the 34th ieee international conference on computer design (iccd), 1–8.

Physical design of a 3D-stacked heterogeneous multi-core processor

2016 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2016 IEEE International 3D Systems Integration Conference (3DIC), -San Francisco, CA.

Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching

IEEE TRANSACTIONS ON COMPUTERS, 64(8), 2182–2203.

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow

2014 19th asia and south pacific design automation conference (asp-dac), 400–405.

Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores

2014 IEEE 32nd International Conference on Computer Design (ICCD). Presented at the 2014 32nd IEEE International Conference on Computer Design (ICCD).

A Unified View of Non-monotonic Core Selection and Application Steering in Heterogeneous Chip Multiprocessors

Proceedings of the 22nd IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-22), 133–144.

Design of controller for L2 cache mapped in Tezzaron stacked DRAM

2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA.

Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors

Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7.

Rationale for a 3D heterogeneous multi-core processor

2013 IEEE 31st International Conference on Computer Design (ICCD), 154–168.

A physical design study of fabscalar-generated superscalar cores

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). Presented at the 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC).

Control-Flow Decoupling

2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), pp. 329–340.

FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN

IEEE MICRO, 32(3), 48–59.

FPGA modeling of diverse superscalar processors

2012 IEEE International Symposium on Performance Analysis of Systems & Software. Presented at the 2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS).

Research for Transporting Alpha ISA and Adopting Multi-processor to FabScalar

Proceedings of the Symposium on Advanced Computing Systems and Infrastructures 2012 (SACSIS 2012), 374–381.

FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template

ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22.

Criticality-driven Superscalar Design Space Exploration

PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, pp. 261–272.

EXACT: Explicit Dynamic-Branch Prediction with Active Updates

Proceedings of the 7th ACM international conference on Computing frontiers - CF '10, 165–176.

Architectural Contesting

2009 IEEE 15th International Symposium on High Performance Computer Architecture. Presented at the 2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA).

Core-Selectability in Chip Multiprocessors

18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 113–122.

The Importance of Accurate Task Arrival Characterization in the Design of Processing Cores

PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, pp. 75–85.

Configurational Workload Characterization

ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software. Presented at the Software (ISPASS).

Coverage of a microarchitecture-level fault check regimen in a superscalar processor

2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN). Presented at the 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance

37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07). Presented at the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

Transparent control independence (TCI)

Proceedings of the 34th annual international symposium on Computer architecture - ISCA '07. Presented at the the 34th annual international symposium.

ZettaRAM: A power-scalable DRAM alternative through charge-voltage decoupling

IEEE TRANSACTIONS ON COMPUTERS, 56(2), 147–160.

Assertion-Based Microarchitecture Design for Improved Fault Tolerance

2006 International Conference on Computer Design. Presented at the 2006 International Conference on Computer Design.

FAST: Frequency-Aware Static Timing Analysis

ACM Transactions on Programming Languages and Systems, 5(1), 200–224.

Non-uniform program analysis & repeatable execution constraints: Exploiting out-of-order processors in real-time systems

Non-uniform program analysis & repeatable execution constraints: Exploiting out-of-order processors in real-time systems. SIGBED Review, 3(1).

Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM

TWELFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 157-+.

Systems, methods and devices for providing variable-latency write operations in memory devices

Washington, DC: U.S. Patent and Trademark Office.

The State of ZettaRAM

2006 1st International Conference on Nano-Networks and Workshops. Presented at the 2006 1st International Conference on Nano-Networks and Workshops.

Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance

Proceedings of the 12th international conference on Architectural support for programming languages and operating systems - ASPLOS-XII. Presented at the the 12th international conference.

Architecture of embedded microprocessors

In W. Wolf & A. Jerraya (Eds.), Multiprocessor systems on chips (pp. 81–112).

Tapping ZettaRAM (TM) for low-power memory systems

11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 83–94.

Trace caches

In D. Kaeli & P.-C. Yew (Eds.), Speculative execution in high performance computer architectures.

Variable-persistence molecular memory devices and methods of operation thereof

Washington, DC: U.S. Patent and Trademark Office.

Virtual multiprocessor: An analyzable, high-performance microarchitecture for real-time computing

CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 24-27, 2005, San Francisco, California, USA, 213–224.

A simple mechanism for detecting ineffectual instructions in slipstream processors

IEEE TRANSACTIONS ON COMPUTERS, 53(4), 399–413.

Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (VISA)

25TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 114–125.

Safely exploiting multithreaded processors to tolerate memory latency in real-time systems

CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 22-25, 2004, Washington, DC, USA, 2–13.

Adaptive mode control: A static-power-efficient cache design

ACM Transactions on Embedded Computing Systems, 2(3), 347–372.

FAST: Frequency-aware static timing analysis

RTSS 2003: 24TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 40–51.

Slipstream execution mode for CMP-based multiprocessors

NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, Vol. 12, pp. 179–190.

Virtual Simple Architecture (VISA): Exceeding the complexity limit in safe real-time systems

Computers and their applications :|bproceedings of the ISCA 16th International Conference, Seattle, Washington, USA, March 28-30, 2001, 350–361. Cary, NC: ISCA.

A case for dynamic pipeline scaling

Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems|h: 2002, Greenoble, France, October 08-11, 2002, 1–8.

A large, fast instruction window for tolerating cache misses

29th Annual International Symposium on Computer Architecture: Proceedings : 25-29 May, 2002, Anchorage, Alaska, 59–70.

Adaptive mode control: A static-power-efficient cache design

2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70.

Trace caching and trace processors

In Computer engineering handbook (pp. 8–45). Boca Raton, FL: CRC Press.

Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems

34TH ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO-34, PROCEEDINGS, pp. 28–39.

A study of slipstream processors

Proceedings: 33rd Annual IEEE/ACM International Symposium on Microarchitecture: Monterey, California, USA, 10-13 December 2000, 269–280.

Control independence in trace processors

Journal of Instruction-Level Parallelism, 2, 63–85.

Slipstream processors: Improving both performance and fault tolerance

ASPLOS-IX proceedings: Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, November 12-15, 2000, 257–268.

A study of control independence in superscalar processors

FIFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 115–124.

A trace cache microarchitecture and evaluation

IEEE TRANSACTIONS ON COMPUTERS, 48(2), 111–120.

AR-SMT: A microarchitectural approach to fault tolerance in microprocessors

Digest of papers: Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing: June 15-18, 1999, Madison, Wisconsin, USA, 84–91.

Control independence in trace processors

32ND ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-32), PROCEEDINGS, pp. 4–15.

Path-based next trace prediction

THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, pp. 14–23.

Trace processors

THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, pp. 138–148.

Assigning confidence to conditional branch predictions

PROCEEDINGS OF THE 29TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE - MICRO-29, pp. 142–152.

Trace cache: A low latency approach to high bandwidth instruction fetching

PROCEEDINGS OF THE 29TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE - MICRO-29, pp. 24–34.