Eric Rotenberg

Franzon, P., Davis, W., Rotenberg, E., Stevens, J., Lipa, S., Nigussie, T., … Li, W. (2021). Design for 3D Stacked Circuits. 2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM). https://doi.org/10.1109/IEDM19574.2021.9720553

Kumar, C., Chaudhary, A., Bhawalkar, S., Mathur, U., Jain, S., Vastrad, A., & Rotenberg, E. (2020). Post-Silicon Microarchitecture. IEEE COMPUTER ARCHITECTURE LETTERS, 19(1), 26–29. https://doi.org/10.1109/LCA.2020.2978841

Srinivasan, V., Chowdhury, R. B. R., & Rotenberg, E. (2020). Slipstream Processors Revisited: Exploiting Branch Sets. 2020 ACM/IEEE 47TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA 2020), pp. 105–117. https://doi.org/10.1109/ISCA45697.2020.00020

Ku, S., Forbes, E., Chowdhury, R. B. R., & Rotenberg, E. (2017). A case for standard-cell based RAMs in highly-ported superscalar processor structures. Proceedings of the eighteenth international symposium on quality electronic design (isqed), 131–137. https://doi.org/10.1109/isqed.2017.7918305

Srinivasan, V., Chowdhury, R. B. R., Forbes, E., Widialaksono, R., Zhang, Z. Q., Schabel, J., … Franzon, P. D. (2017). H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor. 2017 IEEE International Conference on Computer Design (ICCD), 145–152. https://doi.org/10.1109/ICCD.2017.30

Chowdhury, R. B. R., Kannepalli, A. K., & Rotenberg, E. (2016). AnyCore-1: A comprehensively adaptive 4-way superscalar processor. 2016 ieee hot chips 28 symposium (hcs). https://doi.org/10.1109/hotchips.2016.7936237

Chowdhury, R. B. R., Kannepalli, A. K., Ku, S., & Rotenberg, E. (2016). AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores. Ieee international symposium on performance analysis of systems and, 214–224. https://doi.org/10.1109/ispass.2016.7482096

Forbes, E., & Rotenberg, E. (2016). Fast register consolidation and migration for heterogeneous multi-core processors. Proceedings of the 34th ieee international conference on computer design (iccd), 1–8. https://doi.org/10.1109/iccd.2016.7753254

Widialaksono, R., Basu Roy Chowdhury, R., Zhang, Z., Schabel, J., Lipa, S., Rotenberg, E., … Franzon, P. (2016). Physical design of a 3D-stacked heterogeneous multi-core processor. 2016 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2016 IEEE International 3D Systems Integration Conference (3DIC), -San Francisco, CA. https://doi.org/10.1109/3dic.2016.7970036

Sheikh, R., Tuck, J., & Rotenberg, E. (2015). Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching. IEEE TRANSACTIONS ON COMPUTERS, 64(8), 2182–2203. https://doi.org/10.1109/tc.2014.2361526

Nakabayashi, T., Sugiyama, T., Sasaki, T., Rotenberg, E., & Kondo, T. (2014). Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. 2014 19th asia and south pacific design automation conference (asp-dac), 400–405. https://doi.org/10.1109/aspdac.2014.6742924

Forbes, E., Choudhary, N. K., Dwiel, B. H., & Rotenberg, E. (2014). Design-effort alloy: Boosting a highly tuned primary core with untuned alternate cores. 2014 IEEE 32nd International Conference on Computer Design (ICCD). Presented at the 2014 32nd IEEE International Conference on Computer Design (ICCD). https://doi.org/10.1109/iccd.2014.6974713

Navada, S., Choudhary, N. K., Wadhavkar, S. V., & Rotenberg, E. (2013). A Unified View of Non-monotonic Core Selection and Application Steering in Heterogeneous Chip Multiprocessors. Proceedings of the 22nd IEEE/ACM International Conference on Parallel Architectures and Compilation Techniques (PACT-22), 133–144.

Tshibangu, N. M., Franzon, P. D., Rotenberg, E., & Davis, W. R. (2013). Design of controller for L2 cache mapped in Tezzaron stacked DRAM. 2013 IEEE International 3D Systems Integration Conference (3DIC). Presented at the 2013 IEEE International 3D Systems Integration Conference (3DIC), San Francisco, CA. https://doi.org/10.1109/3dic.2013.6702397

Priyadarshi, S., Choudhary, N., Dwiel, B., Upreti, A., Rotenberg, E., Davis, R., & Franzon, P. (2013). Hetero(2) 3d integration: A scheme for optimizing efficiency/cost of chip multiprocessors. Proceedings of the fourteenth international symposium on quality electronic design (ISQED 2013), 1–7. https://doi.org/10.1109/isqed.2013.6523582

Rotenberg, E., Dwiel, B. H., Forbes, E., Zhang, Z., Widialaksono, R., Chowdhury, R. B. R., … al. (2013). Rationale for a 3D heterogeneous multi-core processor. 2013 IEEE 31st International Conference on Computer Design (ICCD), 154–168. https://doi.org/10.1109/iccd.2013.6657038

Choudhary, N. K., Dwiel, B. H., & Rotenberg, E. (2012). A physical design study of fabscalar-generated superscalar cores. 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). Presented at the 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). https://doi.org/10.1109/vlsi-soc.2012.7332095

Sheikh, R., Tuck, J., & Rotenberg, E. (2012). Control-Flow Decoupling. 2012 IEEE/ACM 45TH INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO-45), pp. 329–340. https://doi.org/10.1109/micro.2012.38

Choudhary, N. K., Wadhavkar, S. V., Shah, T. A., Mayukh, H., Gandhi, J., Dwiel, B. H., … Rotenberg, E. (2012). FABSCALAR: AUTOMATING SUPERSCALAR CORE DESIGN. IEEE MICRO, 32(3), 48–59. https://doi.org/10.1109/mm.2012.23

Dwiel, B. H., Choudhary, N. K., & Rotenberg, E. (2012). FPGA modeling of diverse superscalar processors. 2012 IEEE International Symposium on Performance Analysis of Systems & Software. Presented at the 2012 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS). https://doi.org/10.1109/ispass.2012.6189225

Nakabayashi, T., Sasaki, T., Rotenberg, E., Ohno, K., & Kondo, T. (2012). Research for Transporting Alpha ISA and Adopting Multi-processor to FabScalar. Proceedings of the Symposium on Advanced Computing Systems and Infrastructures 2012 (SACSIS 2012), 374–381.

Choudhary, N. K., Wadhavkar, S. V., Shah, T. A., Mayukh, H., Gandhi, J., Dwiel, B. H., … Rotenberg, E. (2011). FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template. ISCA 2011: Proceedings of the 38th Annual International Symposium on Computer Architecture, 11–22. https://doi.org/10.1145/2000064.2000067

Navada, S., Choudhary, N. K., & Rotenberg, E. (2010). Criticality-driven Superscalar Design Space Exploration. PACT 2010: PROCEEDINGS OF THE NINETEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, pp. 261–272. https://doi.org/10.1145/1854273.1854308

Al-Otoom, M., Forbes, E., & Rotenberg, E. (2010). EXACT: Explicit Dynamic-Branch Prediction with Active Updates. Proceedings of the 7th ACM international conference on Computing frontiers - CF '10, 165–176. https://doi.org/10.1145/1787275.1787321

Najaf-abadi, H. H., & Rotenberg, E. (2009). Architectural Contesting. 2009 IEEE 15th International Symposium on High Performance Computer Architecture. Presented at the 2009 IEEE 15th International Symposium on High Performance Computer Architecture (HPCA). https://doi.org/10.1109/hpca.2009.4798254

Najaf-abadi, H. H., Choudhary, N. K., & Rotenberg, E. (2009). Core-Selectability in Chip Multiprocessors. 18TH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES, PROCEEDINGS, pp. 113–122. https://doi.org/10.1109/pact.2009.44

Najaf-abadi, H. H., & Rotenberg, E. (2009). The Importance of Accurate Task Arrival Characterization in the Design of Processing Cores. PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, pp. 75–85. https://doi.org/10.1109/iiswc.2009.5306795

Najaf-abadi, H. H., & Rotenberg, E. (2008). Configurational Workload Characterization. ISPASS 2008 - IEEE International Symposium on Performance Analysis of Systems and software. Presented at the Software (ISPASS). https://doi.org/10.1109/ispass.2008.4510747

Reddy, V., & Rotenberg, E. (2008). Coverage of a microarchitecture-level fault check regimen in a superscalar processor. 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN). Presented at the 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN). https://doi.org/10.1109/dsn.2008.4630065

Reddy, V., & Rotenberg, E. (2007). Inherent Time Redundancy (ITR): Using Program Repetition for Low-Overhead Fault Tolerance. 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07). Presented at the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07). https://doi.org/10.1109/dsn.2007.59

Al-Zawawi, A. S., Reddy, V. K., Rotenberg, E., & Akkary, H. H. (2007). Transparent control independence (TCI). Proceedings of the 34th annual international symposium on Computer architecture  - ISCA '07. Presented at the the 34th annual international symposium. https://doi.org/10.1145/1250662.1250717

Venkatesan, R. K., Al-Zawawi, A. S., Sivasubramanian, K., & Rotenberg, E. (2007). ZettaRAM: A power-scalable DRAM alternative through charge-voltage decoupling. IEEE TRANSACTIONS ON COMPUTERS, 56(2), 147–160. https://doi.org/10.1109/TC.2007.37

Reddy, V. K., Al-Zawawi, A. S., & Rotenberg, E. (2006). Assertion-Based Microarchitecture Design for Improved Fault Tolerance. 2006 International Conference on Computer Design. Presented at the 2006 International Conference on Computer Design. https://doi.org/10.1109/iccd.2006.4380842

Seth, K., Anantaraman, A., Mueller, F., & Rotenberg, E. (2006). FAST: Frequency-Aware Static Timing Analysis. ACM Transactions on Programming Languages and Systems, 5(1), 200–224.

Anantaraman, A., & Rotenberg, E. (2006). Non-uniform program analysis & repeatable execution constraints: Exploiting out-of-order processors in real-time systems. SIGBED Review, 3(1). https://doi.org/10.1145/1279711.1279716

Venkatesan, R. K., Herr, S., & Rotenberg, E. (2006). Retention-aware placement in DRAM (RAPID): Software methods for quasi-non-volatile DRAM. TWELFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 157-+. https://doi.org/10.1109/hpca.2006.1598122

Rotenberg, E., Venkatesan, R. K., & Al-Zawawi, A. S. (2006). Systems, methods and devices for providing variable-latency write operations in memory devices. Washington, DC: U.S. Patent and Trademark Office.

Rotenberg, E., & Venkatesan, R. K. (2006). The State of ZettaRAM. 2006 1st International Conference on Nano-Networks and Workshops. Presented at the 2006 1st International Conference on Nano-Networks and Workshops. https://doi.org/10.1109/nanonet.2006.346220

Reddy, V. K., Rotenberg, E., & Parthasarathy, S. (2006). Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance. Proceedings of the 12th international conference on Architectural support for programming languages and operating systems  - ASPLOS-XII. Presented at the the 12th international conference. https://doi.org/10.1145/1168857.1168869

Rotenberg, E., & Anantaraman, A. (2005). Architecture of embedded microprocessors. In W. Wolf & A. Jerraya (Eds.), Multiprocessor systems on chips (pp. 81–112). https://doi.org/10.1016/b978-012385251-9/50018-9

Venkatesan, R. K., Al-Zawawi, A. S., & Rotenberg, E. (2005). Tapping ZettaRAM (TM) for low-power memory systems. 11TH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 83–94. https://doi.org/10.1109/hpca.2005.35

Rotenberg, E. (2005). Trace caches. In D. Kaeli & P.-C. Yew (Eds.), Speculative execution in high performance computer architectures. https://doi.org/10.1201/9781420035155.ch4

Rotenberg, E., & Lindsey, J. S. (2005). Variable-persistence molecular memory devices and methods of operation thereof. Washington, DC: U.S. Patent and Trademark Office.

El-Haj-Mahmoud, A., Al-Zawawi, A. S., Anantaraman, A., & Rotenberg, E. (2005). Virtual multiprocessor: An analyzable, high-performance microarchitecture for real-time computing. CASES 2005: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 24-27, 2005, San Francisco, California, USA, 213–224. https://doi.org/10.1145/1086297.1086326

Koppanalil, J. J., & Rotenberg, E. (2004). A simple mechanism for detecting ineffectual instructions in slipstream processors. IEEE TRANSACTIONS ON COMPUTERS, 53(4), 399–413. https://doi.org/10.1109/TC.2004.1268397

Anantaraman, A., Seth, K., Rotenberg, E., & Mueller, F. (2004). Enforcing safety of real-time schedules on contemporary processors using a virtual simple architecture (VISA). 25TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 114–125. https://doi.org/10.1109/real.2004.19

El-Haj-Mahmoud, A., & Rotenberg, E. (2004). Safely exploiting multithreaded processors to tolerate memory latency in real-time systems. CASES 2004: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, September 22-25,  2004, Washington, DC, USA, 2–13. https://doi.org/10.1145/1023833.1023837

Huiyang, Toburen, M. C., Rotenberg, E., & Conte, T. M. (2003). Adaptive mode control: A static-power-efficient cache design. ACM Transactions on Embedded Computing Systems, 2(3), 347–372. https://doi.org/10.1145/860176.860181

Seth, K., Anantaraman, A., Mueller, F., & Rotenberg, E. (2003). FAST: Frequency-aware static timing analysis. RTSS 2003: 24TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, pp. 40–51. https://doi.org/10.1109/real.2003.1253252

Ibrahim, K. Z., Byrd, G. T., & Rotenberg, E. (2003). Slipstream execution mode for CMP-based multiprocessors. NINTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, Vol. 12, pp. 179–190. https://doi.org/10.1109/hpca.2003.1183536

Anantaraman, A., Seth, K., Patil, K., Rotenberg, E., & F. Mueller, F. (2003). Virtual Simple Architecture (VISA): Exceeding the complexity limit in safe real-time systems. Computers and their applications :|bproceedings of the ISCA 16th International Conference, Seattle, Washington, USA, March 28-30, 2001, 350–361. Cary, NC: ISCA.

Koppanalil, J., Ramrakhyani, P., Desai, S., Vaidyanathan, A., & Rotenberg, E. (2002). A case for dynamic pipeline scaling. Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems|h: 2002, Greenoble, France, October 08-11, 2002, 1–8. https://doi.org/10.1145/581630.581632

Lebeck, A. R., Koppanalil, J. J., Li, T., Patwardhan, J., & Rotenberg, E. (2002). A large, fast instruction window for tolerating cache misses. 29th Annual International Symposium on Computer Architecture: Proceedings : 25-29 May, 2002, Anchorage, Alaska, 59–70. https://doi.org/10.1109/isca.2002.1003562

Huiyang, Toburen, M. C., Rotenberg, E., & Conte, T. M. (2001). Adaptive mode control: A static-power-efficient cache design. 2001 International Conference on Parallel Architectures and Compilation Techniques: Proceedings: 8-12 September, 2001, Barcelona, Catalunya, Spain, 61–70. https://doi.org/10.1109/pact.2001.953288

Rotenberg, E. (2001). Trace caching and trace processors. In Computer engineering handbook (pp. 8–45). Boca Raton, FL: CRC Press.

Rotenberg, E. (2001). Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems. 34TH ACM/IEEE INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, MICRO-34, PROCEEDINGS, pp. 28–39. https://doi.org/10.1109/micro.2001.991103

Purser, Z., Sundaramoorthy, K., & Rotenberg, E. (2000). A study of slipstream processors. Proceedings: 33rd Annual IEEE/ACM International Symposium on Microarchitecture: Monterey, California, USA, 10-13 December 2000, 269–280. https://doi.org/10.1145/360128.360155

Rotenberg, E., & Smith, J. E. (2000). Control independence in trace processors. Journal of Instruction-Level Parallelism, 2, 63–85.

Sundaramoorthy, K., Purser, Z., & Rotenberg, E. (2000). Slipstream processors: Improving both performance and fault tolerance. ASPLOS-IX proceedings: Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, November 12-15, 2000, 257–268. https://doi.org/10.1145/378993.379247

Rotenberg, E., Jacobson, Q., & Smith, J. (1999). A study of control independence in superscalar processors. FIFTH INTERNATIONAL SYMPOSIUM ON HIGH-PERFORMANCE COMPUTER ARCHITECTURE, PROCEEDINGS, pp. 115–124. https://doi.org/10.1109/hpca.1999.744346

Rotenberg, E., Bennett, S., & Smith, J. E. (1999). A trace cache microarchitecture and evaluation. IEEE TRANSACTIONS ON COMPUTERS, 48(2), 111–120. https://doi.org/10.1109/12.752652

Rotenberg, E. (1999). AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. Digest of papers: Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing: June 15-18, 1999, Madison, Wisconsin, USA, 84–91. https://doi.org/10.1109/ftcs.1999.781037

Rotenberg, E., & Smith, J. (1999). Control independence in trace processors. 32ND ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, (MICRO-32), PROCEEDINGS, pp. 4–15. https://doi.org/10.1109/micro.1999.809438

Jacobson, Q., Rotenberg, E., & Smith, J. E. (1997). Path-based next trace prediction. THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, pp. 14–23. https://doi.org/10.1109/micro.1997.645793

Rotenberg, E., Jacobson, Q., Sazeides, Y., & Smith, J. (1997). Trace processors. THIRTIETH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, PROCEEDINGS, pp. 138–148. https://doi.org/10.1109/micro.1997.645805

Jacobsen, E., Rotenberg, E., & Smith, J. E. (1996). Assigning confidence to conditional branch predictions. PROCEEDINGS OF THE 29TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE - MICRO-29, pp. 142–152. https://doi.org/10.1109/micro.1996.566457

Rotenberg, E., Bennett, S., & Smith, J. E. (1996). Trace cache: A low latency approach to high bandwidth instruction fetching. PROCEEDINGS OF THE 29TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE - MICRO-29, pp. 24–34. https://doi.org/10.1109/micro.1996.566447