@inproceedings{liu_jiang_solihin_2010, title={Understanding how off-chip memory bandwidth partitioning in chip multiprocessors affects system performance}, DOI={10.1109/hpca.2010.5416655}, abstractNote={Chip Multi-Processor (CMP) architectures have recently become a mainstream computing platform. Recent CMPs allow cores to share expensive resources, such as the last level cache and off-chip pin bandwidth. To improve system performance and reduce the performance volatility of individual threads, last level cache and off-chip bandwidth partitioning schemes have been proposed. While how cache partitioning affects system performance is well understood, little is understood regarding how bandwidth partitioning affects system performance, and how bandwidth and cache partitioning interact with one another. In this paper, we propose a simple yet powerful analytical model that gives us an ability to answer several important questions: (1) How does off-chip bandwidth partitioning improve system performance? (2) In what situations the performance improvement is high or low, and what factors determine that? (3) In what way cache and bandwidth partitioning interact, and is the interaction negative or positive? (4) Can a theoretically optimum bandwidth partition be derived, and if so, what factors affect it? We believe understanding the answers to these questions is very valuable to CMP system designers in coming up with strategies to deal with the scarcity of off-chip bandwidth in future CMPs with many cores on a chip.}, booktitle={International symposium on high-performance computer}, author={Liu, F. and Jiang, X. W. and Solihin, Y.}, year={2010}, pages={57–68} }
 @article{liu_solihin_2010, title={Understanding the Behavior and Implications of Context Switch Misses}, volume={7}, ISSN={["1544-3973"]}, DOI={10.1145/1880043.1880048}, abstractNote={One of the essential features in modern computer systems is context switching, which allows multiple threads of execution to time-share a limited number of processors. While very useful, context switching can introduce high performance overheads, with one of the primary reasons being the cache perturbation effect. Between the time a thread is switched out and when it resumes execution, parts of its working set in the cache may be perturbed by other interfering threads, leading to (context switch) cache misses to recover from the perturbation.}, number={4}, journal={ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION}, author={Liu, Fang and Solihin, Yan}, year={2010}, month={Dec} }