@article{samberg_carlin_bradshaw_colter_harmon_allen_hauser_bedair_2013, title={Effect of GaAs interfacial layer on the performance of high bandgap tunnel junctions for multijunction solar cells}, volume={103}, ISSN={["1077-3118"]}, DOI={10.1063/1.4819917}, abstractNote={The effect of the heterojunction interface on the performance of high bandgap InxGa1−xP:Te/Al0.6Ga0.4As:C tunnel junctions (TJs) was investigated. The insertion of 30 Å of GaAs:Te at the junction interface resulted in a peak current of 1000 A/cm2 and a voltage drop of ∼3 mV for 30 A/cm2 (2000× concentration). The presence of this GaAs interfacial layer also improved the uniformity across the wafer. Modeling results are consistent with experimental data and were used to explain the observed enhancement in TJ performance. This architecture could be used within multijunction solar cells to extend the range of usable solar concentration with minimal voltage drop.}, number={10}, journal={APPLIED PHYSICS LETTERS}, author={Samberg, Joshua P. and Carlin, C. Zachary and Bradshaw, Geoff K. and Colter, Peter C. and Harmon, Jeffrey L. and Allen, J. B. and Hauser, John R. and Bedair, S. M.}, year={2013}, month={Sep} }
 @inproceedings{hauser_carlin_harmon_bradshaw_samberg_colter_bedair_2013, title={Modeling an InGaP/AlGaAs tunnel junction containing an AlAs diffusion barrier}, DOI={10.1109/pvsc.2013.6744883}, abstractNote={Cost improvements in concentrated photovoltaic (CPV) systems can be achieved by operating at increased solar concentration. Current multijunction CPV systems are limited to about 1000× concentration by the performance of the tunnel junctions (TJ) which connect the subcells. The TJ requires materials which are doped in excess of 1019 cm-3 in order to operate effectively, and so are susceptible to diffusion during the growth of subsequent layers. This paper considers a tunnel junction comprised of tellurium doped n+-InGaP and carbon doped p+-AlGaAs with a several monolayers of AlAs at the interface. The diffusion profile of the dopants was found and used to calculate the tunneling current through a junction. Due to uncertainty in the diffusion constants of C and Te in the three layers, the tunneling current was calculated for several values of Dt. The diffusion constant ratio in the AlAs was taken as a fraction of the diffusion constant in the other two layers. A significant increase in peak tunneling current was seen for Dt>1×10-14 cm2 when a three monolayer thick AlAs barrier was present.}, booktitle={2013 ieee 39th photovoltaic specialists conference (pvsc)}, author={Hauser, J. and Carlin, Z. and Harmon, J. and Bradshaw, G. and Samberg, J. and Colter, P. and Bedair, S.}, year={2013}, pages={2082–2085} }
 @article{hauser_carlin_bedair_2010, title={Modeling of tunnel junctions for high efficiency solar cells}, volume={97}, ISSN={["1077-3118"]}, DOI={10.1063/1.3469942}, abstractNote={Ultrahigh efficiency, in the range of 40%, can be achieved in multijunction solar cells operating at high solar concentrations, larger than 100 suns. Critical to this approach are high band gap tunnel junctions that serve as electrically low loss interconnections between the cells. The purpose of this work is to theoretically model such wide band gap tunnel junctions and to explore the advantages of a staggered band line up for improving the peak tunnel current. Theoretical results are calculated for heterojunction diodes made of n+-InGaP/p+-AlGaAs over a range of doping levels. The results illustrate the advantage of a conduction band discontinuity in achieving low interconnect resistance for multijunction solar cells.}, number={4}, journal={APPLIED PHYSICS LETTERS}, author={Hauser, John R. and Carlin, Zach and Bedair, S. M.}, year={2010}, month={Jul} }
 @article{hauser_2005, title={A new and improved physics-based model for MOS transistors}, volume={52}, ISSN={["1557-9646"]}, DOI={10.1109/ted.2005.859623}, abstractNote={An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.}, number={12}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Hauser, JR}, year={2005}, month={Dec}, pages={2640–2647} }
 @article{young_zeitzoff_brown_bersuker_lee_hauser_2005, title={Intrinsic mobility evaluation of high-kappa gate dielectric transistors using pulsed I-d-V-g}, volume={26}, ISSN={["1558-0563"]}, DOI={10.1109/LED.2005.852746}, abstractNote={A novel intrinsic mobility extraction methodology for high-/spl kappa/ gate stacks that only requires a capacitance-voltage and pulsed I/sub d/-V/sub g/ measurement is demonstrated on SiO/sub 2/ and high-/spl kappa/ gate dielectric transistors and is benchmarked to other reported mobility extraction techniques. Fast transient charging effects in high-/spl kappa/ gate stacks are shown to cause the mobility extracted using conventional dc-based techniques to be lower than the intrinsic mobility.}, number={8}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Young, CD and Zeitzoff, P and Brown, GA and Bersuker, G and Lee, BH and Hauser, JR}, year={2005}, month={Aug}, pages={586–589} }
 @article{wartenberg_hauser_2005, title={Substrate voltage and accumulation-mode MOS varactor capacitance}, volume={52}, DOI={10.1109/TED.2005.850953}, abstractNote={To adjust the capacitance of an accumulation-mode MOS varactor, a voltage is applied to the drain/source with the gate grounded. In this novel arrangement, a voltage is applied to the gate V/sub gate/ and another to the substrate V/sub sub/ with the drain/source grounded. Applying V/sub sub/ between the p/sup +/-type substrate and the varactor's n-well adjusts the minimum capacitance C/sub min/ and flattens the overall capacitance-voltage (C-V) curve over a wide range of negative V/sub gate/. Measurements show the tuning range using V/sub sub/ to be as wide as that using V/sub gate/. By tuning with V/sub sub/, the capacitance C/sub min/ is constant over a range of negative V/sub gate/. In this region, it may be possible to apply a large ac signal on V/sub gate/ without modulating the capacitance. To illustrate this technique, C-V measurements of a MOS varactor are simulated in a differential LC-tank VCO circuit. Simulations show how adjusting both V/sub gate/ and V/sub sub/ alters the oscillation frequency.}, number={7}, journal={IEEE Transactions on Electron Devices}, author={Wartenberg, S. A. and Hauser, J. R.}, year={2005}, pages={1563–1567} }
 @article{lee_park_yoon_hauser_2004, title={Enhancing the durability of linen-like properties of low temperature mercerized cotton}, volume={74}, DOI={10.1177/004051750407400211}, abstractNote={ In order to develop durable linen-like cotton yam with low temperature mercerization, pretreatment methods ensuring efficient and uniform penetration of the low temperature alkali solution into cotton yarn are studied. Pretreatments consisting of an alkaline scouring at higher NaOH concentrations and of a cellulase treatment and subsequent alkaline scouring are evaluated for their efficiency in removing wax and enhancing absorptive properties. The cellulase treatment/alkaline scouring is more efficient at re moving wax than alkaline scouring at higher NaOH concentrations. The cellulase treat ment and subsequent alkaline scouring result in wax contents lower than 0.1%. The cellulase treatment appears to degrade the cellulose on the surface of the cotton fibers, making it more accessible to the scouring agent and making wax removal easier. Swelling and wetting times are compared to identify a pretreatment sufficient for developing linen-like cotton. In low temperature mercerization, the pretreatment consisting of cellu lase treatment and alkaline scouring yields a linen-like cotton yarn whose stiffness is durable to knitting, wet processing, and even ten laundering cycles. The durability appears to be sufficient for practical applications of the process for producing linen-like cotton. }, number={2}, journal={Textile Research Journal}, author={Lee, M. H. and Park, H. S. and Yoon, K. J. and Hauser, P. J.}, year={2004}, pages={146–154} }
 @article{wartenberg_hauser_2003, title={The epHEMT gate at microwave frequencies}, volume={51}, ISSN={["1557-9670"]}, DOI={10.1109/TMTT.2003.812573}, abstractNote={This paper examines the high-frequency behavior of the enhancement-mode pseudomorphic high electron-mobility transistor (epHEMT) gate. During this study, no bias was applied between the drain and source. Rather, the gate was forward biased with either the drain, source, or channel (drain and source connected together) grounded. While applying positive voltage V/sub g/ to the gate, one-port S-parameters were measured from 0.1 to 10 GHz and then converted to Z-parameters. Plotting the real part R of the impedance reveals two sharp peaks. The first peak occurs near the device threshold voltage for conduction in the InGaAs well. A second peak occurs at higher voltages where conduction begins to occur in the surface AlGaAs layer. An equivalent-circuit model is proposed to account for the epHEMT gate's high-frequency behavior and the proposed model is shown to be in good agreement with the experimental data.}, number={6}, journal={IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES}, author={Wartenberg, SA and Hauser, JR}, year={2003}, month={Jun}, pages={1718–1723} }
 @article{osburn_kim_han_de_yee_gannavaram_lee_lee_luo_zhu_et al._2002, title={Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go?}, volume={46}, ISSN={["2151-8556"]}, DOI={10.1147/rd.462.0299}, abstractNote={The vertical scaling requirements for gate stacks and for shallow extension junctions are reviewed. For gate stacks, considerable progress has been made in optimizing oxide/nitride and oxynitride dielectrics to reduce boron penetration and dielectric leakage compared to pure SiO2 in order to allow sub-2-nm dielectrics. Several promising alternative material candidates exist for 1-nm equivalent oxide thickness (EOT)-for example, HfO2, ZrO2, and their silicates. Nevertheless, considerable challenges lie ahead if we are to achieve an EOT of less than 0.5 nm. If only a single molecular interface layer of oxide is needed to preserve high channel mobility, it seems likely that an EOT of 0.4-0.5 nm would represent the physical limit of dielectric scaling, but even then with a very high leakage (∼105 A/cm2). For junctions, the main challenge lies in providing low parasitic series resistance as depths are scaled in order to reduce short-channel effects. Because contacts are ultimately expected to dominate the parasitic resistance, low-barrier-height contacts and/or very heavily doped junctions will be required. While ion implantation and annealing processes can certainly be extended to meet the junction-depth and series-resistance requirements for additional generations, alternative low-temperature deposition processes that produce either metastably or extraordinarily activated, abruptly doped regions seem better suited to solve the contact resistance problem.}, number={2-3}, journal={IBM JOURNAL OF RESEARCH AND DEVELOPMENT}, author={Osburn, CM and Kim, I and Han, SK and De, I and Yee, KF and Gannavaram, S and Lee, SJ and Lee, CH and Luo, ZJ and Zhu, W and et al.}, year={2002}, pages={299–315} }
 @article{weintraub_vogel_hauser_yang_misra_wortman_ganem_masson_2001, title={Study of low-frequency charge pumping on thin stacked dielectrics}, volume={48}, ISSN={["1557-9646"]}, DOI={10.1109/16.974700}, abstractNote={The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO/sub 2/ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO/sub 2/ dielectrics to thin stacked gate dielectrics are discussed.}, number={12}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Weintraub, CE and Vogel, E and Hauser, JR and Yang, N and Misra, V and Wortman, JJ and Ganem, J and Masson, P}, year={2001}, month={Dec}, pages={2754–2762} }
 @article{min_lamb_hauser_2001, title={Time-dependent Si etch behavior and its effect on oxide/Si selectivity in CF4+D-2 electron cyclotron resonance plasma etching}, volume={19}, ISSN={["1071-1023"]}, DOI={10.1116/1.1371318}, abstractNote={Transient poly-Si etching behavior in CF4+D2 electron cyclotron resonance plasmas containing different D2 proportions was investigated. Higher D2 proportions resulted in lower atomic F and higher CF2 concentration in the plasma, as evidenced by optical emission spectroscopy (OES), and in greater oxide-to-Si etch selectivity. A high initial poly-Si etch rate that declined very rapidly to a finite-steady-state value was observed for plasma etching under conditions giving low (3:1) oxide-to-Si etch selectivity. In contrast, a lower initial etch rate that declined to approximately zero over a longer (∼45 s) period was observed for poly-Si etching under plasma conditions giving (∼15:1) selectivity. In the latter case, Si consumption during overetching would be significantly underestimated if calculated on the basis of the conventional 60 s selectivity ration. X-ray photoelectron spectroscopy analysis indicated that a thick, more F-deficient fluorocarbon film was deposited on Si under the high-selectivity etching conditions. Real-time SiF4 and atomic F signals, which were measured during SiO2 etching using OES and mass spectroscopy, respectively, evidenced significantly different end-point trends for the high- and low-selectivity etching conditions. These trends are interpreted in light of the transient etching behavior observed for poly-Si under equivalent plasma conditions.}, number={3}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B}, author={Min, K and Lamb, HH and Hauser, JR}, year={2001}, pages={695–700} }
 @article{ahmed_wortman_hauser_2000, title={A two-dimensional numerical simulation of pulsed drain current transients in weak inversion and application to interface trap characterization on small geometry MOSFETs with ultrathin oxides}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.877189}, abstractNote={Based on two-dimensional (2-D) numerical simulation, a pulsed-drain current (PDC) measurement technique in weak inversion is investigated as an alternative to the standard charge-pumping technique for the extraction of interface trap density using small geometry MOSFETs. The PDC technique was found particularly useful for small MOSFETs with sub-20 /spl Aring/ oxides to avoid high gate tunneling current effects. The numerical simulation results are in excellent agreement with the simple analytical expressions used in the PDC technique.}, number={11}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Wortman, JJ and Hauser, JR}, year={2000}, month={Nov}, pages={2236–2237} }
 @article{ahmed_ibok_hauser_2000, title={Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides}, volume={36}, ISSN={["1350-911X"]}, DOI={10.1049/el:20001160}, abstractNote={The parasitic accumulation capacitance attenuation in MOS structures with hyper-thin oxides has been modelled using a distributed RC network. The simple analytic model is in excellent agreement with a two-dimensional numerical simulation and experimental data.}, number={20}, journal={ELECTRONICS LETTERS}, author={Ahmed, K and Ibok, E and Hauser, J}, year={2000}, month={Sep}, pages={1699–1700} }
 @article{ahmed_ibok_bains_chi_ogle_wortman_hauser_2000, title={Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.848276}, abstractNote={In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n/sup +/ poly-SiO/sub 2/-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 /spl Aring/ have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 /spl Aring/ over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 /spl Aring/ for thickness 31-47 /spl Aring/. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 /spl Aring/ over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 /spl Aring/).}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Bains, G and Chi, D and Ogle, B and Wortman, JJ and Hauser, JR}, year={2000}, month={Jul}, pages={1349–1354} }
 @article{wang_parker_hodge_croswell_yang_misra_hauser_2000, title={Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks}, volume={21}, ISSN={["0741-3106"]}, DOI={10.1109/55.830971}, abstractNote={In this work, we demonstrate that the magnitude of flatband voltage (V/sub FB/) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Wang, ZG and Parker, CG and Hodge, DW and Croswell, RT and Yang, N and Misra, V and Hauser, JR}, year={2000}, month={Apr}, pages={170–172} }
 @article{yang_henson_hauser_wortman_2000, title={Estimation of the effects of remote charge scattering on electron mobility of n-MOSFET's with ultrathin gate oxides}, volume={47}, ISSN={["1557-9646"]}, DOI={10.1109/16.822292}, abstractNote={The effects of remote charge scattering on the electron mobility of n-MOSFETs with ultrathin gate oxides from 1.5 nm to 3.2 nm have been estimated. By calculating the scattering rate of the two-dimensional (2-D) electron gas at the Si/silicon dioxide interface due to the ionized doping impurities at the poly-Si/silicon dioxide interface, the remote charge scattering mobility has been calculated. Electron mobility measured from the n-MOSFETs with ultrathin gate oxides has been used to extract several known mobility components. These mobility components have been compared to the calculated remote charge scattering mobility. From these comparisons, it is clear that the overall electron mobility is not severely degraded by remote charge scattering for the oxide thickness studied.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={2000}, month={Feb}, pages={440–447} }
 @article{ahmed_de_osburn_wortman_hauser_2000, title={Limitations of the modified shift-and-ratio technique for extraction of the bias dependence of L-eff and R-sd of LDD MOSFET's}, volume={47}, ISSN={["0018-9383"]}, DOI={10.1109/16.831010}, abstractNote={The purpose of this study, based on two-dimensional (2-D) simulation, was to scale effective channel length and series resistance extraction routines for sub-100 nm CMOS devices. We demonstrate that L/sub eff/- and R/sub sd/-gate-bias dependence extracted using a modified shift-and-ratio (M-S&R) method may not give accurate results because of a nonnegligible effective mobility dependence on gate bias. Using a reasonable gate bias-dependent mobility model, one observes a finite V/sub g/ dependence of L/sub eff/ and R/sub sd/ even for devices with degenerately doped drain junction.}, number={4}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and De, I and Osburn, C and Wortman, J and Hauser, J}, year={2000}, month={Apr}, pages={891–895} }
 @inbook{holten_hauser_kim_lynch_2000, title={Overview of semiconductor devices}, booktitle={Handbook of semiconductor manufacturing technology}, publisher={New York: Marcel Dekker}, author={Holten, W. C. and Hauser, J. R. and Kim, K. W. and Lynch, W. T.}, editor={Y. Nishi and Doering, R.Editors}, year={2000} }
 @article{carter_hauser_nemanich_2000, title={Surface residue island nucleation in anhydrous HF/alcohol vapor processing of Si surfaces}, volume={147}, ISSN={["0013-4651"]}, DOI={10.1149/1.1393929}, abstractNote={Anhydrous HF/methanol vapor-phase chemistries were employed to etch SiO 2 /Si surfaces at low pressure (5-50 Torr) and ambient temperature. The oxides on Si were formed from the following: (1) RCA chemical cleaning and (ii) UV-ozone treatment. Atomic force microscopy (AFM) and lateral force microscopy (LFM) were used to analyze the HF vapor-cleaned Si surfaces. AFM/LFM displayed residue islands distributed randomly upon the Si surface as a result of vapor-phase cleaning. As a result of etching RCA chemical oxides, the average lateral dimension of the residue islands is 40 nm and the average height of the islands is 6 nm. As a result of etching UV-ozone oxides, the average lateral dimension of the residue islands is 30 nm, and the average height of the islands is 3.5 nm. A decrease in residue island density is observed after the removal of a UV-ozone oxide compared to RCA chemical oxide removal. Secondary ion mass spectroscopy was used to characterize chemical impurities (O, C, F, and N) in the SiO 2 films and and the Si surface after HF vapor-phase cleaning. The constituents of the residue islands have been attributed to nitrogen impurities and silicon atoms imbedded in the passivating oxides. Results indicate that condensation of methanol vapor onto the bare Si surface, after oxide removal, is necessary for residue island formation. We suggest a model in which residue island nucleation occurs from nonvolatile N-Si complexes that form hydrogen bonds with methanol molecules and diffuse into the adsorbed alcohol layer. The molecular impurities then interact and form residue islands.}, number={9}, journal={JOURNAL OF THE ELECTROCHEMICAL SOCIETY}, author={Carter, RJ and Hauser, JR and Nemanich, RJ}, year={2000}, month={Sep}, pages={3512–3518} }
 @article{henson_ahmed_vogel_hauser_wortman_venables_xu_venables_1999, title={Estimating oxide thickness of tunnel oxides down to 1.4 nm using conventional capacitance-voltage measurements on MOS capacitors}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.753759}, abstractNote={High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Henson, WK and Ahmed, KZ and Vogel, EM and Hauser, JR and Wortman, JJ and Venables, RD and Xu, M and Venables, D}, year={1999}, month={Apr}, pages={179–181} }
 @article{ibok_ahmed_hao_ogle_wortman_hauser_1999, title={Gate quality ultrathin (2.5 nm) PECVD deposited oxynitride and nitrided oxide dielectrics}, volume={20}, ISSN={["0741-3106"]}, DOI={10.1109/55.784446}, abstractNote={Ultrathin oxynitride using plasma assisted deposition was evaluated against thermal oxide and nitrided thermal oxide as an alternative direct tunneling gate dielectric to thermal oxide in the 2.5-nm regime. The oxynitride showed an enhanced high field effective mobility relative to the thermal oxide although the low field mobility was slightly depressed. The N/sub 2/O nitrided oxide showed an enhanced high field effective mobility with no degradation in low field mobility. The interface state density of the oxynitride was equivalent to that of the thermal and nitrided thermal oxides; a very welcome observation for this deposition chemistry and anneal conditions.}, number={9}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Ibok, E and Ahmed, K and Hao, MY and Ogle, B and Wortman, JJ and Hauser, JR}, year={1999}, month={Sep}, pages={442–444} }
 @article{ahmed_ibok_yeap_xiang_ogle_wortman_hauser_1999, title={Impact of tunnel currents and channel resistance on the characterization of channel inversion layer charge and polysilicon-gate depletion of sub-20-angstrom gate oxide MOSFET's}, volume={46}, ISSN={["0018-9383"]}, DOI={10.1109/16.777153}, abstractNote={This paper discusses the limitations on MOSFET test structures used in extracting the polysilicon gate doping from capacitance-voltage (C-V) analysis in strong inversion, especially for ultrathin gate oxides. It is shown that for sub-20-/spl Aring/ oxide MOS devices, transistors with channel lengths less than about 10 /spl mu/m will be needed to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length has been estimated using a new simple transmission-line-model of the terminal capacitance, which accounts for the nonnegligible gate tunneling current and finite channel resistance.}, number={8}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Ahmed, K and Ibok, E and Yeap, GCF and Xiang, Q and Ogle, B and Wortman, JJ and Hauser, JR}, year={1999}, month={Aug}, pages={1650–1655} }
 @article{misra_lazar_wang_wu_niimi_lucovsky_wortman_hauser_1999, title={Interfacial properties of ultrathin pure silicon nitride formed by remote plasma enhanced chemical vapor deposition}, volume={17}, number={4}, journal={Journal of Vacuum Science & Technology. B, Microelectronics and Nanometer Structures}, author={Misra, V. and Lazar, H. and Wang, Z. and Wu, Y. and Niimi, H. and Lucovsky, G. and Wortman, J. J. and Hauser, J. R.}, year={1999}, pages={1836–1839} }
 @article{yang_henson_hauser_wortman_1999, title={Modeling study of ultrathin gate oxides using direct tunneling current and capacitance-voltage measurements in MOS devices}, volume={46}, ISSN={["1557-9646"]}, DOI={10.1109/16.772492}, abstractNote={Using both quantum mechanical calculations for the silicon substrate and a modified WKB approximation for the transmission probability, direct tunneling currents across ultra-thin gate oxides of MOS structures have been modeled for electrons from the inversion layers in p-type Si substrates. The modeled direct tunneling currents have been compared to experimental data obtained from nMOSFET's with direct tunnel gate oxides. Excellent agreement between the model and experimental data for gate oxides as thin as 1.5 nm has been achieved. Advanced capacitance-voltage techniques have been employed to complement direct tunneling current modeling and measurements. With capacitance-voltage (C-V) techniques, direct tunneling currents can be used as a sensitive characterization technique for direct tunnel gate oxides. The effects of both silicon substrate doping concentration and polysilicon doping concentration on the direct tunneling current have also been studied as a function of applied gate voltage.}, number={7}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Yang, N and Henson, WK and Hauser, JR and Wortman, JJ}, year={1999}, month={Jul}, pages={1464–1471} }
 @article{shanware_massoud_vogel_henson_hauser_wortman_1999, title={Modeling the trends in valence-band electron tunneling in NMOSFETs with ultrathin SiO2 and SiO2/Ta2O5 dielectrics with oxide scaling}, volume={48}, ISSN={["1873-5568"]}, DOI={10.1016/s0167-9317(99)00392-5}, abstractNote={Gate oxide scaling in NMOSFETs causes electrons to tunnel from the conduction and valence bands of the silicon substrate in the direct-tunneling regime. In NMOSFETs, the tunneling of electrons from the substrate's valence band is a source of the substrate current IB and contributes to the gate current IG. Oxide thickness scaling leads to an increase in the substrate current IB and in the ratio IBIG of substrate to gate current. In this paper, we report the trends in the IBIG ratio due to oxide thickness scaling in ultrathin SiO2 and SiO2Ta2O5 composite gate dielectrics.}, number={1-4}, journal={MICROELECTRONIC ENGINEERING}, author={Shanware, A and Massoud, HZ and Vogel, E and Henson, K and Hauser, JR and Wortman, JJ}, year={1999}, month={Sep}, pages={295–298} }
 @article{shanware_massoud_acker_li_mirabedini_henson_hauser_wortman_1999, title={The effects of Ge content in poly-Si1-xGex gate material on the tunneling barrier in PMOS devices}, volume={48}, ISSN={["0167-9317"]}, DOI={10.1016/s0167-9317(99)00333-0}, abstractNote={The use of SiGe gates in MOSFET technology has promise as a single-gate material for both n- and p-channel MOSFETs. The Ge content in the gate, however, affects the gate energy band diagram. While Ge in the SiGe gate does not affect the conduction-band energy level, it is found to raise the valence-band energy level and reduce the gate bandgap. This change results in an increase in the gate current resulting mainly from the tunneling of electrons from the valence band of the gate in PMOSFETs. This paper reports on the effects of Ge content in SiGe gates on the tunneling characteristics of PMOSFETs.}, number={1-4}, journal={MICROELECTRONIC ENGINEERING}, author={Shanware, A and Massoud, HZ and Acker, A and Li, VZQ and Mirabedini, MR and Henson, K and Hauser, JR and Wortman, JJ}, year={1999}, month={Sep}, pages={39–42} }
 @article{srivastava_heinisch_vogel_parker_osburn_masnari_wortman_hauser_1998, title={Evaluation of 2.0 nm grown and deposited dielectrics in 0.1 mu m PMOSFETs}, volume={525}, ISBN={["1-55899-431-9"]}, ISSN={["0272-9172"]}, DOI={10.1557/proc-525-163}, abstractNote={ABSTRACT}, journal={RAPID THERMAL AND INTEGRATED PROCESSING VII}, author={Srivastava, A and Heinisch, HH and Vogel, E and Parker, C and Osburn, CM and Masnari, NA and Wortman, JJ and Hauser, JR}, year={1998}, pages={163–170} }
 @article{vogel_ahmed_hornung_henson_mclarty_lucovsky_hauser_wortman_1998, title={Modeled tunnel currents for high dielectric constant dielectrics}, volume={45}, ISSN={["0018-9383"]}, DOI={10.1109/16.678572}, abstractNote={The effect of dielectric constant and barrier height on the WKB modeled tunnel currents of MOS capacitors with effective oxide thickness of 2.0 nm is described. We first present the WKB numerical model used to determine the tunneling currents. The results of this model indicate that alternative dielectrics with higher dielectric constants show lower tunneling currents than SiO/sub 2/ at expected operating voltages. The results of SiO/sub 2//alternative dielectric stacks indicate currents which are asymmetric with electric field direction. The tunneling current of these stacks at low biases decreases with decreasing SiO/sub 2/ thickness. Furthermore, as the dielectric constant of an insulator increased, the effect of a thin layer of SiO/sub 2/ on the current characteristics of the dielectric stack increases.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Vogel, EM and Ahmed, KZ and Hornung, B and Henson, WK and McLarty, PK and Lucovsky, G and Hauser, JR and Wortman, JJ}, year={1998}, month={Jun}, pages={1350–1355} }
 @article{lucovsky_niimi_wu_parker_hauser_1998, title={Optimization of nitrided gate dielectrics by plasma-assisted and rapid thermal processing}, volume={16}, ISSN={["0734-2101"]}, DOI={10.1116/1.581291}, abstractNote={This article addresses several aspects of nitrogen atom (N atom) incorporation into ultrathin gate oxides including: (i) monolayer incorporation of N atoms at the Si–SiO2 interfaces to reduce tunneling currents and improve device reliability; and (ii) the incorporation of silicon nitride films into stacked oxide–nitride (ON) gate dielectrics to (a) increase the capacitance in ultrathin dielectrics without decreasing film thickness, and (b) suppress boron atom (B atom) diffusion from p+ polycrystalline Si gate electrodes through the dielectric layer to the Si substrate channel region. The results of this article demonstrate that these N-atom spatial distributions can be accomplished by low thermal budget, single wafer processing which includes (i) low-temperature (300 °C) plasma assisted oxidation, nitridation, and/or deposition to achieve the desired N-atom incorporation, followed by (ii) low thermal budget (30 s at 900 °C) rapid thermal annealing to promote chemical and structural bulk and interface relaxation.}, number={3}, journal={JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A}, author={Lucovsky, G and Niimi, H and Wu, Y and Parker, CR and Hauser, JR}, year={1998}, pages={1721–1729} }
 @article{parker_lucovsky_hauser_1998, title={Ultrathin oxide-nitride gate dielectric MOSFET's}, volume={19}, ISSN={["0741-3106"]}, DOI={10.1109/55.663529}, abstractNote={The first ultrathin oxide-nitride (O-N) gate dielectrics with oxide equivalent thickness of less than 2 nm have been deposited and characterized in n-MOSFET's. The O-N gates, deposited by remote plasma-enhanced CVD, demonstrate reduced gate leakage when compared with oxides of equivalent thickness while retaining comparable drive currents.}, number={4}, journal={IEEE ELECTRON DEVICE LETTERS}, author={Parker, CG and Lucovsky, G and Hauser, JR}, year={1998}, month={Apr}, pages={106–108} }
 @article{hauser_1997, title={Bias sweep rate effects on quasi-static capacitance of MOS capacitors}, volume={44}, ISSN={["0018-9383"]}, DOI={10.1109/16.585558}, abstractNote={MOS capacitance measurements are very fundamental characterization methods for MOS and FET structures. This paper discusses the effects of a finite bias sweep rate on quasi-static and high-frequency (HF) capacitance-voltage (C-V) measurements. As typically measured, a finite sweep rate causes the transition region from inversion to depletion of the quasistatic C-V curve to be shifted by several tenths of a volt along the bias voltage axis. The physical origin of this shift as well as a model to account for the effect is discussed. In order to understand quasi-static MOS C-V measurements and to extract fundamental parameters such as substrate doping density and polysilicon depletion effects from C-V measurements, these bias sweep rate effects must be understood and taken into account.}, number={6}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={Hauser, JR}, year={1997}, month={Jun}, pages={1009–1012} }
 @article{tian_kim_hauser_masnari_littlejohn_1995, title={Effects of profile doped elevated source/drain structures on deep-submicron MOSFETs}, volume={38}, ISSN={0038-1101}, url={http://dx.doi.org/10.1016/0038-1101(94)00160-H}, DOI={10.1016/0038-1101(94)00160-H}, abstractNote={Computer simulations have been carried out to systematically evaluate and compare device characteristics for various profile doped elevated source/drain (ESD) 0.25 μm channel-length MOSFET structures. In particular, characteristics for MOSFETs with a gradual profile doped ESD and for MOSFETs with an abrupt profile N+-N− doped ESD are examined in detail. Design considerations for key parameters related to the ESD formation (such as sidewall oxide width, elevation height and source/drain doping profile) and their influences on device characteristics are discussed. The results show the importance of ESD design parameters and structural optimization. They also indicate that the proposed gradual profile doped ESD MOSFETs can be as effective as the abrupt profile N+-N− doped ESD MOSFETs in achieving overall performance enhancement and reliability for deep-submicron device applications.}, number={3}, journal={Solid-State Electronics}, publisher={Elsevier BV}, author={Tian, H. and Kim, K.W. and Hauser, J.R. and Masnari, N.A. and Littlejohn, M.A.}, year={1995}, month={Mar}, pages={573–579} }
 @misc{hauser_sorrell_wortman_1995, title={Three-zone rapid thermal processing system utilizing wafer edge heating means}, volume={5,418,885}, number={1995 May 23}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Hauser, J. and Sorrell, F. and Wortman, J.}, year={1995} }
 @article{tian_hulfachor_ellis-monaghan_kim_littlejohn_hauser_masnari_1994, title={An evaluation of super-steep-retrograde channel doping for deep-submicron MOSFET applications}, volume={41}, ISSN={0018-9383}, url={http://dx.doi.org/10.1109/16.324605}, DOI={10.1109/16.324605}, abstractNote={Performance and reliability of deep-submicron MOSFET's employing super-steep-retrograde (SSR) channel doping configurations are examined using self-consistent Monte Carlo and drift-diffusion simulations. It is found that SSR channel doped MOSFET's provide increased current drive and reduced threshold voltage shift when compared with conventional MOSFET structures. However, they also display a relatively higher substrate current and interface state generation rate. The physical mechanisms of performance enhancement/degradation and design tradeoffs for SSR channel doped MOSFET's are discussed. >}, number={10}, journal={IEEE Transactions on Electron Devices}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Tian, H. and Hulfachor, R.B. and Ellis-Monaghan, J.J. and Kim, K.W. and Littlejohn, M.A. and Hauser, J.R. and Masnari, N.A.}, year={1994}, pages={1880–1882} }
 @article{masnari_hauser_lucovsky_maher_markunas_ozturk_wortman_1993, title={CENTER FOR ADVANCED ELECTRONIC MATERIALS PROCESSING}, volume={81}, ISSN={["0018-9219"]}, DOI={10.1109/JPROC.1993.752025}, abstractNote={Microelectronics manufacturing technology is rapidly moving toward integrated circuits with submicron minimum feature sizes. This is being driven by the development of devices and circuits with reduced device lateral dimensions, increased density per chip, thinner material layers, increased use of the vertical dimension (three-dimensional circuits), low volume/fast tumaround design (ASIC's), increased use of heterojunctions, mixed material technologies, and quantum-based device structures. These trends require precise control of thin layers processed on wafers and a need for lower temperature processing or a lower overall thermal budget}, number={1}, journal={PROCEEDINGS OF THE IEEE}, author={MASNARI, NA and HAUSER, JR and LUCOVSKY, G and MAHER, DM and MARKUNAS, RJ and OZTURK, MC and WORTMAN, JJ}, year={1993}, month={Jan}, pages={42–59} }
 @misc{wortman_sorrell_hauser_fordham_1993, title={Conical rapid thermal processing apparatus}, volume={5,253,324}, number={1993 Oct. 12}, publisher={Washington, DC: U.S. Patent and Trademark Office}, author={Wortman, J. and Sorrell, F. and Hauser, J. and Fordham, M.}, year={1993} }
 @book{glen l. urban_1993, title={Design and marketing of new products}, publisher={Englewood Cliffs, NJ: Prentice Hall}, author={Glen L. Urban, John R. Hauser}, year={1993} }
 @book{glen l. urban_dholakia_1987, title={Essentials of new product management}, publisher={Englewood Cliffs, NJ: Prentice-Hall}, author={Glen L. Urban, John R. Hauser and Dholakia, Nikhilesh}, year={1987} }
 @article{arora_hauser_roulston_1982, title={ELECTRON AND HOLE MOBILITIES IN SILICON AS A FUNCTION OF CONCENTRATION AND TEMPERATURE}, volume={29}, ISSN={["0018-9383"]}, DOI={10.1109/t-ed.1982.20698}, abstractNote={An analytical expression has been derived for the electron and hole mobility in silicon based on both experimental data and modified Brooks-Herring theory of mobility. The resulting expression allows one to obtain electron and hole mobility as a function of concentration up to\sim 10^{20}cm-3in an extended and continuous temperature range (250-500 K) within ± 13 percent of the reported experimental values.}, number={2}, journal={IEEE TRANSACTIONS ON ELECTRON DEVICES}, author={ARORA, ND and HAUSER, JR and ROULSTON, DJ}, year={1982}, pages={292–295} }
 @book{glen l. urban_1980, title={Design and marketing of new products}, publisher={Englewood Cliffs, NJ: Prentice-Hall}, author={Glen L. Urban, John R. Hauser}, year={1980} }
 @article{littlejohn_hauser_glisson_1977, title={VELOCITY-FIELD CHARACTERISTICS OF GAAS WITH GAMMA-6(C)-L6(C)-X6(C) CONDUCTION-BAND ORDERING}, volume={48}, ISSN={["0021-8979"]}, DOI={10.1063/1.323516}, abstractNote={This paper describes Monte Carlo calculations of velocity-field characteristics for GaAs using the recent experimental conduction-band ordering of Aspnes, which places the Lc6(111) conduction-band minima lower in energy than the Xc6(100) minima. These calculations use intervalley deformation potentials which give the best fit to recent high-field drift velocity measurements, and at the same time give good agreement with accepted peak velocity and threshold field values.}, number={11}, journal={JOURNAL OF APPLIED PHYSICS}, author={LITTLEJOHN, MA and HAUSER, JR and GLISSON, TH}, year={1977}, pages={4587–4590} }