Hancheng Wu

Works (4)

Updated: November 2nd, 2023 05:01

2022 article

Accelerating Random Forest Classification on GPU and FPGA

51ST INTERNATIONAL CONFERENCE ON PARALLEL PROCESSING, ICPP 2022.

By: M. Shah n, R. Neff n, H. Wu n, M. Minutoli *, A. Tumeo * & M. Becchi n

author keywords: random forest classification; GPU; FPGA
TL;DR: This work proposes a hierarchical memory layout suitable to the GPU/FPGA memory hierarchy, and designs three RF classification code variants based on that layout, and investigates GPU- and FPGA-specific considerations for these kernels. (via Semantic Scholar)
UN Sustainable Development Goal Categories
Source: Web Of Science
Added: October 30, 2023

2020 article

Evaluating Thread Coarsening and Low-cost Synchronization on Intel Xeon Phi

2020 IEEE 34TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM IPDPS 2020, pp. 1018–1029.

By: H. Wu n & M. Becchi n

author keywords: SIMT; manycore processors; Intel Xeon Phi; thread coarsening; synchronization
TL;DR: This work explores thread coarsening as a way to remap the work to the available cores and vector lanes, and proposes low- overhead synchronization primitives, such as atomic operations and barriers, which transparently apply to threads mapped to the same or different VPUs and x86 cores. (via Semantic Scholar)
Source: Web Of Science
Added: June 10, 2021

2018 article

A Compiler Framework for Fixed-topology Non-deterministic Finite Automata on SIMD Platforms

2018 IEEE 24TH INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED SYSTEMS (ICPADS 2018), pp. 507–516.

By: M. Nourian, H. Wu & M. Becchi

author keywords: Automata Processing; NFAs; SIMD; GPUs; Intel Xeon Phi platforms
Source: Web Of Science
Added: April 22, 2019

2018 article

Compiling SIMT Programs on Multi- and Many-core Processors with Wide Vector Units: A Case Study with CUDA

2018 IEEE 25TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING (HIPC), pp. 123–132.

By: H. Wu n, J. Ravi n & M. Becchi n

author keywords: Xeon Phi; hybrid MIMD/SIMD systems; CUDA; SIMT; vectorization
TL;DR: A set of compiler techniques are proposed to transform programs written using a SIMT programming model (a subset of CUDA C) into code that leverages both the x86 cores and the vector units of a hybrid MIMD/SIMD architecture, thus providing programmability, high system utilization and performance. (via Semantic Scholar)
Source: Web Of Science
Added: June 17, 2019

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