@article{stevens_pan_ravichandiran_franzon_2023, title={Chiplet Set For Artificial Intelligence}, ISSN={["2164-0157"]}, DOI={10.1109/3DIC57175.2023.10154953}, abstractNote={The design reuse strategy has significantly shortened the time required to create complex System on Chips (SoCs). However, when introducing new intellectual properties (IPs), the monolithic SoC methodology requires a re-run of system-level validation steps, incurring significant costs. Partitioning the design into chiplets over an interposer would mitigate these issues by consigning the IP updates to the individual chiplet. This paper presents a chipletized design used for Artificial Intelligence (AI). This design details a scalable AI chiplet set, along with Central Processing Units (CPUs). The AI chiplet set includes an Long Short Term Memory (LSTM) Application Specific Instruction Set Processor (ASIP) for accelerating inference and training and an Sparse Convolution Neural Network (SCNN) ASIP for accelerating inference through a zero-skipping technique. The CPUs control AI accelerators and handle general tasks. The accelerators and CPUs have an AXI crossbar Network on Chip (NoC) for memory and one for controlling the accelerators. This project has two phases: phase one, IP validation with an emulated interposer (No interposer, connect chiplets through back end of line (BEOL) metal layers), and phase two, connecting validated IP through an interposer. This paper focuses on phase one, which uses the United Semiconductor Japan Co. (USJC) 55 nm LP process to fabricate the design. The chiplets' clock frequencies range from 200 - 400 MHz.}, journal={2023 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE, 3DIC}, author={Stevens, Joshua A. and Pan, Tse-Han and Ravichandiran, Prasanth Prabu and Franzon, Paul D.}, year={2023} }
 @article{franzon_davis_rotenberg_stevens_lipa_nigussie_pan_baker_schabel_dey_et al._2021, title={Design for 3D Stacked Circuits}, ISSN={["2380-9248"]}, DOI={10.1109/IEDM19574.2021.9720553}, abstractNote={2.5D and 3D technologies can give rise to a node equivalent of scaling due to improved connectivity. Aggressive exploitation scenarios include functional partitioning, circuit partitioning, logic on DRAM, design obfuscation and modular chiplets. Design issues that need to be addressed in pursuing such exploitations include thermal management, design for test and computer aided design.}, journal={2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)}, author={Franzon, P. and Davis, W. and Rotenberg, E. and Stevens, J. and Lipa, S. and Nigussie, T. and Pan, H. and Baker, L. and Schabel, J. and Dey, S. and et al.}, year={2021} }