Works (3)
Updated: July 5th, 2023 15:35
2018 journal article
Exploring the Tradeoffs of Application-Specific Processing
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 8(3), 531–542.
author keywords: ASIP; SIMD; CGRA; processing-in-memory; processing-near-memory; HTM; sparsey; artificial neural networks
TL;DR:
This work proposes an architecture that combines existing processing schemes utilizing CGRAs for dynamic data path configuration as a means to add flexibility and reusability to data-centric acceleration and presents a CGRA architecture for mapping functional accelerators operating at 500 MHz in 32 nm.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, NC State University Libraries
Added: October 16, 2018
2017 conference paper
H3 (heterogeneity in 3D): A logic-on-logic 3D-stacked heterogeneous multi-core processor
2017 IEEE International Conference on Computer Design (ICCD), 145–152.
Event: 2017 IEEE International Conference on Computer Design (ICCD) at Boston, MA on November 5-8, 2017
TL;DR:
The H3 chip is presented, that uses 3D die stacking and novel microarchitecture to implement a heterogeneous multi-core processor (HMP) with low-latency fast thread migration capabilities and can reduce power consumption of benchmarks by up to 26%.
(via Semantic Scholar)
UN Sustainable Development Goal Categories
7. Affordable and Clean Energy
(OpenAlex)
Sources: Web Of Science, NC State University Libraries
Added: August 6, 2018
conference paper
Processor-in-memory support for artificial neural networks
Schabel, J., Baker, L., Dey, S., Li, W. F., & Franzon, P. D. 2016 IEEE International Conference on Rebooting Computing (icrc).
Source: NC State University Libraries
Added: August 6, 2018
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