John Ravi

College of Engineering

Works (9)

Updated: September 19th, 2023 05:01

2023 article

Evaluating Asynchronous Parallel I/O on HPC Systems

2023 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM, IPDPS, pp. 211–221.

By: J. Ravi n, S. Byna *, Q. Koziol *, H. Tang * & M. Becchi n

author keywords: Performance Evaluation; Modeling; Asynchronous; I/O; Parallel I/O
TL;DR: A systematic study of various factors affecting the performance and efficacy of asynchronous I/O in HPC systems is performed, a performance model is developed to estimate the aggregateI/O bandwidth achievable by iterative applications using synchronous and asynchronous I-O based on past observations, and the performance of the recently developed asynchronous I /O feature of a parallel I/o library (HDF5) is evaluated using benchmarks and real-world science applications. (via Semantic Scholar)
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Source: Web Of Science
Added: September 5, 2023

2023 article

Runway: In-transit Data Compression on Heterogeneous HPC Systems

2023 IEEE/ACM 23RD INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND INTERNET COMPUTING, CCGRID, pp. 229–239.

By: J. Ravi n, S. Byna * & M. Becchi n

author keywords: Object Data Management; In-transit Computation; Heterogeneous Resources
TL;DR: This paper introduces Runway, a runtime framework that enables computation on in-transit data with an object storage abstraction that is designed to be extensible to execute user-defined functions at runtime. (via Semantic Scholar)
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Source: Web Of Science
Added: August 21, 2023

2023 article

Runway: In-transit Data Compression on Heterogeneous HPC Systems

2023 IEEE/ACM 23RD INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND INTERNET COMPUTING WORKSHOPS, CCGRIDW, pp. 340–342.

By: J. Ravi n, S. Byna * & M. Becchi n

author keywords: Object Data Management; In-transit Computation; Heterogeneous Resources
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Source: Web Of Science
Added: September 18, 2023

2022 article

HDF5 Cache VOL: Efficient and Scalable Parallel I/O through Caching Data on Node-local Storage

2022 22ND IEEE/ACM INTERNATIONAL SYMPOSIUM ON CLUSTER, CLOUD AND INTERNET COMPUTING (CCGRID 2022), pp. 61–70.

By: H. Zheng *, V. Vishwanath *, Q. Koziol *, H. Tang *, J. Ravi n, J. Mainzer*, S. Byna *

author keywords: Parallel IO; storage hierarchy; node-local storage; HDF5; Caching; Prefetching; deep learning
TL;DR: This paper designed this to move data asynchronously between the caching storage layer and a parallel file system to overlap the data movement overhead in performing I/O with compute phases, thus achieving faster time-to-solution in scientific simulations. (via Semantic Scholar)
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Added: September 29, 2022

2021 journal article

Molecular organization of cytokinesis node predicts the constriction rate of the contractile ring

JOURNAL OF CELL BIOLOGY, 220(3).

By: K. Bellingham-Johnstun n, E. Anders n, J. Ravi n, C. Bruinsma n & C. Laplante n

MeSH headings : Acetyltransferases / metabolism; Actin Cytoskeleton / metabolism; Actins / metabolism; Cytokinesis; Models, Biological; Mutation / genetics; Schizosaccharomyces / cytology; Schizosaccharomyces / metabolism; Schizosaccharomyces pombe Proteins / genetics; Schizosaccharomyces pombe Proteins / metabolism; Time Factors
TL;DR: This work leveraged the Δmid1 contractile ring assembly mechanism to determine how two distinct molecular organizations, nodes versus strands, can yield functional contractile rings and establishes a predictive correlation between the molecular organization of nodes and the behavior of the contractiles ring. (via Semantic Scholar)
Source: Web Of Science
Added: March 29, 2021

2021 article

PILOT: a Runtime System to Manage Multi-tenant GPU Unified Memory Footprint

2021 IEEE 28TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING, DATA, AND ANALYTICS (HIPC 2021), pp. 442–447.

By: J. Ravi n, T. Nguyen n , H. Zhou n  & M. Becchi n

TL;DR: A proposed three methods to transparently mitigate memory interference through kernel preemption and scheduling policies are proposed, which would enable new OS-managed scheduling policies to be implemented for GPU kernels to dynamically handle resource contention and offer consistent performance. (via Semantic Scholar)
Sources: Web Of Science, NC State University Libraries, ORCID
Added: May 2, 2022

2021 journal article

Transparent Asynchronous Parallel I/O Using Background Threads

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 33(4), 891–902.

By: H. Tang *, Q. Koziol *, J. Ravi n & S. Byna *

author keywords: Task analysis; Connectors; Libraries; Instruction sets; Computational modeling; Monitoring; Middleware; Asynchronous I; O; parallel I; O; background threads
TL;DR: An asynchronous I/O framework is presented that supports all types ofI/O operations, manages data dependencies transparently and automatically, provides implicit and explicit modes for application flexibility, and error information retrieval, and is implemented in HDF5. (via Semantic Scholar)
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Added: November 1, 2021

2020 article

GPU Direct I/O with HDF5

PROCEEDINGS OF 2020 IEEE/ACM FIFTH INTERNATIONAL PARALLEL DATA SYSTEMS WORKSHOP (PDSW 2020), pp. 28–33.

By: J. Ravi n, S. Byna * & Q. Koziol *

author keywords: GPU I/O; NVIDIA GPUDirect Storage (GDS); HDF5 GDS Virtual File Driver (VFD)
TL;DR: The effort of integrating GDS with HDF5, the top I/O library at NERSC and at DOE leadership computing facilities, is described and this integration using aHDF5 Virtual File Driver (VFD), which provides a file system abstraction to the application that allows HDF 5 applications to perform I/o without the need to move data between CPUs and GPUs explicitly. (via Semantic Scholar)
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Source: Web Of Science
Added: August 9, 2021

2018 article

Compiling SIMT Programs on Multi- and Many-core Processors with Wide Vector Units: A Case Study with CUDA

2018 IEEE 25TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING (HIPC), pp. 123–132.

By: H. Wu n, J. Ravi n & M. Becchi n

author keywords: Xeon Phi; hybrid MIMD/SIMD systems; CUDA; SIMT; vectorization
TL;DR: A set of compiler techniques are proposed to transform programs written using a SIMT programming model (a subset of CUDA C) into code that leverages both the x86 cores and the vector units of a hybrid MIMD/SIMD architecture, thus providing programmability, high system utilization and performance. (via Semantic Scholar)
Source: Web Of Science
Added: June 17, 2019

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